On Wed, 5 Jun 2019 at 14:42, Greg Kurz wrote:
>
> On Tue, 4 Jun 2019 15:34:56 +0800
> elohi...@gmail.com wrote:
>
> > From: Xie Yongji
> >
> > Besides virtio 1.0 transitional devices, we should also
> > set "start_on_kick" flag for legacy devices (virtio 0.9).
> >
> > Signed-off-by: Xie Yongji
Lidong Chen 于2019年6月5日周三 下午2:23写道：
> The check for poll_fds in g_assert() was incorrect. The correct assertion
> should check "n_poll_fds + w->num <= ARRAY_SIZE(poll_fds)" because the
> subsequent for-loop is doing access to poll_fds[n_poll_fds + i] where i
> is in [0, w->num).
>
> Signed-off-by:
On Tue, 4 Jun 2019 15:34:56 +0800
elohi...@gmail.com wrote:
> From: Xie Yongji
>
> Besides virtio 1.0 transitional devices, we should also
> set "start_on_kick" flag for legacy devices (virtio 0.9).
>
> Signed-off-by: Xie Yongji
> ---
Patch looks good but it would be even better if applied
e
On Wed, Jun 05, 2019 at 09:08:28AM +0800, Wei Yang wrote:
> In case we gets a queued page, the order of block is interrupted. We may
> not rely on the complete_round flag to say we have already searched the
> whole blocks on the list.
>
> Signed-off-by: Wei Yang
> ---
> migration/ram.c | 6 +
On 04/06/2019 22:23, Laurent Vivier wrote:
> This patch breaks something in the libcrypto.
>
> I've been able to reproduce the problem with Fedora 29:
>
> dnf install 'dnf-command(download)'
> dnf download --source coreutils-single
> rpm --verify coreutils-8.30-7.fc29.src.rpm
> error: coreutils-
The check for poll_fds in g_assert() was incorrect. The correct assertion
should check "n_poll_fds + w->num <= ARRAY_SIZE(poll_fds)" because the
subsequent for-loop is doing access to poll_fds[n_poll_fds + i] where i
is in [0, w->num).
Signed-off-by: Lidong Chen
Reviewed-by: Liran Alon
Reviewed-
The v2 changes include the fix for the incorrect assertion for poll_fds
in util/main-loop.c according to the review comments from the previous
sd fixes.
Lidong Chen (2):
sd: Fix out-of-bounds assertions
util/main-loop: Fix incorrect assertion
hw/sd/sd.c | 4 ++--
util/main-loop.c | 2 +
Due to an off-by-one error, the assert statements allow an
out-of-bound array access.
Signed-off-by: Lidong Chen
Reviewed-by: Liam Merwick
Reviewed-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Li Qiang
Reviewed-by: Darren Kenny
---
hw/sd/sd.c | 4 ++--
1 file chang
From: David Brenken
Hello everyone,
in the scope of this patchset we added implementations for the following
instructions for the target TriCore:
QSEED, FTOIZ, UTOF
For the implementation of the QSEED instruction we wrote a test application to
record the QSEED results on the actual target. W
From: David Brenken
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/fpu_helper.c | 25 +
target/tricore/helper.h | 1 +
target/tricore/tra
From: Georg Hofstetter
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/tricore/translate.c b/tar
From: David Brenken
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/translate.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/
From: David Brenken
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/fpu_helper.c | 16
target/tricore/helper.h | 1 +
target/tricore/translate.c
From: Andreas Konopik
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/fpu_helper.c | 88 +
target/tricore/helper.h | 1 +
targ
On 6/4/2019 11:04 PM, Igor Mammedov wrote:
On Wed, 8 May 2019 14:17:22 +0800
Tao Xu wrote:
From: Liu Jingqi
This structure describes memory side cache information for memory
proximity domains if the memory side cache is present and the
physical device(SMBIOS handle) forms the memory side ca
Aarushi Mehta writes:
> Option only enumerates for hosts that support it.
Blank line here, please. Same in other patches.
> Signed-off-by: Aarushi Mehta
> ---
> qapi/block-core.json | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/qapi/block-core.json b/qapi/block-
Max Reitz writes:
> A snapshot is something that reflects the state of something at a
> certain point in time. It does not change.
>
> The file our snapshot commands create (or the node they install) is not
> a snapshot, as it does change over time. It is an overlay. We cannot
> do anything ab
On Tue, Jun 04, 2019 at 08:01:10PM +0100, Mark Cave-Ayland wrote:
> Nothing to see here - just Anton's patches fixing several issues with the
> VSX native endian conversion patches from 4.0, plus a related bug in xvxsigdp
> queued for 4.0 stable.
>
> Signed-off-by: Mark Cave-Ayland
Acked-by: Dav
On Tue, Jun 04, 2019 at 04:12:24PM -0600, Alex Williamson wrote:
> Backport of QEMU v4.1 commit for stable v4.0.1 release
>
> commit c87759ce876a7a0b17c2bf4f0b964bd51f0ee871
> Author: Alex Williamson
> Date: Tue May 14 14:14:41 2019 -0600
>
> q35: Revert to kernel irqchip
>
> Commit b
Patchew URL: https://patchew.org/QEMU/cover.1559638310.git.tgfb...@me.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH 0/2] ui/cocoa: Fix input device issues on Mojave
Type: series
Message-id: cover.1559638310.gi
Running tests on a development branch (I haven't touched chardev stuff,
I swear!); I ran into the below crash where s->ioc was NULL. I don't
have the time to investigate at this exact moment, so please excuse the
hasty report so I don't forget to tell someone.
It does not reproduce consistently, a
In case we gets a queued page, the order of block is interrupted. We may
not rely on the complete_round flag to say we have already searched the
whole blocks on the list.
Signed-off-by: Wei Yang
---
migration/ram.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/migration/ram.c b/migra
On Mojave, absolute input device, i.e. tablet, had trouble re-grabbing
the cursor in re-entry into the virtual screen area. In some cases,
the `window` property of NSEvent object was nil after cursor exiting from
window, hinting that the `-locationInWindow` method would return value in
screen coor
The following patches fixed issues of absolute and relative input devices on
macOS Mojave.
Chen Zhang (2):
ui/cocoa: Fix absolute input device grabbing issue on Mojave
ui/cocoa: Fix mouse grabbing in fullscreen mode for relative input
device
ui/cocoa.m | 50 +
In fullscreen mode, the window property of cocoaView may not be the key
window, and the current implementation would not re-grab cursor by left click
in fullscreen mode after ungrabbed in fullscreen mode with hot-key ctrl-opt-g.
This patch used value of isFullscreen as a short-cirtuit condition fo
Patchew URL:
https://patchew.org/QEMU/20190604203351.27778-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v4 00/39] tcg: Move the softmmu tlb to
CPUNegativeOffsetState
Type: series
Patchew URL:
https://patchew.org/QEMU/20190604203351.27778-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v4 00/39] tcg: Move the softmmu tlb to
CPUNegativeOffsetState
Type: series
Patchew URL:
https://patchew.org/QEMU/20190604203351.27778-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v4 00/39] tcg: Move the softmmu tlb to
CPUNegativeOffsetState
Backport of QEMU v4.1 commit for stable v4.0.1 release
commit c87759ce876a7a0b17c2bf4f0b964bd51f0ee871
Author: Alex Williamson
Date: Tue May 14 14:14:41 2019 -0600
q35: Revert to kernel irqchip
Commit b2fc91db8447 ("q35: set split kernel irqchip as default") changed
the default fo
On 08/01/2019 23:45, David Gibson wrote:
> From: Mark Cave-Ayland
>
> These helpers allow us to move VSR register values to/from the specified
> TCGv_i64
> argument.
>
> To prevent VSX helpers accessing the cpu_vsr array directly, add extra TCG
> temporaries as required.
>
> Signed-off-by: Mar
This changes the code generation for the tlb from e.g.
ldr ip, [r6, #-0x10]
ldr r2, [r6, #-0xc]
and ip, ip, r4, lsr #8
ldrd r0, r1, [r2, ip]!
ldr r2, [r2, #0x18]
to
ldrd r0, r1, [r6, #-0x10]
and r0, r0, r4,
Consolidate some boilerplate from foo_cpu_initfn.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 11 +++
target/alpha/cpu.c | 3 +--
target/arm/cpu.c| 3 +--
target/cris/cpu.
Cleanup in the boilerplate that each target must define.
Replace xtensa_env_get_cpu with env_archcpu. The combination
CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h"
so that the definition of env_cpu i
There was nothing armv7 specific about the bic+cmp sequence, however
looking at the set of guests more closely shows that the 8-bit immediate
operand for the bic can only be satisfied with one guest in tree:
baseline m-profile -- 10-bit pages with aligned 4-byte memory ops.
Therefore it does not se
This macro is now always empty, so remove it. This leaves the
entire contents of CPUArchState under the control of the guest
architecture.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 2 --
target/alpha/cpu.h | 3
Cleanup in the boilerplate that each target must define.
Replace uc32_env_get_cpu with env_archcpu. The combination
CPU(uc32_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
targe
Amusingly, we had already ignored the comment to keep this value
at the end of CPUState. This restores the minimum negative offset
from TCG_AREG0 for code generation.
For the couple of uses within qom/cpu.c, without NEED_CPU_H, add
a pointer from the CPUState object to the IcountDecr object withi
Cleanup in the boilerplate that each target must define.
Replace tricore_env_get_cpu with env_archcpu. The combination
CPU(tricore_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
Now that we have ArchCPU, we can define this generically,
in the one place that needs it.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/gen-icount.h | 2 ++
target/alpha/cpu.h| 1 -
target/arm/cpu.h | 2 --
target/cr
Cleanup in the boilerplate that each target must define.
Replace tilegx_env_get_cpu with env_archcpu. The combination
CPU(tilegx_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
t
This changes the code generation for the tlb from e.g.
ldur x0, [x19, #0xffe0]
ldur x1, [x19, #0xffe8]
and x0, x0, x20, lsr #8
add x1, x1, x0
ldr x0, [x1]
ldr x1, [x1, #0x18]
to
ldp x
We have for some time had code within the tcg backends to
handle large positive offsets from env. This move makes
sure that need not happen. Indeed, we are able to assert
at build time that simple offsets suffice for all hosts.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-of
Cleanup in the boilerplate that each target must define.
Replace riscv_env_get_cpu with env_archcpu. The combination
CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu.h |
Nothing in there so far, but all of the plumbing done
within the target ArchCPU state.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 24
include/exec/cpu-defs.h | 8
target/alpha/cpu.h
Cleanup in the boilerplate that each target must define.
Replace sh_env_get_cpu with env_archcpu. The combination
CPU(sh_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
Cleanup in the boilerplate that each target must define.
Replace mb_env_get_cpu with env_archcpu. The combination
CPU(mb_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Move cpu_mmu_index below the include of "exec/cpu-all.h",
so that the definition of env_archcpu is availabl
Cleanup in the boilerplate that each target must define.
Replace sparc_env_get_cpu with env_archcpu. The combination
CPU(sparc_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Cleanup in the boilerplate that each target must define.
Replace openrisc_env_get_cpu with env_archcpu. The combination
CPU(openrisc_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
--
Fix all of the coding style errors in this file at once.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/cris/op_helper.c | 817 +++-
1 file changed, 398 insertions(+), 419 deletions(-)
diff --gi
Cleanup in the boilerplate that each target must define.
Replace s390_env_get_cpu with env_archcpu. The combination
CPU(s390_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
targe
Cleanup in the boilerplate that each target must define.
Replace moxie_env_get_cpu with env_archcpu. The combination
CPU(moxie_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tar
Cleanup in the boilerplate that each target must define.
Replace ppc_env_get_cpu with env_archcpu. The combination
CPU(ppc_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/
Cleanup in the boilerplate that each target must define.
Replace cris_env_get_cpu with env_archcpu. The combination
CPU(cris_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
targe
Cleanup in the boilerplate that each target must define.
Replace x86_env_get_cpu with env_archcpu. The combination
CPU(x86_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/
Fix all of the coding style errors in this file at once.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/cris/mmu.c | 479 +++---
1 file changed, 237 insertions(+), 242 deletions(-)
diff --git a/target/cris/mmu.c b/target/cris/m
Cleanup in the boilerplate that each target must define.
Replace nios2_env_get_cpu with env_archcpu. The combination
CPU(nios2_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tar
Cleanup in the boilerplate that each target must define.
Replace arm_env_get_cpu with env_archcpu. The combination
CPU(arm_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/
This will replace foo_env_get_cpu with a generic definition.
No changes to the target specific code so far.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
Cleanup in the boilerplate that each target must define.
Replace hppa_env_get_cpu with env_archcpu. The combination
CPU(hppa_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
targe
Cleanup in the boilerplate that each target must define.
Replace mips_env_get_cpu with env_archcpu. The combination
CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/cpu.h
For all targets, into this new file move TARGET_LONG_BITS,
TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS,
TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.
Include this new file from exec/cpu-defs.h.
This now removes the somewhat odd requirement that target/arch/cpu.h
defines TARGET_LONG_BITS before
For all targets, do this just before including exec/cpu-all.h.
Reviewed-by: Peter Maydell
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/cris/cpu.h | 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.
Cleanup in the boilerplate that each target must define.
Replace m68k_env_get_cpu with env_archcpu. The combination
CPU(m68k_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux
Now that we have both ArchCPU and CPUArchState, we can define
this generically instead of via macro in each target's cpu.h.
Reviewed-by: Peter Maydell
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 8 +--
include/exec/cpu-all.h
Move all softmmu tlb data into this structure. Arrange the
members so that we are able to place mask+table together and
at a smaller absolute offset from ENV.
Reviewed-by: Peter Maydell
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 61 +++-
Patches missing review/ack:
0038-tcg-arm-Use-LDRD-to-load-tlb-mask-table.patch
Changes from v3->v4:
* Rebase to master, fixing a few conflicts.
* Reword and replicate commit messages.
Changes from v2->v3:
* Incorporate review from pm215:
include guards and copyright/license for new head
Cleanup in the boilerplate that each target must define.
Replace lm32_env_get_cpu with env_archcpu. The combination
CPU(lm32_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
targe
Cleanup in the boilerplate that each target must define.
Replace alpha_env_get_cpu with env_archcpu. The combination
CPU(alpha_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tar
For all targets, do this just before including exec/cpu-all.h.
Reviewed-by: Peter Maydell
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 4 ++--
target/arm/cpu.h| 4 ++--
target/cris/cpu.h | 4 ++--
target/hppa/cpu.h | 4 ++--
targ
Both structures are allocated once per mmu_idx.
There is no reason for them to be separate.
Reviewed-by: Alistair Francis
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 17 -
accel/tcg/cputlb.c | 24
2 files
On Tue, 4 Jun 2019 22:04:21 +0200
Greg Kurz wrote:
> On Tue, 4 Jun 2019 12:34:37 +0530
> Aravinda Prasad wrote:
>
> > On Monday 03 June 2019 09:10 PM, Greg Kurz wrote:
> > > On Wed, 29 May 2019 11:10:57 +0530
> > > Aravinda Prasad wrote:
> > >
> > >> This patch includes migration suppor
On Tue, 4 Jun 2019 12:34:37 +0530
Aravinda Prasad wrote:
> On Monday 03 June 2019 09:10 PM, Greg Kurz wrote:
> > On Wed, 29 May 2019 11:10:57 +0530
> > Aravinda Prasad wrote:
> >
> >> This patch includes migration support for machine check
> >> handling. Especially this patch blocks VM migrat
From: Aleksandar Rikalo
Implement support for translation of system call statx(). The
implementation includes invoking other (more mature) system calls
(from the same 'stat' family) on the host side. This way, the
problems of potential lack of statx() availability of on the host
side are avoided.
From: Neng Chen
Add support for options IPV6_ADD_MEMBERSHIP and IPV6_DROP_MEMPEMBERSHIP
of the syscall setsockopt(). These options control membership in
multicast groups. Their argument is a pointer to a struct ipv6_mreq,
which is in turn defined in IP v6 header netinet/in.h as:
struct ipv6_mre
From: Yunqiang Su
Add support for options SOL_ALG of the syscall setsockopt(). This
option is used in relation to Linux kernel Crypto API, and allows
a user to set additional information for the cipher operation via
syscall setsockopt(). The field "optname" must be one of the
following:
- ALG_
From: Aleksandar Markovic
This is a collection of misc patches for Linux user that I recently
accumulated from variuous sources. All of them originate from problems
observed on mips target. However, these changes actually affect and fix
problems on multiple targets.
v8->v9:
- fixed build erro
The MSI-X relocation code can sometimes be used to work around bogus
MSI-X capabilities, but this test for whether the PBA is outside of
the specified BAR causes the device to error before we can apply a
relocation. Let it proceed if we intend to relocate MSI-X anyway.
Signed-off-by: Alex William
The resizable BAR capability is currently exposed read-only from the
kernel and we don't yet implement a protocol for virtualizing it to
the VM. Exposing it to the guest read-only introduces poor behavior
as the guest has no reason to test that a control register write is
accepted by the hardware.
From: Anton Blanchard
We were using set_cpu_vsr*() when we should have used get_cpu_vsr*().
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
Message-Id: <20190509104912.6b754dff@kryten>
Reviewed-by: Mark
From: Anton Blanchard
Fix a typo in xxbrq and xxbrw where we put both results into the lower
doubleword.
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
Message-Id: <20190507004811.29968-3-an...@ozlabs.o
From: Anton Blanchard
Fix a typo in xvxsigdp where we put both results into the lower
doubleword.
Fixes: dd977e4f45cb ("target/ppc: Optimize x[sv]xsigdp using deposit_i64()")
Signed-off-by: Anton Blanchard
Message-Id: <20190507004811.29968-1-an...@ozlabs.org>
Signed-off-by: David Gibson
---
t
From: Anton Blanchard
During the conversion these instructions were incorrectly treated as
stores. We need to use set_cpu_vsr* and not get_cpu_vsr*.
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard
Review
From: Anton Blanchard
A recent cleanup changed the pre zeroing of the result from 64 bit
to 32 bit operations:
-result.u64[i] = 0;
+result.VsrW(i) = 0;
This corrupts the result.
Fixes: 60594fea298d ("target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in
int_helper.c")
Signe
Nothing to see here - just Anton's patches fixing several issues with the
VSX native endian conversion patches from 4.0, plus a related bug in xvxsigdp
queued for 4.0 stable.
Signed-off-by: Mark Cave-Ayland
Anton Blanchard (5):
target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]p
* Michael S. Tsirkin (m...@redhat.com) wrote:
> On Tue, Jun 04, 2019 at 03:43:21PM +0200, Jens Freimann wrote:
> > On Mon, Jun 03, 2019 at 04:36:48PM -0300, Eduardo Habkost wrote:
> > > On Mon, Jun 03, 2019 at 10:24:56AM +0200, Jens Freimann wrote:
> > > > On Fri, May 31, 2019 at 06:47:48PM -0300,
On 03/06/2019 11:48, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20190602110903.3431-1-mark.cave-ayl...@ilande.co.uk/
>
>
>
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Subject: [Qemu-devel] [PATCH v2 0
Patchew URL:
https://patchew.org/QEMU/20190602110903.3431-1-mark.cave-ayl...@ilande.co.uk/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v2 00/15] target/ppc: remove getVSR()/putVSR() and
further tidy-up
Type: se
Stefano Garzarella writes:
> Hi Alex,
> sorry for the big delay, but I was traveling without my PC.
>
> On Wed, Mar 06, 2019 at 05:51:05PM +, Alex Bennée wrote:
>>
>> Hi,
>>
>> I've been looking at using PVH as an alternative to a long bios boot
>> sequence to boot some x86_64 test kernels
This is the common header guard idiom:
/*
* File comment
*/
#ifndef GUARD_SYMBOL_H
#define GUARD_SYMBOL_H
... actual contents ...
#endif
A few of our headers have some #include before the guard.
target/tilegx/spr_def_64.h has #ifndef __DOXYGEN__ outside the guard.
Commit 58ea30f5145 "Clean up header guards that don't match their file
name" messed up contrib/elf2dmp/qemu_elf.h and
tests/migration/migration-test.h.
It missed target/cris/opcode-cris.h and
tests/uefi-test-tools/UefiTestToolsPkg/Include/Guid/BiosTablesTest.h
due to the scripts/clean-header-guard
Signed-off-by: Markus Armbruster
---
hw/9pfs/xen-9pfs.h| 6 +-
hw/hppa/hppa_hardware.h | 5 +
hw/input/adb-internal.h | 4
hw/net/e1000e_core.h | 5 +
hw/net/e1000x_common.h| 5 +
hw/net/vmxnet3_
clean-header-guards.pl fails to recognize a header guard #endif when
it's followed by a // comment, or multiple comments. Fix that.
Signed-off-by: Markus Armbruster
---
scripts/clean-header-guards.pl | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/scripts/clean-
Markus Armbruster (4):
Normalize position of header guard
scripts/clean-header-guards: Fix handling of trailing comments
Clean up a few header guard symbols
Supply missing header guards
contrib/elf2dmp/qemu_elf.h | 5 ++---
crypto/ivgen-essiv.h
On Tue, Jun 04, 2019 at 01:51:33PM +0200, Igor Mammedov wrote:
> On Mon, 3 Jun 2019 18:08:12 +0200
> Laszlo Ersek wrote:
>
> > On 06/03/19 13:22, Igor Mammedov wrote:
> > > adds simple arm/virt test case that starts guest with
> > > bios-tables-test.aarch64.iso.qcow2 boot image which
> > > initia
On Tue, Jun 04, 2019 at 05:55:36PM +0100, Peter Maydell wrote:
> On Tue, 4 Jun 2019 at 17:48, Michael S. Tsirkin wrote:
> > I see. I can drop this patch for now, but I suspect this
> > means this host always produced warning and possibly
> > that the tables are all wrong.
> > Could you send me the
On Tue, Jun 04, 2019 at 03:43:21PM +0200, Jens Freimann wrote:
> On Mon, Jun 03, 2019 at 04:36:48PM -0300, Eduardo Habkost wrote:
> > On Mon, Jun 03, 2019 at 10:24:56AM +0200, Jens Freimann wrote:
> > > On Fri, May 31, 2019 at 06:47:48PM -0300, Eduardo Habkost wrote:
> > > > On Thu, May 30, 2019 at
On 6/4/2019 3:13 AM, Klaus Birkelund wrote:
On Tue, Jun 04, 2019 at 10:46:45AM +0200, Kevin Wolf wrote:
Am 04.06.2019 um 10:28 hat Klaus Birkelund geschrieben:
On Mon, Jun 03, 2019 at 09:30:53AM -0600, Heitke, Kenneth wrote:
On 6/3/2019 5:14 AM, Kevin Wolf wrote:
Am 28.05.2019 um 08:18 h
On Tue, 4 Jun 2019 at 17:14, Kevin Wolf wrote:
>
> The following changes since commit e2a58ff493a2e00db3e963c1839c5374500110f2:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2019-06-03 18:26:21 +0100)
>
> are available in the Git repository at:
>
> git:/
On 21/05/19 08:17, Wanpeng Li wrote:
> From: Wanpeng Li
>
> Allow guest reads CORE cstate when exposing host CPU power management
> capabilities
> to the guest. PKG cstate is restricted to avoid a guest to get the whole
> package
> information in multi-tenant scenario.
>
> Cc: Eduardo Habkos
On Tue, 4 Jun 2019 at 17:48, Michael S. Tsirkin wrote:
> I see. I can drop this patch for now, but I suspect this
> means this host always produced warning and possibly
> that the tables are all wrong.
> Could you send me the actual and expected files please?
> Preferably both dsl and binary.
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