Re: [Qemu-devel] [PATCH v9 1/2] hw/arm: Add arm SBSA reference machine, skeleton part

On Sun, 30 Jun 2019 at 11:21, Hongbo Zhang wrote: > > For the Aarch64, there is one machine 'virt', it is primarily meant to > run on KVM and execute virtualization workloads, but we need an > environment as faithful as possible to physical hardware, for supporting > firmware and OS development fo

Re: [Qemu-devel] [PATCH v6 4/8] hw/arm/virt: Add memory hotplug framework

On Tue, 25 Jun 2019 at 13:15, Shameer Kolothum wrote: > > From: Eric Auger > > This patch adds the memory hot-plug/hot-unplug infrastructure > in machvirt. The device memory is not yet exposed to the Guest > either through DT or ACPI and hence both cold/hot plug of memory > is explicitly disabled

Re: [Qemu-devel] [RFC PATCH] accel/tcg/translator: add tb_enter TCG trace

On Mon, Jul 01, 2019 at 02:33:11PM +0100, Alex Bennée wrote: > > Edgar E. Iglesias writes: > > > On Fri, Jun 28, 2019 at 02:16:41PM +0200, Richard Henderson wrote: > >> On 6/28/19 1:39 PM, Luc Michel wrote: > >> > Add a TCG trace at the begining of a translation block recording the > >> > first

[Qemu-devel] [PATCH v3 15/15] hw/i386/pc: Extract the x86 generic fw_cfg code

Extract all the functions that are not PC-machine specific into the (arch-specific) fw_cfg.c file. This will allow other X86-machine to reuse these functions. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/fw_cfg.c | 137

Re: [Qemu-devel] [PATCH v5 0/8] Build ACPI Heterogeneous Memory Attribute Table (HMAT)

On Fri, 14 Jun 2019 23:56:18 +0800 Tao Xu wrote: > This series of patches will build Heterogeneous Memory Attribute Table (HMAT) > according to the command line. The ACPI HMAT describes the memory attributes, > such as memory side cache attributes and bandwidth and latency details, > related to t

Re: [Qemu-devel] [PATCH v24 1/7] target/avr: Add outward facing interfaces and core CPU logic

should I use *-avr-cpu* suffix or can I do without it. i.e. *xyz* instead of *xyz-avr-cpu* On Mon, Jul 1, 2019 at 2:08 AM Igor Mammedov wrote: > On Fri, 28 Jun 2019 18:54:27 +0300 > Michael Rolnik wrote: > > > Igor. > > > > so avr6 instead of a6-avr-cpu, xmega2 instead of xmega2-avr-cpu and so

Re: [Qemu-devel] [PATCH v2 0/9] configure: Fix softmmu --static linking

On 6/14/19 12:07 PM, Philippe Mathieu-Daudé wrote: > Hi, > > Apparently QEMU static linking is slowly bitroting. Obviously it > depends the libraries an user has installed, anyway it seems there > are not much testing done. > > This series fixes few issues, enough to build QEMU on a Ubuntu > 18.0

[Qemu-devel] [PATCH v3 11/15] hw/i386/pc: Rename pc_build_smbios() as generic fw_cfg_build_smbios()

Now that the pc_build_smbios() function has been refactored to not depend of PC specific types, rename it to a more generic name. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.

Re: [Qemu-devel] [PATCH] BootLinuxSshTest: Only use 'test' for unittest.TestCase method names

ping? On 6/7/19 7:49 PM, Philippe Mathieu-Daudé wrote: > In commit f6e501a28ef9, Eduardo started to use "check_" as a > prefix for methods of similar purpose. Follow this prior art, > since it might become the conventions when writting Avocado > tests. > > Suggested-by: Cleber Rosa > Signed-off-

[Qemu-devel] [PATCH v3 10/15] hw/i386/pc: Let pc_build_smbios() take a generic MachineState argument

Let the pc_build_smbios() function take a generic MachineState argument. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2b6502a38c..1195394694 100644 ---

[Qemu-devel] [PATCH v3 13/15] hw/i386/pc: Let pc_build_feature_control() take a MachineState argument

Let the pc_build_feature_control_file() function take a generic MachineState argument. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index c49617a3f1..2ab2c63

[Qemu-devel] [PATCH v3 14/15] hw/i386/pc: Rename pc_build_feature_control() as generic fw_cfg_build_*

Now that the pc_build_feature_control_file() function has been refactored to not depend of PC specific types, rename it to a more generic name. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --g

Re: [Qemu-devel] [PATCH] ati-vga: Add DDC reg names for debug

On 6/21/19 8:12 PM, BALATON Zoltan wrote: > Incremental patch to squash into last series > > Signed-off-by: BALATON Zoltan > --- > hw/display/ati_dbg.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c > index b045f81d06..88b3a11315 100644 >

Re: [Qemu-devel] [RFC PATCH] accel/tcg/translator: add tb_enter TCG trace

Edgar E. Iglesias writes: > On Fri, Jun 28, 2019 at 02:16:41PM +0200, Richard Henderson wrote: >> On 6/28/19 1:39 PM, Luc Michel wrote: >> > Add a TCG trace at the begining of a translation block recording the >> > first and last (past-the-end) PC values. >> > >> > Signed-off-by: Luc Michel >>

[Qemu-devel] [PATCH v3 09/15] hw/i386/pc: Let pc_build_smbios() take a FWCfgState argument

Pass the FWCfgState object by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c in

[Qemu-devel] [PATCH v3 12/15] hw/i386/pc: Let pc_build_feature_control() take a FWCfgState argument

Pass the FWCfgState object by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index

[Qemu-devel] [PATCH v3 08/15] hw/i386/pc: Let fw_cfg_init() use the generic MachineState

We removed the PCMachineState access, we can now let the fw_cfg_init() function to take a generic MachineState object. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i38

[Qemu-devel] [PATCH v3 07/15] hw/i386/pc: Pass the CPUArchIdList array by argument

Pass the CPUArchIdList array by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc.c b/hw/i38

[Qemu-devel] [PATCH v3 06/15] hw/i386/pc: Pass the apic_id_limit value by argument

Pass the apic_id_limit value by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index

[Qemu-devel] [PATCH v3 03/15] hw/i386/pc: Use address_space_memory in place

The address_space_memory variable is used once. Use it in place and remove the argument. Suggested-by: Samuel Ortiz Reviewed-by: Li Qiang Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.

Re: [Qemu-devel] [PATCH v2] aspeed: Link SCU to the watchdog

On Fri, 21 Jun 2019 at 07:52, Joel Stanley wrote: > > The ast2500 uses the watchdog to reset the SDRAM controller. This > operation is usually performed by u-boot's memory training procedure, > and it is enabled by setting a bit in the SCU and then causing the > watchdog to expire. Therefore, we n

[Qemu-devel] [RFC PATCH v3 26/27] target/arm: Do not build A/M-profile cpus when using KVM

A KVM-only build won't be able to run A or M-profile cpus, disable them. If KVM is not enabled, they are enabled by default. Signed-off-by: Philippe Mathieu-Daudé --- Sadly this does not work with --enable-tcg --enable-kvm dual config. --- default-configs/arm-softmmu.mak | 14 ++ hw

[Qemu-devel] [PATCH v3 05/15] hw/i386/pc: Pass the boot_cpus value by argument

The boot_cpus is used once. Pass it by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc

[Qemu-devel] [PATCH v3 04/15] hw/i386/pc: Rename bochs_bios_init as more generic fw_cfg_arch_create

The bochs_bios_init() function is not restricted to the Bochs BIOS and is useful to other BIOS. Since it is not specific to the PC machine, and can be reused by other machines of the X86 architecture, rename it as fw_cfg_arch_create(). Suggested-by: Samuel Ortiz Reviewed-by: Li Qiang Signed-off-

[Qemu-devel] [PATCH v3 01/15] hw/i386/pc: Use e820_get_num_entries() to access e820_entries

To be able to extract the e820* code out of this file (in the next patch), access e820_entries with its correct helper. Reviewed-by: Li Qiang Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c in

[Qemu-devel] [PATCH v3 00/15] hw/i386/pc: Do not restrict the fw_cfg functions to the PC machine

Hi, This is my take at salvaging some NEMU good work. Samuel worked in adding the fw_cfg device to the x86-virt NEMU machine. This series is inspired by NEMU's commit 3cb92d080835 [0] and adapted to upstream style. The result makes the upstream codebase more modularizable. There are very little lo

[Qemu-devel] [PATCH v3 17/27] target/arm/vfp_helper: Restrict the SoftFloat use to TCG

This code is specific to the SoftFloat floating-point implementation, which is only used by TCG. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/vfp_helper.c | 26 +++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/

[Qemu-devel] [PATCH v3 02/15] hw/i386/pc: Extract e820 memory layout code

Suggested-by: Samuel Ortiz Reviewed-by: Li Qiang Signed-off-by: Philippe Mathieu-Daudé --- v3: KISS, do not use unsigned, do not add broken documentation --- hw/i386/Makefile.objs| 2 +- hw/i386/e820_memory_layout.c | 59 ++ hw/i386/e820_memory_layout.h

Re: [Qemu-devel] [PATCH v2 00/21] aspeed: machine extensions and fixes

On Tue, 18 Jun 2019 at 17:53, Cédric Le Goater wrote: > > Hello, > > This series improves the current models of the Aspeed machines in QEMU > and adds new ones. It also prepares ground for the future Aspeed SoC. > You will find patches for : > > - per SoC mappings of the memory space and the inte

[Qemu-devel] [PATCH v3 20/27] target/arm: Declare arm_log_exception() function publicly

In few commits we will split the M-profile functions from this file, and this function will also be called in the new file. Declare it in the "internals.h" header. Since it is in the middle of a block of M profile functions, move it previous to this block to ease the later refactor. Signed-off-by:

[Qemu-devel] [RFC PATCH v3 24/27] target/arm: Do not build pre-ARMv7 cpus when using KVM

A KVM-only build won't be able to run pre-ARMv7 cpus, disable them. If KVM is not enabled, they are enabled by default. Signed-off-by: Philippe Mathieu-Daudé --- Sadly this does not work with --enable-tcg --enable-kvm dual config. --- default-configs/arm-softmmu.mak | 33 ---

[Qemu-devel] [PATCH v3 27/27] target/arm: Do not build TCG objects when TCG is off

We can now safely turn all TCG dependent build off when CONFIG_TCG is off. This allows building ARM binaries with --disable-tcg. Signed-off-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- v3: complete rewrite of patch content, removed R-b tags --- target/arm/Makefile.objs | 4 1

[Qemu-devel] [PATCH v3 18/27] target/arm: Restrict semi-hosting to TCG

Per Peter Maydell: Semihosting hooks either SVC or HLT instructions, and inside KVM both of those go to EL1, ie to the guest, and can't be trapped to KVM. Let check_for_semihosting() return False when not running on TCG. Signed-off-by: Philippe Mathieu-Daudé --- v3: inline call to g_asser

[Qemu-devel] [PATCH v3 14/27] target/arm/vfp_helper: Move code around

To ease the review of the next commit, move the vfp_exceptbits_to_host() function directly after vfp_exceptbits_from_host(). Amusingly the diff shows we are moving vfp_get_fpscr(). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/vfp_helper.c | 52 -

[Qemu-devel] [RFC PATCH v3 25/27] target/arm: Restrict R and M profiles to TCG

KVM is only able to run A profile cpus. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d0376f46f7..b21d0fb891 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c

[Qemu-devel] [PATCH v3 19/27] target/arm: Restrict PSCI to TCG

Under KVM, the kernel gets the HVC call and handle the PSCI requests. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 46a1313d69..57e0253ef4 100644 ---

[Qemu-devel] [PATCH v3 10/27] target/arm: Move CPU state dumping routines to cpu.c

Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 226 + target/arm/cpu.h | 2 - target/arm/translate-a64.c | 128 - target/arm/translate.c | 88 --- target/arm/tr

[Qemu-devel] [PATCH v3 15/27] target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()

The vfp_set_fpscr() helper contains code specific to the host floating point implementation (here the SoftFloat library). Extract this code to vfp_set_fpscr_to_host(). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/vfp_helper.c | 127 +--- 1 file changed

[Qemu-devel] [RFC PATCH v3 23/27] target/arm: Restrict pre-ARMv7 cpus to TCG

KVM requires at least a ARMv7 cpu. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 12 1 file changed, 12 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 37afb12b2d..d0376f46f7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1643,6 +1643,8

[Qemu-devel] [PATCH v3 12/27] target/arm: Move TLB related routines to tlb_helper.c

These routines are TCG specific. The arm_deliver_fault() function is only used within the new helper. Make it static. Suggested-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- target/arm/Makefile.objs | 1 + target/arm/cpu.c | 6 +- target/arm/helper.c | 53 -

[Qemu-devel] [PATCH v3 13/27] target/arm: Move debug routines to debug_helper.c

These routines are TCG specific. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/Makefile.objs | 2 +- target/arm/cpu.c | 11 +- target/arm/debug_helper.c | 334 ++ target/arm/helper.c | 23 --- target/arm/op_helper.c| 295

[Qemu-devel] [PATCH v3 06/27] target/arm/helper: Remove unused include

Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d3f3cb57d5..ca4d4a57bf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -14,7 +14,6 @@ #include "exec/gdbstub.h" #inclu

[Qemu-devel] [PATCH v3 21/27] target/arm: Declare some M-profile functions publicly

In the next commit we will split the M-profile functions from this file. Some function will be called out of helper.c. Declare them in the "internals.h" header. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- v3: Was v7-only, add v8 --- target/arm/helper.c| 38 ++-

[Qemu-devel] [PATCH v3 11/27] target/arm: Declare get_phys_addr() function publicly

In the next commit we will split the TLB related routines of this file, and this function will also be called in the new file. Declare it in the "internals.h" header. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c| 21 + target/arm/internals.h | 16

[Qemu-devel] [PATCH v3 07/27] target/arm: Fix multiline comment syntax

Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline comment syntax. Since we'll move this code around, fix its style first. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- v3: added vfp_helper.c --- target/arm/helper.c | 237 ++--

[Qemu-devel] [PATCH v3 16/27] target/arm/vfp_helper: Extract vfp_set_fpscr_from_host()

The vfp_set_fpscr() helper contains code specific to the host floating point implementation (here the SoftFloat library). Extract this code to vfp_set_fpscr_from_host(). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/vfp_helper.c | 19 +-- 1 file changed, 13 insertions(+),

[Qemu-devel] [PATCH v3 04/27] target/arm: Makefile cleanup (softmmu)

Group SOFTMMU objects together. Since PSCI is TCG specific, keep it separate. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- target/arm/Makefile.objs | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs i

[Qemu-devel] [PATCH v3 03/27] target/arm: Makefile cleanup (KVM)

Group KVM rules together. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- target/arm/Makefile.objs | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 1cbe7cfdb4..7a933eebc7 100644 --- a/target

[Qemu-devel] [PATCH v3 08/27] target/arm: Fix coding style issues

Since we'll move this code around, fix its style first. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- v3: added vfp_helper.c --- target/arm/translate.c | 11 ++- target/arm/vfp_helper.c | 36 2 files changed, 30 insertions(+), 1

[Qemu-devel] [PATCH v3 05/27] target/arm: Add copyright boilerplate

Reviewed-by: Robert Bradford Reviewed-by: Samuel Ortiz Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index df4276f5f6..d3f3cb57d5 100644 --- a/target/ar

[Qemu-devel] [PATCH v3 09/27] target/arm: Move the DC ZVA helper into op_helper

From: Samuel Ortiz Those helpers are a software implementation of the ARM v8 memory zeroing op code. They should be moved to the op helper file, which is going to eventually be built only when TCG is enabled. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Robert Bradford Signed-off-by: Samue

[Qemu-devel] [PATCH v3 01/27] target/arm: Makefile cleanup (Aarch64)

Group Aarch64 rules together, TCG related ones at the bottom. This will help when restricting TCG-only objects. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- target/arm/Makefile.objs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/Makefil

[Qemu-devel] [PATCH v3 00/27] Support disabling TCG on ARM

Paolo motived me to salvage this (other!) previous series fromi Samuel Ortiz (NEMU project). v1 cover from Samuel [1]: This patchset allows for building and running ARM targets with TCG disabled. It splits the target/arm/helper.c file into logical TCG and non TCG dependent files so that one

[Qemu-devel] [PATCH v3 02/27] target/arm: Makefile cleanup (ARM)

Group ARM objects together, TCG related ones at the bottom. This will help when restricting TCG-only objects. Reviewed-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- v3: move vfp_helper.o --- target/arm/Makefile.objs | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) d

[Qemu-devel] [REPOST PATCH for-4.1] spapr/xive: Add proper rollback to kvmppc_xive_connect()

Make kvmppc_xive_disconnect() able to undo the changes of a partial execution of kvmppc_xive_connect() and use it to perform rollback. Signed-off-by: Greg Kurz Reviewed-by: Cédric Le Goater --- David, This is the only pending fix for XIVE, rebased on ppc-for-4.1. SHA1 d6923ffa0748af614e7d2c82

Re: [Qemu-devel] [Qemu-trivial] Fix cacheline size retrieval on FreeBSD/PowerPC(64)

Le 01/07/2019 à 15:02, Justin Hibbits a écrit : > > > On Mon, Jul 1, 2019, 03:54 Laurent Vivier > wrote: > > Le 27/06/2019 à 02:15, Justin Hibbits a écrit : > > > > > > On Wed, Jun 26, 2019, 19:08 Laurent Vivier > > <

Re: [Qemu-devel] [Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3

On Mon, Jul 1, 2019 at 6:12 PM Jonathan Cameron wrote: > > On Fri, 28 Jun 2019 09:12:45 -0700 > Alistair Francis wrote: > > > On Fri, Jun 28, 2019 at 2:47 AM Jonathan Cameron > > wrote: > > > > > > On Thu, 27 Jun 2019 08:20:10 -0700 > > > Palmer Dabbelt wrote: > > > > > > > From: Alistair Franc

Re: [Qemu-devel] [PATCH v2 16/21] aspeed/smc: add DMA calibration settings

On Tue, 18 Jun 2019 at 17:55, Cédric Le Goater wrote: > > When doing calibration, the SPI clock rate in the CE0 Control Register > and the read delay cycles in the Read Timing Compensation Register are > set using bit[11:4] of the DMA Control Register. > > Signed-off-by: Cédric Le Goater > Acked-

Re: [Qemu-devel] [PATCH 4/3] pcie: minor cleanups for slot control/status

On Mon, 1 Jul 2019 05:34:54 -0400 "Michael S. Tsirkin" wrote: > Rename function arguments to make intent clearer. > Better documentation for slot control logic. > > Suggested-by: Igor Mammedov > Signed-off-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov > --- > > > include/hw/pci/pcie

Re: [Qemu-devel] [PATCH 2/3] pcie: check that slt ctrl changed before deleting

On Fri, 21 Jun 2019 02:46:48 -0400 "Michael S. Tsirkin" wrote: > During boot, linux would sometimes overwrites control of a powered off > slot before powering it on. Unfortunately QEMU interprets that as a > power off request and ejects the device. > > For example: > > /x86_64-softmmu/qemu-syst

Re: [Qemu-devel] [PATCH v2 15/21] aspeed/smc: add support for DMAs

On Tue, 18 Jun 2019 at 17:55, Cédric Le Goater wrote: > > The FMC controller on the Aspeed SoCs support DMA to access the flash > modules. It can operate in a normal mode, to copy to or from the flash > module mapping window, or in a checksum calculation mode, to evaluate > the best clock settings

Re: [Qemu-devel] [RFC PATCH] accel/tcg/translator: add tb_enter TCG trace

On Fri, Jun 28, 2019 at 02:16:41PM +0200, Richard Henderson wrote: > On 6/28/19 1:39 PM, Luc Michel wrote: > > Add a TCG trace at the begining of a translation block recording the > > first and last (past-the-end) PC values. > > > > Signed-off-by: Luc Michel > > --- > > This can be used to trace

Re: [Qemu-devel] [Qemu-trivial] Fix cacheline size retrieval on FreeBSD/PowerPC(64)

On Mon, Jul 1, 2019, 03:54 Laurent Vivier wrote: > Le 27/06/2019 à 02:15, Justin Hibbits a écrit : > > > > > > On Wed, Jun 26, 2019, 19:08 Laurent Vivier > > wrote: > > > > Le 27/06/2019 à 02:02, Justin Hibbits a écrit : > > > > > > > > > On Wed, Jun 26,

Re: [Qemu-devel] [PATCH 3/3] pcie: work around for racy guest init

On Fri, 21 Jun 2019 02:46:50 -0400 "Michael S. Tsirkin" wrote: > During boot, linux guests tend to clear all bits in pcie slot status > register which is used for hotplug. > If they clear bits that weren't set this is racy and will lose events: > not a big problem for manual hotplug on bare-metal

Re: [Qemu-devel] [PULL 0/6] final s390x patches for 4.1 softfreeze

Patchew URL: https://patchew.org/QEMU/2019070722.32068-1-coh...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 2019070722.32068-1-coh...@redhat.com Type: series Subject: [Qemu-devel] [PULL 0/6] final s390x patche

Re: [Qemu-devel] [PATCH v2 10/21] aspeed/timer: Provide back-pressure information for short periods

On Tue, 18 Jun 2019 at 17:54, Cédric Le Goater wrote: > > From: Andrew Jeffery > > First up: This is not the way the hardware behaves. > > However, it helps resolve real-world problems with short periods being > used under Linux. Commit 4451d3f59f2a ("clocksource/drivers/fttmr010: > Fix set_next_

Re: [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3

On Fri, 28 Jun 2019 09:12:45 -0700 Alistair Francis wrote: > On Fri, Jun 28, 2019 at 2:47 AM Jonathan Cameron > wrote: > > > > On Thu, 27 Jun 2019 08:20:10 -0700 > > Palmer Dabbelt wrote: > > > > > From: Alistair Francis > > > > > > Add OpenSBI version 0.3 as a git submodule and as a prebult

Re: [Qemu-devel] [PULL 0/8] xen queue 2019-06-24

On Mon, 24 Jun 2019 at 16:33, Anthony PERARD wrote: > > The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: > > Merge remote-tracking branch > 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 > 15:40:50 +0100) > > are available in the Git reposi

[Qemu-devel] [PATCH v3 1/3] qemu-bridge-helper: restrict interface name to IFNAMSIZ

From: Prasad J Pandit The network interface name in Linux is defined to be of size IFNAMSIZ(=16), including the terminating null('\0') byte. The same is applied to interface names read from 'bridge.conf' file to form ACL rules. If user supplied '--br=bridge' name is not restricted to the same len

[Qemu-devel] [PATCH v3 3/3] net: tap: refactor net_bridge_run_helper routine

From: Prasad J Pandit Refactor 'net_bridge_run_helper' routine to avoid buffer formatting to prepare 'helper_cmd' and using shell to invoke helper command. Instead directly execute helper program with due arguments. Signed-off-by: Prasad J Pandit --- net/tap.c | 43 +---

[Qemu-devel] [PATCH v3 2/3] qemu-bridge-helper: move repeating code in parse_acl_file

From: Prasad J Pandit Move repeating error handling sequence in parse_acl_file routine to an 'err' label. Signed-off-by: Prasad J Pandit --- qemu-bridge-helper.c | 19 +-- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/qemu-bridge-helper.c b/qemu-bridge-helper.c

[Qemu-devel] [PATCH] hw/misc/macio: Add the nvram as child of the MacIO south bridge

Avoid another QOM orphean, link it back to its parent. Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/macio/macio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 82492096f8..e02882be28 100644 --- a/hw/misc/macio/macio

[Qemu-devel] [PATCH v3 0/3] restrict bridge interface name to IFNAMSIZ

From: Prasad J Pandit Hello, Linux net_deivce defines network interface name to be of IFNAMSIZE(=16) bytes, including the terminating null('\0') byte. Qemu tap deivce, while invoking 'qemu-bridge-helper' tool to set up the network bridge interface, supplies bridge name of 16 characters, thus al

[Qemu-devel] [PATCH 4/6] hw/arm/fsl-imx: Add the cpu as child of the SoC object

Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/fsl-imx25.c | 4 +++- hw/arm/fsl-imx31.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 869ee89b15..a237e967e4 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -36,7

[Qemu-devel] [PATCH 6/6] hw/net/xilinx_axi: Use object_initialize_child for correct ref. counting

As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be prope

Re: [Qemu-devel] [PATCH 0/6] hw/arm: Use ARM_CPU_TYPE_NAME() and object_initialize_child()

Buh I forgot to Cc Eduardo. On 7/1/19 2:31 PM, Philippe Mathieu-Daudé wrote: > First we use ARM_CPU_TYPE_NAME() when we should. > > Then is follow up of > https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg01492.html > > This series looks at Eduardo suggestions from [1] > and Thomas co

[Qemu-devel] [PATCH 1/6] hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate

Commit ba1ba5cca introduce the ARM_CPU_TYPE_NAME() macro. Unify the code base by use it in all places. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/allwinner-a10.c | 3 ++- hw/arm/cubieboard.c| 3 ++- hw/arm/digic.c | 3 ++- hw/arm/fsl-imx6.c | 3 ++- hw/arm/fsl-imx6ul.c

[Qemu-devel] [PATCH 5/6] hw/dma/xilinx_axi: Use object_initialize_child for correct ref. counting

As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be prope

[Qemu-devel] [PATCH 2/6] hw/arm: Use object_initialize_child for correct reference counting

As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be prope

[Qemu-devel] [PATCH 3/6] hw/arm: Use sysbus_init_child_obj for correct reference counting

As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be prope

[Qemu-devel] [PATCH 0/6] hw/arm: Use ARM_CPU_TYPE_NAME() and object_initialize_child()

First we use ARM_CPU_TYPE_NAME() when we should. Then is follow up of https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg01492.html This series looks at Eduardo suggestions from [1] and Thomas commit aff39be0ed97 to replace various object_initialize + qdev_set_parent_bus calls by sy

Re: [Qemu-devel] [PATCH v4 1/4] hw/mips: Explicit the semi-hosting feature is always required

> From: Philippe Mathieu-Daudé > Sent: Monday, July 1, 2019 1:26 PM > Subject: [PATCH v4 1/4] hw/mips: Explicit the semi-hosting feature is always > required > > Disabling the semi-hosting feature leads to build failure: ... > Add a comment to avoid this feature to be disabled. Signed-off-by:

Re: [Qemu-devel] [PATCH v4 4/4] hw/mips: Express dependencies of the r4k platform with Kconfig

> From: Philippe Mathieu-Daudé > Sent: Monday, July 1, 2019 1:26 PM > Subject: [PATCH v4 4/4] hw/mips: Express dependencies of the r4k platform > with Kconfig > > This platform use standard PC devices connected to an ISA bus. > Networking is provided by a ne2000 chipset. > > Signed-off-by: Phil

Re: [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes

On Tue, 18 Jun 2019 at 01:27, Andrey Smirnov wrote: > > On Mon, Apr 15, 2019 at 6:39 PM Andrey Smirnov > wrote: > > > > Everyone: > > > > I recently revisited my i.MX7 work and this series contains all of the > > fixes I had to make to get it to work with latest (5.1-rc1) Linux > > kernel again

Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

On Mon, 1 Jul 2019 at 13:04, Lucien Anti-Spam wrote: > Further to my initial problem I noticed that TRAP #0 also jumps to the > handlers +1 instruction. > Same behavior can also be seen with ARM "SWI #0".(PC shows 0x0C vs the > expected 0x08) Yes, that's a known bug for arm -- we treat "sin

Re: [Qemu-devel] [RFC 1/1] hw/pvrdma: Add live migration support

> > > > > > @Marcel, @Yuval: As David has suggested, what if we just read the dma > > > addresses in pvrdma_load(), and let the load_dsr() do the mapping? > > > In pvrdma_regs_write(), we can check if dev->dsr_info.dma is already set, > > > so > > > that its value is not overwritten. > > > > Have

Re: [Qemu-devel] [PATCH 3/3] pcie: work around for racy guest init

On Mon, Jul 01, 2019 at 02:04:02PM +0200, Igor Mammedov wrote: > On Mon, 1 Jul 2019 05:20:41 -0400 > "Michael S. Tsirkin" wrote: > > > On Tue, Jun 25, 2019 at 03:07:30PM +0200, Igor Mammedov wrote: > > > On Fri, 21 Jun 2019 02:46:50 -0400 > > > "Michael S. Tsirkin" wrote: > > > > > > > During

Re: [Qemu-devel] [PATCH 3/3] pcie: work around for racy guest init

On Mon, 1 Jul 2019 05:20:41 -0400 "Michael S. Tsirkin" wrote: > On Tue, Jun 25, 2019 at 03:07:30PM +0200, Igor Mammedov wrote: > > On Fri, 21 Jun 2019 02:46:50 -0400 > > "Michael S. Tsirkin" wrote: > > > > > During boot, linux guests tend to clear all bits in pcie slot status > > > register w

Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

>On Monday, July 1, 2019, 06:10:55 PM GMT+9, Peter Maydell wrote: > > On Sat, 29 Jun 2019 at 17:37, Lucien Murray-Pitts> > wrote: > > However for the m68k the do_transaction_failed function pointer field > > has not been implemented.>Er, I implemented that in commit > > e1aaf3a88e95ab007

Re: [Qemu-devel] [PATCH 5/5] i.mx7d: pci: Update PCI IRQ mapping to match HW

On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov wrote: > > Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches > that of i.MX6: > > * INTD/MSI122 > * INTC123 > * INTB124 > * INTA125 > > Fix all of the relevant code to reflect that fact. Nee

Re: [Qemu-devel] [PULL v2 0/8] Block patches

On Mon, 24 Jun 2019 at 15:47, Max Reitz wrote: > > The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: > > Merge remote-tracking branch > 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 > 15:40:50 +0100) > > are available in the Git repository

Re: [Qemu-devel] [PATCH v2 0/2] intel_iommu: Fix unexpected unmaps during global unmap

On Mon, Jun 24, 2019 at 05:18:09PM +0800, Peter Xu wrote: > v2: > - rename helper to get_naturally_aligned_size(), simplify the > codes as suggested [Paolo] > - check against vtd page size when looping over for unmaps [Yan] > - add r-b for Eric > > Please review, thanks. Series: Reviewed-by: Mi

Re: [Qemu-devel] [PATCH 4/5] pci: designware: Update MSI mapping when MSI address changes

On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov wrote: > > MSI mapping needs to be update when MSI address changes, so add the > code to do so. > > Signed-off-by: Andrey Smirnov > Cc: Peter Maydell > Cc: Michael S. Tsirkin > Cc: qemu-devel@nongnu.org > Cc: qemu-...@nongnu.org > --- Reviewed-by: P

Re: [Qemu-devel] [PATCH v1 1/1] hw/scsi: Report errors and sense to guests through scsi-block

On 01/07/19 12:14, Shinichiro Kawasaki wrote: > I observe four of them listed below in sense data, > when I ran basic operations to the zoned storage from the guest via > scsi-block. > > 21h 04h: UNALIGNED WRITE COMMAND > 21h 05h: WRITE BOUNDARY VIOLATION > 21h 06h: ATTEMPT TO REA

Re: [Qemu-devel] [PATCH 3/5] pci: designware: Update MSI mapping unconditionally

On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov wrote: > > Expression to calculate update_msi_mapping in code handling writes to > DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should > be: > > !!root->msi.intr[0].enable ^ !!val; > > so that MSI mapping is updated when enabled tra

Re: [Qemu-devel] [PATCH v6 15/16] tcg/ppc: Update vector support to v2.07

On Mon, Jul 1, 2019 at 12:29 PM Richard Henderson wrote: > > On 7/1/19 5:57 AM, Aleksandar Markovic wrote: > > > > On Jun 30, 2019 5:12 PM, "Richard Henderson" > > wrote: > >> > >> On 6/30/19 3:37 PM, Aleksandar Markovic wrote: > >> >> bool have_isa_2_06; > >

Re: [Qemu-devel] [PATCH 4/7] target/mips: Correct comments in translate.c

On 7/1/19 1:04 PM, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > Fix some checkpatch comment-related warnings. > > Signed-off-by: Aleksandar Markovic > --- > target/mips/translate.c | 347 > +++- > 1 file changed, 225 insertions(+), 122

[Qemu-devel] [PULL 6/6] s390x: add cpu feature/model files to KVM section

The cpu features/models are not only relevant for TCG, but also for KVM. Make sure that the KVM maintainers are cc:ed on patches as well. Message-Id: <20190626130820.12290-1-coh...@redhat.com> Acked-by: Christian Borntraeger Acked-by: Halil Pasic Signed-off-by: Cornelia Huck --- MAINTAINERS |

[Qemu-devel] [PATCH v4 3/4] hw/mips: Express dependencies of the Jazz machine with Kconfig

The Jazz use the RC4030 Asic to provide an EISA bus and DMA/IRQ. The framebuffer display is managed by a G364, the network card is a Sonic DP83932. A QLogic ESP216 provides a SCSI bus. None, for the both machine variants (PICA-61 and Magnum 4000), the DP83932 chipset is soldered on the board, and

[Qemu-devel] [PATCH v4 4/4] hw/mips: Express dependencies of the r4k platform with Kconfig

This platform use standard PC devices connected to an ISA bus. Networking is provided by a ne2000 chipset. Signed-off-by: Philippe Mathieu-Daudé --- v4: use 'imply' for VGA_ISA/NE2000_ISA (Thomas) v3: remove CONFIG_NE2000_ISA (Thomas) add PFLASH_CFI01 --- default-configs/mips-softmmu-common

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