On 18/06/2020 21.04, Claudio Fontana wrote:
> refactoring of cpus.c continues with cpu timer state extraction.
>
> cpu-timers: responsible for the cpu timers state, and for access to
> cpu clocks and ticks.
>
> icount: counts the TCG instructions executed. As such it is specific to
> the TCG
On 18/06/2020 21.03, Claudio Fontana wrote:
> move arch_init, balloon, cpus, ioport, memory, memory_mapping, qtest.
>
> They are all specific to CONFIG_SOFTMMU.
>
> Signed-off-by: Claudio Fontana
> Reviewed-by: Alex Bennée
> ---
> MAINTAINERS | 12 ++--
On 18.06.2020 20:38, Peter Maydell wrote:
For -icount mode to work, there are requirements on the target/
code (notably around marking up "I/O" instructions). Unfortunately
we've never documented what these are, which makes it pretty rough
for people writing new targets or reviewing changes to
> On Jun 18, 2020, at 6:29 PM, Richard Henderson
> wrote:
>
> On 6/12/20 9:20 PM, Lijun Pan wrote:
>> +#define VMULH_DO(name, op, element, cast_orig, cast_temp) \
>> +void helper_vmulh##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
>> \
>> +{
> On Jun 18, 2020, at 6:27 PM, Richard Henderson
> wrote:
>
> On 6/12/20 9:20 PM, Lijun Pan wrote:
>> vmulld: Vector Multiply Low Doubleword.
>>
>> Signed-off-by: Lijun Pan
>> ---
>> target/ppc/helper.h | 1 +
>> target/ppc/int_helper.c | 1 +
>>
> On Jun 18, 2020, at 6:19 PM, Richard Henderson
> wrote:
>
> On 6/12/20 9:20 PM, Lijun Pan wrote:
>> POWER ISA 3.1 introduces following byte-reverse instructions:
>> brd: Byte-Reverse Doubleword X-form
>> brw: Byte-Reverse Word X-form
>> brh: Byte-Reverse Halfword X-form
>>
>>
> On Jun 18, 2020, at 6:09 PM, Richard Henderson
> wrote:
>
> On 6/15/20 1:53 PM, Lijun Pan wrote:
+static inline void uint128_add(uint64_t ah, uint64_t al, uint64_t bh,
+ uint64_t bl, uint64_t *rh, uint64_t *rl, uint64_t *ca)
+{
+ __uint128_t a =
On Thu, Jun 18, 2020 at 08:55:53AM +0200, Markus Armbruster wrote:
> Either I'm confused (quite possible), or kvmppc_check_papr_resize_hpt()
> can leak an Error object on failure. Please walk through the code with
> me:
>
> kvmppc_check_papr_resize_hpt(_hpt_err);
>
> This sets
On Thu, 18 Jun 2020 16:18:20 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Jun 18, 2020 at 3:42 PM Palmer Dabbelt wrote:
On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistai...@gmail.com wrote:
> On Thu, May 28, 2020 at 11:13 AM Alistair Francis
wrote:
>>
>> On Thu, May 21, 2020 at 8:57 AM
On 2020/6/18 下午10:05, no-re...@patchew.org wrote:
/tmp/qemu-test/src/tests/qht-bench.c:287:29: error: implicit conversion from
'unsigned long' to 'double' changes value from 18446744073709551615 to
18446744073709551616 [-Werror,-Wimplicit-int-float-conversion]
*threshold = rate *
Patchew URL:
https://patchew.org/QEMU/20200619020602.118306-1-da...@gibson.dropbear.id.au/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
The default behaviour for virtio devices is not to use the platforms normal
DMA paths, but instead to use the fact that it's running in a hypervisor
to directly access guest memory. That doesn't work if the guest's memory
is protected from hypervisor access, such as with AMD's SEV or POWER's PEF.
This allows failures to be reported richly and idiomatically.
Signed-off-by: David Gibson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/kvm/kvm-all.c | 4 +++-
include/exec/host-trust-limitation.h | 2 +-
target/i386/sev.c|
The kvm_memcrypt_enabled() and kvm_memcrypt_encrypt_data() helper functions
don't conceptually have any connection to KVM (although it's not possible
in practice to use them without it).
They also rely on looking at the global KVMState. But the same information
is available from the machine, and
Some upcoming POWER machines have a system called PEF (Protected
Execution Facility) which uses a small ultravisor to allow guests to
run in a way that they can't be eavesdropped by the hypervisor. The
effect is roughly similar to AMD SEV, although the mechanisms are
quite different.
Most of the
Several architectures have mechanisms which are designed to protect guest
memory from interference or eavesdropping by a compromised hypervisor. AMD
SEV does this with in-chip memory encryption and Intel has a similar
mechanism. POWER's Protected Execution Framework (PEF) accomplishes a
similar
We haven't yet implemented the fairly involved handshaking that will be
needed to migrate PEF protected guests. For now, just use a migration
blocker so we get a meaningful error if someone attempts this (this is the
same approach used by AMD SEV).
Signed-off-by: David Gibson
---
At the moment AMD SEV sets a special function pointer, plus an opaque
handle in KVMState to let things know how to encrypt guest memory.
Now that we have a QOM interface for handling things related to host trust
limitation, use a QOM method on that interface, rather than a bare function
pointer
A number of hardware platforms are implementing mechanisms whereby the
hypervisor does not have unfettered access to guest memory, in order
to mitigate the security impact of a compromised hypervisor.
AMD's SEV implements this with in-cpu memory encryption, and Intel has
its own memory encryption
When the "memory-encryption" property is set, we also disable KSM
merging for the guest, since it won't accomplish anything.
We want that, but doing it in the property set function itself is
thereoretically incorrect, in the unlikely event of some configuration
environment that set the property
Currently the "memory-encryption" property is only looked at once we get to
kvm_init(). Although protection of guest memory from the hypervisor isn't
something that could really ever work with TCG, it's not conceptually tied
to the KVM accelerator.
In addition, the way the string property is
On Thu, Jun 18, 2020 at 1:03 AM Bin Meng wrote:
>
> On Wed, Jun 17, 2020 at 3:30 AM Atish Patra wrote:
> >
> > Currently, all riscv machines have identical reset vector code
> > implementations with memory addresses being different for all machines.
> > They can be easily combined into a single
On Thu, Jun 18, 2020 at 1:26 AM Bin Meng wrote:
>
> On Wed, Jun 17, 2020 at 3:29 AM Atish Patra wrote:
> >
> > Currently, the fdt is copied to the ROM after the reset vector. The firmware
> > has to copy it to DRAM. Instead of this, directly copy the device tree to a
> > pre-computed dram
On Wed, Jun 10, 2020 at 11:37:14PM +0200, Halil Pasic wrote:
> On Wed, 10 Jun 2020 14:25:54 +1000
> David Gibson wrote:
>
> > > > I'm going to definitely have a good look at that. What I think special
> > > > about s390 is that F_ACCESS_PLATFORM is hurting us because all IO needs
> > > > to go
On Wed, Jun 10, 2020 at 03:57:03PM +0200, Halil Pasic wrote:
> On Wed, 10 Jun 2020 14:29:29 +1000
> David Gibson wrote:
>
> > On Tue, Jun 09, 2020 at 06:28:39PM +0200, Halil Pasic wrote:
> > > On Tue, 9 Jun 2020 17:47:47 +0200
> > > Claudio Imbrenda wrote:
> > >
> > > > On Tue, 9 Jun 2020
On Wed, Jun 10, 2020 at 03:19:22PM +0200, Viktor Mihajlovski wrote:
>
>
> On 6/10/20 12:24 PM, David Hildenbrand wrote:
> > On 10.06.20 12:07, David Gibson wrote:
> > > On Wed, Jun 10, 2020 at 09:22:45AM +0200, David Hildenbrand wrote:
> > > > On 10.06.20 06:31, David Gibson wrote:
> > > > > On
On Wed, Jun 10, 2020 at 12:24:14PM +0200, David Hildenbrand wrote:
> On 10.06.20 12:07, David Gibson wrote:
> > On Wed, Jun 10, 2020 at 09:22:45AM +0200, David Hildenbrand wrote:
> >> On 10.06.20 06:31, David Gibson wrote:
> >>> On Tue, Jun 09, 2020 at 12:44:39PM -0400, Michael S. Tsirkin wrote:
>
Another way to reproduce this bug is with qemu-s390x and a cross-
compiled binary:
$ s390x-linux-gnu-gcc-5 -static -o bug-sqrtl-one-line.s390x bug-sqrtl-one-line.c
$ qemu-s390x bug-sqrtl-one-line.s390x
Segmentation fault (core dumped)
Find attached the binary.
** Attachment added: "statically
On Mon, Jun 15, 2020 at 11:20:31AM +0200, Greg Kurz wrote:
> On Sat, 13 Jun 2020 17:18:04 +1000
> David Gibson wrote:
>
> > On Thu, Jun 11, 2020 at 03:40:33PM +0200, Greg Kurz wrote:
> > > Nested KVM-HV only works on POWER9.
> > >
> > > Signed-off-by: Greg Kurz
> > > Reviewed-by: Laurent
Public bug reported:
When I try to use -fsoption on OSX I receive this error:
-fsdev local,security_model=mapped,id=fsdev0,path=devel/dmos-example:
There is no option group 'fsdev'
** Affects: qemu
Importance: Undecided
Status: New
--
You received this bug notification because
On 6/12/20 9:20 PM, Lijun Pan wrote:
> This patch series add several newly introduced 32/64-bit vector
> instructions in Power ISA 3.1. The newly added instructions are
> flagged as ISA300 temporarily in vmx-ops.inc.c and vmx-impl.inc.c
> to make them compile and function since Power ISA 3.1,
On 6/12/20 9:20 PM, Lijun Pan wrote:
> +#define VDIV_MOD_DO(name, op, element) \
> +void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> +{ \
> +int i;
On 6/12/20 9:20 PM, Lijun Pan wrote:
> The prototypes of muls64/mulu64 in host-utils.h should match the
> definitions in host-utils.c
>
> Signed-off-by: Lijun Pan
> ---
> include/qemu/host-utils.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
CC:
On 6/12/20 9:20 PM, Lijun Pan wrote:
> +void helper_vmulhsd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> + int i;
> + uint64_t h64 = 0;
> + uint64_t l64 = 0;
> +
> + for (i = 0; i < 2; i++) {
> + muls64(, , a->s64[i], b->s64[i]);
> + r->s64[i] = h64;
> +
On 6/12/20 9:20 PM, Lijun Pan wrote:
> +#define VMULH_DO(name, op, element, cast_orig, cast_temp)\
> +void helper_vmulh##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> \
> +{
> \
> + int i;
On Thu, Jun 18, 2020 at 3:42 PM Palmer Dabbelt wrote:
>
> On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistai...@gmail.com wrote:
> > On Thu, May 28, 2020 at 11:13 AM Alistair Francis
> > wrote:
> >>
> >> On Thu, May 21, 2020 at 8:57 AM Alistair Francis
> >> wrote:
> >> >
> >> > On Wed, May 20,
On 6/12/20 9:20 PM, Lijun Pan wrote:
> vmulld: Vector Multiply Low Doubleword.
>
> Signed-off-by: Lijun Pan
> ---
> target/ppc/helper.h | 1 +
> target/ppc/int_helper.c | 1 +
> target/ppc/translate/vmx-impl.inc.c | 1 +
> target/ppc/translate/vmx-ops.inc.c | 1 +
>
On 6/12/20 9:20 PM, Lijun Pan wrote:
> POWER ISA 3.1 introduces following byte-reverse instructions:
> brd: Byte-Reverse Doubleword X-form
> brw: Byte-Reverse Word X-form
> brh: Byte-Reverse Halfword X-form
>
> Signed-off-by: Lijun Pan
> ---
> target/ppc/translate.c | 62
On 6/15/20 1:53 PM, Lijun Pan wrote:
>>> +static inline void uint128_add(uint64_t ah, uint64_t al, uint64_t bh,
>>> + uint64_t bl, uint64_t *rh, uint64_t *rl, uint64_t *ca)
>>> +{
>>> + __uint128_t a = (__uint128_t)ah << 64 | (__uint128_t)al;
>>> + __uint128_t b = (__uint128_t)bh <<
Patchew URL:
https://patchew.org/QEMU/2020061858.23287-1-wall...@linux.ibm.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistai...@gmail.com wrote:
On Thu, May 28, 2020 at 11:13 AM Alistair Francis wrote:
On Thu, May 21, 2020 at 8:57 AM Alistair Francis wrote:
>
> On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt wrote:
> >
> > On Thu, 14 May 2020 13:47:10 PDT (-0700),
Of course it’s open source, I get that. When I say „xyz should be done“
then in the sense of „2+2 should be 4“ not in the sense of „you must
implement xyz right now“ ;)
Nonetheless, if you run e.g. on an ARM platform the command
qemu-system-x86_64 -cpu help
then it shouldn’t list a slew of CPUs
Patchew URL:
https://patchew.org/QEMU/2020061858.23287-1-wall...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v3 0/8] s390: Extended-Length SCCB & DIAGNOSE 0x318
Type: series
Message-id:
As more features and facilities are added to the Read SCP Info (RSCPI)
response, more space is required to store them. The space used to store
these new features intrudes on the space originally used to store CPU
entries. This means as more features and facilities are added to the
RSCPI response,
The start of the CPU entry region in the Read SCP Info response data is
denoted by the offset_cpu field. As such, QEMU needs to begin creating
entries at this address. Note that the length of the Read SCP Info data
(data_len) denotes the same value as the cpu offset.
This is in preparation of
DIAGNOSE 0x318 (diag318) is an s390 instruction that allows the storage
of diagnostic information that is collected by the firmware in the case
of hardware/firmware service events.
QEMU handles the instruction by storing the info in the CPU state. A
subsequent register sync will communicate the
Signed-off-by: Collin Walling
---
linux-headers/asm-s390/kvm.h | 5 -
linux-headers/linux/kvm.h| 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/linux-headers/asm-s390/kvm.h b/linux-headers/asm-s390/kvm.h
index 0138ccb0d8..98665dff19 100644
---
Functions within read scp/cpu info will need access to the machine
state. Let's make a call to retrieve the machine state once and
pass the appropriate data to the respective functions.
Signed-off-by: Collin Walling
Reviewed-by: David Hildenbrand
Reviewed-by: Thomas Huth
---
hw/s390x/sclp.c |
The header of the SCCB contains the actual length of the SCCB. Instead
of using a static 4K size, let's allow for a variable size determined
by the value set in the header. The proper checks are already in place
to ensure the SCCB length is sufficent to store a full response, and
that the length
Rework the SCLP boundary check to account for different SCLP commands
(eventually) allowing different boundary sizes.
Move the length check code into a separate function, and introduce a
new function to determine the length of the read SCP data (i.e. the size
from the start of the struct to where
The SCCB must be checked for a sufficient length before it is filled
with any data. If the length is insufficient, then the SCLP command
is suppressed and the proper response code is set in the SCCB header.
Fixes: 832be0d8a3bb ("s390x: sclp: Report insufficient SCCB length")
Signed-off-by: Collin
Changelog:
v3
• Device IOCTLs removed
- diag 318 info is now communicated via sync_regs
• Reset code removed
- this is now handled in KVM
- diag318_info is stored within the CPU reset portion of the
S390CPUState
• Various cleanups for ELS
BTW: just because I bracket a report with why I think a matter is worth
fixing, shouldn’t make it „invalid“.
The instructions aren’t implemented, yet the CPUs are listed as
available, which is a bug in my book, as functionality is advertised
that is unavailable.
--
You received this bug
The comments with the other reports were just in support of getting them
fixed, and providing a reason as to why that matters. Someone looking at
those reports may not read this one, and as the issues are symptoms of
the same larger issue, this report was filed as an overarching report,
as AVX is
> On Jun 15, 2020, at 3:49 AM, Stefan Hajnoczi wrote:
>
>
> It's challenging to implement a fast and secure IOMMU. The simplest
> approach is secure but not fast: add protocol messages for
> DMA_READ(iova, length) and DMA_WRITE(iova, buffer, length).
>
We do have protocol messages
Patchew URL: https://patchew.org/QEMU/20200618210649.22451-1-jrt...@jrtc27.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
Claiming an interrupt and changing the source priority both potentially
affect whether an interrupt is pending, thus we must re-compute xEIP.
Note that we don't put the sifive_plic_update inside sifive_plic_claim
so that the logging of a claim (and the resulting IRQ) happens before
the state
On 6/18/20 10:03 AM, Richard Henderson wrote:
> First, this could definitely be delayed to the follow-on linux-user patch set.
Bah, no, I need the function to be defined at least,
even if it isn't reachable yet.
r~
On 6/18/20 4:12 PM, Michael S. Tsirkin wrote:
On Wed, Jun 17, 2020 at 07:59:51AM -0400, Stefan Berger wrote:
On 6/17/20 4:22 AM, Auger Eric wrote:
Hi Stefan,
On 6/16/20 10:57 PM, Stefan Berger wrote:
From: Stefan Berger
Move the TPM TIS IRQ to unused IRQ 13, which is the only one accepted
Le 15/06/2020 à 15:03, Peter Maydell a écrit :
On Thu, 4 Jun 2020 at 13:39, Jean-Christophe Dubois
wrote:
improve the PHY implementation with more generic code.
This patch remove a lot of harcoded values to replace them with
generic symbols from header files.
Signed-off-by: Jean-Christophe
On Thu, 18 Jun 2020 at 20:41, Aleksandar Markovic
wrote:
> четвртак, 18. јун 2020., Aleksandar Markovic
> је написао/ла:
>> You may recall that I signalled on couple of occasions that there are some
>> problems related to gcov builds in out-of-tree builds.
>>
>> It turned out that those
Patchew URL: https://patchew.org/QEMU/20200618202343.20455-1-jrt...@jrtc27.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
On Thu, 18 Jun 2020 at 20:36, Gautam Bhat wrote:
> I am confused with the usage of PCI bus for connecting different
> peripherals. If I want to emulate an ARM board which doesn't have a
> PCI controller how can I emulate it to be as close to the real board
> as possible? Is there an ARM
The source priorities can be used to order sources with respect to other
sources, not just as a way to enable/disable them based off a threshold.
We must therefore always claim the highest-priority source, rather than
the first source we find.
Signed-off-by: Jessica Clarke
---
Changes since v1:
>
>> 2. Unclear semantics. Alex tried to document what the actual semantics
>> of hinted pages are. Assume the following in the guest to a previously
>> hinted page
>>
>> /* page was hinted and is reused now */
>> if (page[x] != Y)
>>page[x] == Y;
>> /* migration ends, we now run on the
On Wed, Jun 17, 2020 at 07:59:51AM -0400, Stefan Berger wrote:
> On 6/17/20 4:22 AM, Auger Eric wrote:
> > Hi Stefan,
> >
> > On 6/16/20 10:57 PM, Stefan Berger wrote:
> > > From: Stefan Berger
> > >
> > > Move the TPM TIS IRQ to unused IRQ 13, which is the only one accepted by
> > > Windows.
On Wed, Jun 17, 2020 at 09:11:28AM +0200, Gerd Hoffmann wrote:
> First batch of microvm patches, some generic acpi stuff.
> Split the acpi-build.c monster, specifically split the
> pc and q35 and pci bits into a separate file which we
> can skip building at some point in the future.
Thanks for
On Wed, Jun 17, 2020 at 09:11:36AM +0200, Gerd Hoffmann wrote:
> The _STA methods for COM+LPT used to reference them,
> but that isn't the case any more.
>
> piix4 DSDT changes:
>
> Scope (_SB.PCI0)
> {
> Device (ISA)
> {
> Name (_ADR, 0x0001) //
On Wed, Jun 17, 2020 at 09:11:30AM +0200, Gerd Hoffmann wrote:
> DSDT change: isa device order changes in case MI1 (ipmi) is present.
>
> Signed-off-by: Gerd Hoffmann
> Reviewed-by: Igor Mammedov
> ---
Pls follow process outlined at the top of tests/qtest/bios-tables-test.c
Don't change
On Wed, Jun 17, 2020 at 09:11:33AM +0200, Gerd Hoffmann wrote:
> DSDT change: isa device order changes in case MI1 (ipmi) is present.
>
> Signed-off-by: Gerd Hoffmann
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Igor Mammedov
> ---
> hw/i386/acpi-build.c| 39
Patchew URL: https://patchew.org/QEMU/20200618193556.19459-1-jrt...@jrtc27.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
On 18/06/2020 21:03, Claudio Fontana wrote:
> move the vcpu throttling functionality into its own module.
>
> This functionality is not specific to any accelerator,
> and it is used currently by migration to slow down guests to try to
> have migrations converge, and by the cocoa MacOS UI to
On Thu, Jun 18, 2020 at 10:10 AM David Hildenbrand wrote:
>
> >>
> >> Ugh, ...
> >>
> >> @MST, you might have missed that in another discussion, what's your
> >> general opinion about removing free page hinting in QEMU (and Linux)? We
> >> keep finding issues in the QEMU implementation, including
четвртак, 18. јун 2020., Aleksandar Markovic <
aleksandar.qemu.de...@gmail.com> је написао/ла:
> Hi, Alex, Peter.
>
> You may recall that I signalled on couple of occasions that there are some
> problems related to gcov builds in out-of-tree builds.
>
> It turned out that those problems manifest
On 18/06/2020 21:03, Claudio Fontana wrote:
> move arch_init, balloon, cpus, ioport, memory, memory_mapping, qtest.
>
> They are all specific to CONFIG_SOFTMMU.
>
> Signed-off-by: Claudio Fontana
> Reviewed-by: Alex Bennée
> ---
> MAINTAINERS | 12 ++--
The source priorities can be used to order sources with respect to other
sources, not just as a way to enable/disable them based off a threshold.
We must therefore always claim the highest-priority source, rather than
the first source we find.
Signed-off-by: Jessica Clarke
---
Hi,
I am confused with the usage of PCI bus for connecting different
peripherals. If I want to emulate an ARM board which doesn't have a
PCI controller how can I emulate it to be as close to the real board
as possible? Is there an ARM interconnect or something where I can
connect the peripheral
Hi, Alex, Peter.
You may recall that I signalled on couple of occasions that there are some
problems related to gcov builds in out-of-tree builds.
It turned out that those problems manifest on some opder Linux
distribution, and are always related to the gcovr being older than 4.1. For
older
On Thu, Jun 18, 2020 at 08:16:55PM +0100, Dr. David Alan Gilbert wrote:
> * Vivek Goyal (vgo...@redhat.com) wrote:
> > On Thu, Apr 16, 2020 at 05:49:05PM +0100, Stefan Hajnoczi wrote:
> > > virtiofsd doesn't need of all Linux capabilities(7) available to root.
> > > Keep a
> > > whitelisted set
Patchew URL: https://patchew.org/QEMU/20200618190401.4895-1-cfont...@suse.de/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
export
On 6/18/20 6:33 AM, Peter Maydell wrote:
> On Wed, 3 Jun 2020 at 02:13, Richard Henderson
> wrote:
>>
>> Raise an exception if the given virtual memory is not accessible.
>>
>> Signed-off-by: Richard Henderson
>> ---
>
>> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
>>
* Vivek Goyal (vgo...@redhat.com) wrote:
> On Thu, Apr 16, 2020 at 05:49:05PM +0100, Stefan Hajnoczi wrote:
> > virtiofsd doesn't need of all Linux capabilities(7) available to root.
> > Keep a
> > whitelisted set of capabilities that we require. This improves security in
> > case virtiofsd is
Patchew URL: https://patchew.org/QEMU/20200618190401.4895-1-cfont...@suse.de/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
Patchew URL: https://patchew.org/QEMU/20200618190401.4895-1-cfont...@suse.de/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!
On Thu, Apr 16, 2020 at 05:49:05PM +0100, Stefan Hajnoczi wrote:
> virtiofsd doesn't need of all Linux capabilities(7) available to root. Keep a
> whitelisted set of capabilities that we require. This improves security in
> case virtiofsd is compromised by making it hard for an attacker to gain
refactoring of cpus.c continues with cpu timer state extraction.
cpu-timers: responsible for the cpu timers state, and for access to
cpu clocks and ticks.
icount: counts the TCG instructions executed. As such it is specific to
the TCG accelerator. Therefore, it is built only under CONFIG_TCG.
move the vcpu throttling functionality into its own module.
This functionality is not specific to any accelerator,
and it is used currently by migration to slow down guests to try to
have migrations converge, and by the cocoa MacOS UI to throttle speed.
cpu-throttle contains the controls to
move arch_init, balloon, cpus, ioport, memory, memory_mapping, qtest.
They are all specific to CONFIG_SOFTMMU.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
---
MAINTAINERS | 12 ++--
Makefile.target | 7 ++-
each accelerator registers a new "CpusAccel" interface
implementation on initialization, providing functions for
starting a vcpu, kicking a vcpu, and sychronizing state.
This way the code in cpus.c is now all general softmmu code,
nothing accelerator-specific anymore.
There is still some
Motivation and higher level steps:
https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg04628.html
MAIN OPEN POINTS:
* confirmation on hvf state (Roman)
* naming of "cpus.c" and functions, more cpus_ prefix use? (Roman)
* should we accept the addional clunkyness and overhead for each call
* Alexander Duyck (alexander.du...@gmail.com) wrote:
> On Tue, May 26, 2020 at 9:14 PM Alexander Duyck
> wrote:
> >
> > From: Alexander Duyck
> >
> > In an upcoming patch a feature named Free Page Reporting is about to be
> > added. In order to avoid any confusion we should drop the use of the
On Thu, 18 Jun 2020 at 19:08, Richard Henderson
wrote:
>
> On 6/18/20 3:52 AM, Peter Maydell wrote:
> >> +if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte,
> >> cpu)) {
> >> +if (ri->opc1 == 6) { /* SCTLR_EL3 */
> >> +value &= ~(SCTLR_ITFSB | SCTLR_TCF |
> On Jun 17, 2020, at 7:42 PM, no-re...@patchew.org wrote:
>
> Patchew URL:
> https://patchew.org/QEMU/20200618001127.34438-1-...@linux.ibm.com/
>
>
>
> Hi,
>
> This series failed the asan build test. Please find the testing commands and
> their output below. If you have Docker installed,
On Thu, Jun 18, 2020 at 1:56 AM Bin Meng wrote:
>
> On Wed, Jun 17, 2020 at 3:29 AM Atish Patra wrote:
> >
> > This series adds support OpenSBI dynamic firmware support to Qemu.
> > Qemu loader passes the information about the DT and next stage (i.e. kernel
> > or U-boot) via "a2" register. It
On 6/18/20 3:52 AM, Peter Maydell wrote:
>> +if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu))
>> {
>> +if (ri->opc1 == 6) { /* SCTLR_EL3 */
>> +value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);
>> +} else {
>> +value &=
On Thu, 18 Jun 2020 at 18:04, Richard Henderson
wrote:
> First, this could definitely be delayed to the follow-on linux-user patch set.
>
> Second, in the linux-user patch set, I decode the syndrome data to determine
> what kind of segv to deliver for MTE synchronous faults. It would be easy to
Aleksandar, Alex, see comment #1.
I think the problem happens because I moved the syscall_nr.h from source
directory to build directory. If source directory is not cleaned up
correctly, the build will not generate the new header in the build
directory but in source directory and some targets that
For -icount mode to work, there are requirements on the target/
code (notably around marking up "I/O" instructions). Unfortunately
we've never documented what these are, which makes it pretty rough
for people writing new targets or reviewing changes to existing ones.
Does anybody understand what
On 6/18/20 9:39 AM, Peter Maydell wrote:
>> t = cpu->isar.id_aa64pfr1;
>> t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
>> +t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
>> cpu->isar.id_aa64pfr1 = t;
>
> If we don't actually have tagged memory yet should we really
> set the
On 6/18/20 9:37 AM, Peter Maydell wrote:
>> +/* Return true if tbi bits mean that the access is checked. */
>> +static inline bool tbi_check(uint32_t desc, int bit55)
>> +{
>> +return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1;
>> +}
>> +
>> +/* Return true if tcma bits mean that the access
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