"Dr. David Alan Gilbert" writes:
> * 江芳杰 (18401698...@126.com) wrote:
>> Hi:
>> Sorry to bother you~
>> I have read the discussions about CVE--2019-12928 (
>> https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg01153.html).
>> But, for the scenario of PC users, which is no requireme
On Jan 20 09:44, Minwoo Im wrote:
> On 21-01-19 19:18:16, Klaus Jensen wrote:
> > On Jan 20 02:01, Minwoo Im wrote:
> > > Hello,
> > >
> > > This patch series is third one to support multi-controller and namespace
> > > sharing in multi-path. This series introduced subsystem scheme to
> > > manag
Patchew URL:
https://patchew.org/QEMU/20210120074102.51534-1-marcandre.lur...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210120074102.51534-1-marcandre.lur...@redhat.com
Subject: [PATCH v2] RFC: sphin
From: Marc-André Lureau
The default "alabaster" sphinx theme has a couple shortcomings:
- the navbar moves along the page
- the search bar is not always at the same place
- it lacks some contrast and colours
The "rtd" theme from readthedocs.org is a popular third party theme used
notably by the
19.01.2021 23:21, Eric Blake wrote:
On 10/26/20 12:17 PM, Vladimir Sementsov-Ogievskiy wrote:
Experiments show, that copy_range is not always making things faster.
So, to make experimentation simpler, let's add a parameter. Some more
perf parameters will be added soon, so here is a new struct.
Disks work differently depending on the x86 machine type (SATA vs PATA).
Additionally, we should fuzz the atapi code paths, which might contain
vulnerabilities such as CVE-2020-29443. This patch adds hard-disk and
cdrom generic-fuzzer configs for both the pc (PATA) and q35 (SATA)
machine types.
Si
We passed an is_write flag to the fuzz_dma_read_cb function to
differentiate between the mapped DMA regions that need to be populated
with fuzzed data, and those that don't. We simply passed through the
address_space_map is_write parameter. The goal was to cut down on
unnecessarily populating mappe
On 1/19/2021 4:34 PM, Peter Maydell wrote:
On Tue, 15 Dec 2020 at 18:11, Paolo Bonzini wrote:
From: Alejandro Jimenez
The current default action of pausing a guest after a panic event
is received leaves the responsibility to resume guest execution to the
management layer. The reasons for t
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1214884
Title:
Support VDI
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1284090
Title:
RFE: QMP: r
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1619991
Title:
Concurrent
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/824074
Title:
Provide runt
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1674925
Title:
Qemu PPC64
Patchew URL:
https://patchew.org/QEMU/163349-24906-1-git-send-email-tsimp...@quicinc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 163349-24906-1-git-send-email-tsimp...@quicinc.com
Subject: [PATCH v7 00/
Enable multiarch tests for Hexagon
Modify tests/tcg/configure.sh
Add reference files to tests/tcg/hexagon
---
tests/tcg/configure.sh| 4 +-
tests/tcg/hexagon/Makefile.target | 30 ++
tests/tcg/hexagon/float_convs.ref | 748 +
tests/tcg/hexagon/flo
---
tests/tcg/hexagon/fpstuff.c | 370 ++
tests/tcg/hexagon/Makefile.target | 1 +
2 files changed, 371 insertions(+)
create mode 100644 tests/tcg/hexagon/fpstuff.c
diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c
new file mode 10
Include the generated files and set up the data structures
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.h | 25 +
target/hexagon/genptr.c | 236
2 files changed, 261 insertions(+)
create mode 100644 target/hexagon/genptr.h
create
This was defined at some point before ARMv8.4, and will
shortly be used by new processor descriptions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
I've pulled this out of a largely defunct 2019 branch. This will
be required for the cortex-a76. Aside from simplistic isar ch
Implementation of Linux user emulation for Hexagon
Some common files modified in addition to new files in linux-user/hexagon
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
---
linux-user/hexagon/sockbits.h | 18 ++
linux-user/hexagon/syscall_nr.h | 322 +
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.h | 35 ++
target/hexagon/arch.c | 294 ++
2 files changed, 329 insertions(+)
create mode 100644 target/hexagon/arch.h
create mode 100644 target/hexagon/arch.c
diff --git a/target/hexagon
Read the instruction memory
Create a packet data structure
Generate TCG code for the start of the packet
Invoke the generate function for each instruction
Generate TCG code for the end of the packet
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 91 ++
target/hexagon/transla
GDB register read and write routines
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé dump_state = hexagon_dump_state;
cc->set_pc = hexagon_cpu_set_pc;
cc->synchronize_from_tb = hexagon_cpu_synchronize_from_tb;
+cc->gdb_read_register
Helpers won't work if there are multiple definitions, so we override these
instructions using #define fGEN_TCG_.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 198 +++
1 file changed, 198 insertions(+)
create mode 100644 target/hexagon/
The imported code uses host floating point. We override them
to use qemu softfloat
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 121 +++
1 file changed, 121 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.
From: Alessandro Di Federico
Signed-off-by: Alessandro Di Federico
Tested-by: Taylor Simpson
---
.../debian-hexagon-cross-build-local.docker| 18 +++
.../debian-hexagon-cross.build-toolchain.sh| 141 +
.../docker/dockerfiles/debian-hexagon-cross.docker |
Python scripts generate the following files
helper_protos_generated.h
For each instruction we create DEF_HELPER function prototype
helper_funcs_generated.h
For each instruction we create the helper function definition
tcg_funcs_generated.h
For each instruction we
macros to interface with the generator
macros referenced in instruction semantics
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 591
1 file changed, 591 insertions(+)
create mode 100644 target/hexagon/macros.h
diff --git a/target/h
Run the C preprocessor across the instruction definition files and macro
definition file to expand macros and prepare the semantics_generated.pyinc
file. The resulting file contains one entry with the semantics for each
instruction and one line with the instruction attributes associated with
each
Add hexagon to disas/meson.build
Add disas/hexagon.c
Add hexagon to include/disas/dis-asm.h
Signed-off-by: Taylor Simpson
Tested-by: Philippe Mathieu-Daudé http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * QEMU Hexagon Disassembler
+ */
+
+#include "qemu/osdep.h"
+#include "disas/dis-asm.h"
+#include
Signed-off-by: Taylor Simpson
---
target/hexagon/fma_emu.h | 37 +++
target/hexagon/fma_emu.c | 702 +++
2 files changed, 739 insertions(+)
create mode 100644 target/hexagon/fma_emu.h
create mode 100644 target/hexagon/fma_emu.c
diff --git a/target/h
Python script that emits the decode tree in dectree_generated.h.
Signed-off-by: Taylor Simpson
---
target/hexagon/dectree.py | 351 ++
1 file changed, 351 insertions(+)
create mode 100755 target/hexagon/dectree.py
diff --git a/target/hexagon/dectree.
Signed-off-by: Taylor Simpson
---
target/hexagon/attribs.h | 30 ++
target/hexagon/attribs_def.h | 95
2 files changed, 125 insertions(+)
create mode 100644 target/hexagon/attribs.h
create mode 100644 target/hexagon/attribs_def.h
dif
---
tests/tcg/hexagon/atomics.c | 139 ++
tests/tcg/hexagon/dual_stores.c | 60 ++
tests/tcg/hexagon/mem_noshuf.c| 328
tests/tcg/hexagon/misc.c | 380 ++
tests/tcg/hexagon/preg_alias.c|
The insn_t and packet_t are the interface between instruction decoding and
TCG code generation
Signed-off-by: Taylor Simpson
---
target/hexagon/insn.h | 74 +++
1 file changed, 74 insertions(+)
create mode 100644 target/hexagon/insn.h
diff --git
Define types used in files imported from the Hexagon architecture library
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_arch_types.h | 38 ++
1 file changed, 38 insertions(+)
create mode 100644 target/hexagon/hex_arch_types.h
diff --git a/target/hexag
Signed-off-by: Taylor Simpson
---
target/hexagon/opcodes.h | 63 +
target/hexagon/opcodes.c | 142 +++
2 files changed, 205 insertions(+)
create mode 100644 target/hexagon/opcodes.h
create mode 100644 target/hexagon/opcodes.c
dif
Run the C preprocessor across the instruction definition and encoding
files to expand macros and prepare the iset.py file. The resulting
fill contains python data structures used to build the decode tree.
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé http://www.gnu.org/licens
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_PRINTINSN_H
+#define HEXAGON_PRINTINSN_H
+
+#include "qemu/osdep.h"
+#include "insn.h"
+
+extern void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
+
Add file to default-configs
Add hexagon to meson.build
Add hexagon to target/meson.build
Add target/hexagon/meson.build
Change scripts/qemu-binfmt-conf.sh
We can build a hexagon-linux-user target and run programs on the Hexagon
scalar core. With hexagon-linux-clang installed, "make check-tcg" wil
The majority of helpers are generated. Define the helper functions needed
then include the generated file
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 85
target/hexagon/op_helper.c | 1066
2 files changed, 1151 insertions(+)
Declare bitfields within registers such as user status register (USR)
Signed-off-by: Taylor Simpson
---
target/hexagon/reg_fields.h | 36
target/hexagon/reg_fields_def.h | 41 +
target/hexagon/reg_fields.c | 27
Take the words from instruction memory and build a packet_t for TCG code
generation
The following operations are performed
Convert the .new encoded offset to the register number of the producer
Reorder the packet so .new producer is before consumer
Apply constant extenders
Separate
Add target state header, target definitions and initialization routines
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu-param.h | 29 +
target/hexagon/cpu.h | 159 +++
target/hexagon/cpu_bits.h | 59 +
target/hexagon/internal.h | 36 ++
target/
Determine legal VLIW slots for each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/iclass.h| 50 ++
target/hexagon/iclass.c| 73 ++
target/hexagon/imported/iclass.def | 51 ++
Gives an introduction and overview to the Hexagon target
Signed-off-by: Taylor Simpson
---
target/hexagon/README | 235 ++
1 file changed, 235 insertions(+)
create mode 100644 target/hexagon/README
diff --git a/target/hexagon/README b/target/hexa
Signed-off-by: Taylor Simpson
---
target/hexagon/conv_emu.h | 31
target/hexagon/conv_emu.c | 177 ++
2 files changed, 208 insertions(+)
create mode 100644 target/hexagon/conv_emu.h
create mode 100644 target/hexagon/conv_emu.c
diff --git a/
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
---
target/hexagon/hex_regs.h | 83 +++
1 file changed, 83 insertions(+)
create mode 100644 target/hexagon/hex_regs.h
diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h
new
Define EM_HEXAGON 164
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/elf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/elf.h b/include/elf.h
index 7a418ee..f4fa3c1 100644
--- a/incl
This series adds support for the Hexagon processor with Linux user support
See patch 02/33 Hexagon README for detailed information.
This series assumes int128_or() is implemented.
https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg06004.html
The series is also available at https://githu
Add Taylor Simpson as the Hexagon target maintainer
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3216387..b07ceb4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -187,6 +18
Only define the register if it exists for the cpu.
Signed-off-by: Richard Henderson
---
I've pulled this out of a largely defunct 2019 branch. This will
be required for the cortex-a76, which only implements aa32 at el0.
This did get some review, back in the day,
https://lists.gnu.org/archive/h
Reviewed-by: Cameron Esfahani mailto:di...@apple.com>>
Cameron Esfahani
di...@apple.com
> On Jan 12, 2021, at 10:07 PM, Hill Ma wrote:
>
> This prevents illegal instruction on cpus do not support xgetbv.
>
> Buglink: https://bugs.launchpad.net/qemu/+bug/1758819
> Signed-off-by: Hill Ma
> ---
On 1/19/21 6:09 AM, Peter Maydell wrote:
> On Fri, 15 Jan 2021 at 21:23, Richard Henderson
> wrote:
>>
>> This requires finishing the conversion to tcg_target_op_def.
>> Remove quite a lot of ifdefs, since we can reference opcodes
>> even if they are not implemented.
>>
>> Signed-off-by: Richard H
On Tue, Jan 19, 2021 at 3:46 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Upgrade OpenSBI from v0.8 to v0.9 and the pre-built bios images.
>
> The v0.9 release includes the following commits:
>
> 35bc810 docs/platform: Update QEMU parameter for fw_payload
> 78afe11 config.mk: Update QEMU run command
> Isn't the HBitmap slightly overkill? Can qemu/bitmap.h suffice?
Definitely, yes, I think. Current patch series supoprt up to 32
controllers so I think qemu/bitmap.h is enough for us.
Will update the bitmap operations in the next series.
> Minwoo, try pulling the most current nvme-cli. There was a sysfs
> scanning bug for non-mpath drives that should be fixed now.
Thank you, Keith! I've posted list result based on the latest one :)
On 21-01-19 19:18:16, Klaus Jensen wrote:
> On Jan 20 02:01, Minwoo Im wrote:
> > Hello,
> >
> > This patch series is third one to support multi-controller and namespace
> > sharing in multi-path. This series introduced subsystem scheme to
> > manage controller(s) and namespace(s) in the subsyste
On Tue, Jan 19, 2021 at 05:58:24PM -0300, Daniel Henrique Barboza wrote:
> Commit 006e9d361869 added warning messages for cap-cfpc, cap-ibs and
> cap-sbbc when enabled under TCG. Commit 8ff43ee404d3 did the same thing
> when introducing cap-ccf-assist.
>
> These warning messages, although benign t
On Tue, Jan 19, 2021 at 11:14:52AM +0100, Klaus Jensen wrote:
> From: Klaus Jensen
>
> This is a resend of "hw/block/nvme: allow cmb and pmr to coexist" with
> some more PMR work added (PMR RDS/WDS support).
>
> This includes a resurrection of Andrzej's series[1] from back July.
>
> Andrzej's m
On Mon, Nov 16, 2020 at 6:57 PM Marc-André Lureau
wrote:
>
> Hi,
>
> On Thu, Nov 5, 2020 at 8:03 PM wrote:
> >
> > From: Marc-André Lureau
> >
> > The default "alabaster" sphinx theme has a couple shortcomings:
> > - the navbar moves along the page
> > - the search bar is not always at the same
On 1/19/21 5:27 AM, Peter Maydell wrote:
> On Fri, 15 Jan 2021 at 21:20, Richard Henderson
> wrote:
>>
>> This exports the constraint sets from tcg_target_op_def to
>> a place we will be able to manipulate more in future.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> tcg/i386/tcg-target-con-s
From: Bin Meng
Upgrade OpenSBI from v0.8 to v0.9 and the pre-built bios images.
The v0.9 release includes the following commits:
35bc810 docs/platform: Update QEMU parameter for fw_payload
78afe11 config.mk: Update QEMU run command for generic and sifive fu540
platforms
ec3e5b1 docs/platform:
On 1/20/21 12:06 AM, BALATON Zoltan wrote:
> On Tue, 19 Jan 2021, Richard Henderson wrote:
>> My recent change for caching tcg constants has, in a number of cases,
>> overflowed the statically allocated array of temporaries. Change to
>> dynamic allocation.
>
> This seems to work for me so
>
> T
On 1/19/21 4:58 AM, Peter Maydell wrote:
> On Fri, 15 Jan 2021 at 21:14, Richard Henderson
> wrote:
>>
>> Signed-off-by: Richard Henderson
>> ---
>> tcg/sparc/tcg-target-con-str.h | 22 +
>> tcg/sparc/tcg-target.h | 5 +---
>> tcg/sparc/tcg-target.c.inc | 45 +---
On 1/18/21 6:03 PM, Philippe Mathieu-Daudé wrote:
> We are not ready to handle additional CDB data.
>
> If a guest send a packet with such additional data,
> report the command parameter as not supported.
>
> We can then explicit there is nothing in this additional
> buffer, by fixing its size to
On 1/20/21 12:20 AM, Philippe Mathieu-Daudé wrote:
> Hi Eric,
>
> On 1/20/21 12:07 AM, Eric Blake wrote:
>> ../hw/usb/dev-uas.c:157:31: error: field 'status' with variable sized type
>> 'uas_iu' not at the end of a struct or class is a GNU extension
>> [-Werror,-Wgnu-variable-sized-type-not-at-e
Hi Eric,
On 1/20/21 12:07 AM, Eric Blake wrote:
> ../hw/usb/dev-uas.c:157:31: error: field 'status' with variable sized type
> 'uas_iu' not at the end of a struct or class is a GNU extension
> [-Werror,-Wgnu-variable-sized-type-not-at-end]
> uas_iustatus;
>
../hw/usb/dev-uas.c:157:31: error: field 'status' with variable sized type
'uas_iu' not at the end of a struct or class is a GNU extension
[-Werror,-Wgnu-variable-sized-type-not-at-end]
uas_iustatus;
^
Fix this by specifying a size for the ad
On Tue, 19 Jan 2021, Richard Henderson wrote:
My recent change for caching tcg constants has, in a number of cases,
overflowed the statically allocated array of temporaries. Change to
dynamic allocation.
This seems to work for me so
Tested-by: BALATON Zoltan
but have you done any performanc
On 1/15/21 12:13 PM, Alistair Francis wrote:
>> +#define ALL_GENERAL_REGS 0xu
>> +#ifdef CONFIG_SOFTMMU
>> +#define ALL_QLDST_REGS \
>> +(ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \
>> + (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \
>> +
On 1/19/21 4:50 AM, Peter Maydell wrote:
> On Fri, 15 Jan 2021 at 21:14, Richard Henderson
> wrote:
>>
>> Signed-off-by: Richard Henderson
>> ---
>> tcg/mips/tcg-target-con-str.h | 24
>> tcg/mips/tcg-target.h | 1 +
>> tcg/mips/tcg-target.c.inc | 72 ---
On 11/16/20 5:56 AM, Marc-André Lureau wrote:
Hi,
On Thu, Nov 5, 2020 at 8:03 PM wrote:
From: Marc-André Lureau
The default "alabaster" sphinx theme has a couple shortcomings:
- the navbar moves along the page
- the search bar is not always at the same place
- it lacks some contrast and col
> On Jan 14, 2021, at 11:47 AM, yaroshchuk2...@gmail.com wrote:
>
> From: Vladislav Yaroshchuk
>
> For `-accel hvf` cpu_x86_cpuid() is wrapped with hvf_cpu_x86_cpuid() to
> add paravirtualization cpuid leaf 0x4010
> https://lkml.org/lkml/2008/10/1/246
>
> Leaf 0x4010, Timing Informat
Hi--
On 1/12/21 4:15 AM, Adrian Catangiu wrote:
> - Background and problem
>
> ---
> Documentation/misc-devices/sysgenid.rst | 240 +
> drivers/misc/Kconfig| 16 ++
> drivers/misc/Makefile | 1 +
> drivers/misc/sysgenid.c
On 1/15/21 10:04 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/mips/tcg-target-con-str.h | 24
> tcg/mips/tcg-target.h | 1 +
> tcg/mips/tcg-target.c.inc | 72 ---
> 3 files changed, 41 insertions(+), 56 delet
On 1/14/21 6:27 PM, Dongli Zhang wrote:
> The virtio device/driver (e.g., vhost-scsi) may hang due to the lost of IRQ
s/lost/loss/
> or the lost of doorbell register kick, e.g.,
and again
>
> https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg01711.html
>
> This patch adds a new debug i
On 1/15/21 10:04 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/tci/tcg-target-con-str.h | 11 +++
> tcg/tci/tcg-target.h | 2 ++
> tcg/tci/tcg-target.c.inc | 14 --
> 3 files changed, 13 insertions(+), 14 deletions(-)
> create mode 1
Hi,
Current virtiofsd code uses libvhost-user and I am assuming virtiofsd-rs
uses it too. I am wondering what are the locking requirements for
this library.
Looking at it it does not look like thread safe. Well parts of of kind
of look thread safe. For example, David Gilbert introduced a slave_mu
On 1/19/21 7:55 PM, Richard Henderson wrote:
> Provide a symbol that can always be used to signal an error,
> regardless of optimization. Usage of this should be protected
> by e.g. __builtin_constant_p, which guards for optimization.
>
> Signed-off-by: Richard Henderson
> ---
> include/qemu/co
On 1/18/21 8:59 AM, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrangé (berra...@redhat.com) wrote:
>> On Thu, Jan 14, 2021 at 04:27:28PM -0800, Dongli Zhang wrote:
>>> The virtio device/driver (e.g., vhost-scsi and indeed any device including
>>> e1000e) may hang due to the lost of IRQ or th
On 1/17/21 10:52 AM, Philippe Mathieu-Daudé wrote:
> On 1/16/21 11:38 PM, Alistair Francis wrote:
>> On Sat, Jan 16, 2021 at 2:32 PM Philippe Mathieu-Daudé
>> wrote:
>>>
>>> On 1/16/21 12:00 AM, Alistair Francis wrote:
We were accidently passing RISCVHartArrayState by value instead of
accid
On Tue, 15 Dec 2020 at 18:11, Paolo Bonzini wrote:
>
> From: Alejandro Jimenez
>
> The current default action of pausing a guest after a panic event
> is received leaves the responsibility to resume guest execution to the
> management layer. The reasons for this behavior are discussed here:
> htt
On Wed, Jan 06, 2021 at 06:21:20PM +0300, Andrey Gruzdev wrote:
> Add BCC/eBPF script to analyze userfaultfd write fault latency distribution.
>
> Signed-off-by: Andrey Gruzdev
> Acked-by: Peter Xu
(This seems to be the last patch that lacks a r-b ... Let's see whether I could
convert my a-b i
For ISM devices, use the vfio region to handle intercepted PCILG
instructions. This will allow read I/Os intercepted from the guest to be
performed as single operations that ensure the same non-MIO PCI instruction
is used on the host as specified in the guest.
Signed-off-by: Matthew Rosato
---
Certain zPCI device types (e.g. ISM) allow for a different set of address
alignment rules for PCISTB instructions. Recognize this distinction and
perform only a subset of alignment checks for intercepted PCISTB
instructions. Furthermore for the default path, handle the potential for
writes that a
As inftrastructure to introduce different PCI instruction handlers,
introduce the ZpciOps structure to contain function pointers for the
handlers. Add default handlers for the PCISTG, PCILG and PCISTB
instructions.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c | 3 +
hw/s
s390 PCI currently disallows PCI devices without the MSI-X capability.
However, this fence doesn't make sense for passthrough devices. Move
the check to only fence emulated devices (e.g., virtio).
Signed-off-by: Matthew Rosato
Reviewed-by: Pierre Morel
---
hw/s390x/s390-pci-bus.c | 14
Hi,
This is the v20 of the patchset. This version has the following changes:
[PATCH v18 08/20] io: add qio_channel_readv_full_all_eof &
qio_channel_readv_full_all helpers
- Considers fds as part of the "data" for both
qio_channel_readv_full_all_eof() &
qio_channel_readv_
Add ProxyMemoryListener object which is used to keep the view of the RAM
in sync between QEMU and remote process.
A MemoryListener is registered for system-memory AddressSpace. The
listener sends SYNC_SYSMEM message to the remote process when memory
listener commits the changes to memory, the remot
Commit 006e9d361869 added warning messages for cap-cfpc, cap-ibs and
cap-sbbc when enabled under TCG. Commit 8ff43ee404d3 did the same thing
when introducing cap-ccf-assist.
These warning messages, although benign to the machine launch, can make
users a bit confused. E.g:
$ sudo ./ppc64-softmmu/q
From: Elena Ufimtseva
Defines MPQemuMsg, which is the message that is sent to the remote
process. This message is sent over QIOChannel and is used to
command the remote process to perform various tasks.
Define transmission functions used by proxy and by remote.
Signed-off-by: Jagannathan Raman
From: Elena Ufimtseva
Adds qio_channel_writev_full_all() to transmit both data and FDs.
Refactors existing code to use this helper.
Signed-off-by: Elena Ufimtseva
Signed-off-by: John G Johnson
Signed-off-by: Jagannathan Raman
Reviewed-by: Stefan Hajnoczi
Acked-by: Daniel P. Berrangé
---
in
Placeholder commit to pull in changes from "vfio-pci/zdev: Pass the relaxed
alignment flag" and "vfio-pci/zdev: Introduce the PCISTB vfio region"
Signed-off-by: Matthew Rosato
---
.../infiniband/hw/vmw_pvrdma/pvrdma_verbs.h| 2 +-
include/standard-headers/drm/drm_fourcc.h | 17
Today, ISM devices are completely disallowed for vfio-pci passthrough as
QEMU rejects the device due to an (inappropriate) MSI-X check. Removing
this fence, however, reveals additional deficiencies in the s390x PCI
interception layer that prevent ISM devices from working correctly.
Namely, ISM blo
On 1/19/21 8:44 PM, Gerd Hoffmann wrote:
> Log all traffic of a specific usb device to a pcap file for later
> inspection. File format is compatible with linux usb monitor.
>
> Usage:
> qemu -device usb-${somedevice},pcap=file.pcap
> wireshark file.pcap
Great!
> Signed-off-by: Gerd Hoffmann
x-remote-machine object sets up various subsystems of the remote
device process. Instantiate PCI host bridge object and initialize RAM, IO &
PCI memory regions.
Signed-off-by: John G Johnson
Signed-off-by: Jagannathan Raman
Signed-off-by: Elena Ufimtseva
Reviewed-by: Stefan Hajnoczi
---
inclu
From: John G Johnson
Signed-off-by: John G Johnson
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
Reviewed-by: Stefan Hajnoczi
---
docs/devel/index.rst | 1 +
docs/devel/multi-process.rst | 966 +++
MAINTAINERS
From: Elena Ufimtseva
Perform device reset in the remote process when QEMU performs
device reset. This is required to reset the internal state
(like registers, etc...) of emulated devices
Signed-off-by: Elena Ufimtseva
Signed-off-by: John G Johnson
Signed-off-by: Jagannathan Raman
Reviewed-by
From: Elena Ufimtseva
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
Signed-off-by: John G Johnson
Reviewed-by: Stefan Hajnoczi
---
include/hw/remote/mpqemu-link.h | 4
hw/remote/mpqemu-link.c | 34 ++
2 files changed, 38 inserti
If the underlying host does not provide CLP capabilities, we cannot tell
what type of function is being passed through, which means for ISM devices
we can't properly tell if the vfio I/O region is necessary. If the ISM
device is allowed to pass through erroneously, it will not function
properly wi
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