On 7/12/2021 5:55 PM, Richard Henderson wrote:
The goal here was to address Brad's report for clang vs ppc32.
Somewhere in between here and there I forgot about the ppc32 part,
needed a newer clang for gcc135, accidentally built master instead
of the clang-12 release branch, fixed a bunch of
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1913668
Title:
FPE in
On Fri, 2021-08-13 at 06:50 -0400, Alexander Bulekov wrote:
> >
> > My question is about address_space_map() -- How do we emulate double-
> > fetch
> > bugs in the same map/unmap session? For example:
> >
>
> Hi Qiuhao,
> Right now we don't. One strategy would be to use mprotect. When the
>
Reviewed-by: Huacai Chen
On Fri, Aug 13, 2021 at 7:02 PM Philippe Mathieu-Daudé wrote:
>
> Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
> 1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
> 48 virtual address bits in each 64-bit segment, not 40.
>
> Fixes: af868995e1b
Reviewed-by: Huacai Chen
On Fri, Aug 13, 2021 at 7:01 PM Philippe Mathieu-Daudé wrote:
>
> Document the cores on which each Loongson-3A CPU is based (see
> commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
Net option "-hostfwd" now supports IPv6 addresses.
Commands hostfwd_add, hostfwd_remove now support IPv6 addresses.
Tested:
avocado run tests/acceptance/hostfwd.py
Signed-off-by: Doug Evans
---
Changes from v7:
No changes.
Changes from v6:
No changes.
Changes from v5:
Recognize
... in preparation for adding ipv6 host forwarding support.
Tested:
avocado run tests/acceptance/hostfwd.py
Signed-off-by: Doug Evans
---
Changes from v7:
No changes.
Changes from v6:
Add support for --enable-slirp=system
Tested with system libslirp 4.4.0.
Changes from v5:
Use
This patchset takes the original patch from Maxim,
https://www.mail-archive.com/qemu-devel@nongnu.org/msg569573.html
and updates it.
Option hostfwd is extended to support ipv6 addresses.
Commands hostfwd_add, hostfwd_remove are extended as well.
Changes from v7:
None really, except to remove
The parsing is moved into new function inet_parse_host_port.
Also split out is ipv4=flag, ipv6=flag processing into inet_parse_ipv46.
This is done in preparation for using these functions in net/slirp.c.
Signed-off-by: Doug Evans
Reviewed-by: Marc-André Lureau
---
Changes from v7:
No changes.
If users try to add an isa-vga device that was already registered,
still in command line, qemu will crash:
$ qemu-system-mips64el -M pica61 -device isa-vga
RAMBlock "vga.vram" already registered, abort!
Aborted (core dumped)
That particular board registers such device automaticaly, so it's
not
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of read only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Use unique unit numbers in quanta-gsj eeprom files.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx_boards.c | 15 ++-
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 54cf9785ec..be6c81b29d
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 79 +++--
1 file changed, 45 insertions(+), 34 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/adc/npcm7xx_adc.c | 2 +-
This patch set contains a few bug fixes and I2C devices for some
NPCM7XX boards.
Patch 1~2 fix a problem that causes the SMBus module to behave
incorrectly when it's in FIFO mode and trying to receive more than
16 bytes at a time.
Patch 3 fixes a error in a register for ADC module.
Patch 4
In NPCM7xx boards, at24c eeproms are backed by drives. However,
these drives use unit number as unique identifier. So if we
specify two drives with the same unit number, error will occured:
`Device with id 'none85' exists`.
Instead of using i2c address as unit number, we now assign unique
unit
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by:
Both qemu and qemu-img use writeback cache mode by default, which is
already documented in qemu(1). qemu-nbd uses writethrough cache mode by
default, and the default cache mode is not documented.
According to the qemu-nbd(8):
--cache=CACHE
The cache mode to be used with the file.
On Fri, Aug 13, 2021 at 04:05:06PM +0100, Peter Maydell wrote:
> Zero-initialize sockaddr_in and sockaddr_un structs that we're about
> to fill in and pass to bind() or connect(), to ensure we don't leave
> possible implementation-defined extension fields as uninitialized
> garbage.
>
>
On Fri, Aug 13, 2021 at 04:05:05PM +0100, Peter Maydell wrote:
> Zero-initialize the sockaddr_in struct that we're about to fill in
> and pass to bind(), to ensure we don't leave possible
> implementation-defined extension fields as uninitialized garbage.
>
> Signed-off-by: Peter Maydell
> ---
>
On Fri, Aug 13, 2021 at 04:05:04PM +0100, Peter Maydell wrote:
> Zero-initialize sockaddr_in and sockaddr_un structs that we're about
> to fill in and pass to bind() or connect(), to ensure we don't leave
> possible implementation-defined extension fields as uninitialized
> garbage.
>
>
On Fri, Aug 13, 2021 at 04:05:03PM +0100, Peter Maydell wrote:
> We don't currently zero-initialize the 'struct sockaddr_in' that
> parse_host_port() fills in, so any fields we don't explicitly
> initialize might be left as random garbage. POSIX states that
> implementations may define extensions
On Fri, Aug 13, 2021 at 04:05:02PM +0100, Peter Maydell wrote:
> The POSIX spec for sockaddr_in says that implementations are allowed
> to have implementation-dependent extensions controlled by extra
> fields in the struct, and that the way to ensure these are not
> accidentally activated is to
On Fri, 13 Aug 2021 at 17:59, Richard Henderson
wrote:
>
> On 8/13/21 12:37 AM, Peter Maydell wrote:
> > These changes look OK as far as they go, but it's not clear to
> > me why the other places that set P_REXW are all OK to use P_REXW
> > and not P_VEXW. For instance tcg_out_mov() sets rexw =
From: johannst
Ping.
https://patchew.org/QEMU/20210805193950.514357-1-johannes.sto...@gmail.com/
https://lore.kernel.org/qemu-devel/20210805193950.514357-1-johannes.sto...@gmail.com/
Thanks and best,
Johannes
On 8/13/21 6:59 AM, Richard Henderson wrote:
On 8/13/21 12:37 AM, Peter Maydell wrote:
These changes look OK as far as they go, but it's not clear to
me why the other places that set P_REXW are all OK to use P_REXW
and not P_VEXW. For instance tcg_out_mov() sets rexw = P_REXW
and some of the
On 8/13/21 12:37 AM, Peter Maydell wrote:
These changes look OK as far as they go, but it's not clear to
me why the other places that set P_REXW are all OK to use P_REXW
and not P_VEXW. For instance tcg_out_mov() sets rexw = P_REXW
and some of the codepaths there will then pass that into
On Fri, Aug 13, 2021 at 03:02:22PM +0530, Naveen wrote:
> +static uint16_t nvme_identify_ns_common(NvmeCtrl *n, NvmeRequest *req)
> +{
> +NvmeIdNs id_ns = {};
> +
> +id_ns.nsfeat |= (0x4 | 0x10);
> +id_ns.dpc = 0x1f;
> +
> +NvmeLBAF lbaf[16] = {
> +[0] = {.ds = 9},
> +
On Fri, 13 Aug 2021 at 07:44, Wen, Jianxian
wrote:
>
> From f780b0ee2ee36c562ab814915fff0e7217b25e63 Mon Sep 17 00:00:00 2001
>
> From: Jianxian Wen
>
> Date: Tue, 3 Aug 2021 09:44:35 +0800
>
> Subject: [PATCH] hw/dma/pl330: Add memory region to replace default
>
> address_space_memory
>
>
>
>
On Tue, 10 Aug 2021 at 17:03, Guenter Roeck wrote:
>
> Instantiate SAI1/2/3 and ASRC as unimplemented devices to avoid random
> Linux kernel crashes, such as
Applied to target-arm.next for 6.2 with the ^Ms cleaned up, thanks.
-- PMM
> In the real SMP hardware topology world, it's much more likely that
> we have high cores-per-socket counts and few sockets totally. While
> the current preference of sockets over cores in smp parsing results
> in a virtual cpu topology with low cores-per-sockets counts and a
> large number of
On Fri, 6 Aug 2021 at 15:47, Jan Luebbe wrote:
>
> Break events are currently only handled by chardev/char-serial.c, so we
> just ignore errors, which results in no behaviour change for other
> chardevs.
>
> Signed-off-by: Jan Luebbe
Applied to target-arm.next for 6.2, thanks.
If you're
On Wed, 28 Jul 2021 at 08:30, Paolo Bonzini wrote:
>
> On 28/07/21 01:52, Hamza Mahfooz wrote:
> > As per commit 5626f8c6d468 ("rcu: Add automatically released rcu_read_lock
> > variants"), RCU_READ_LOCK_GUARD() should be used instead of
> > rcu_read_{un}lock().
> >
> > Signed-off-by: Hamza
On Fri, Aug 13, 2021 at 10:37:00AM -0400, Shengtan Mao wrote:
> Hi Corey,
> Thank you so much for your feedback. I took some time to discuss these
> points with my team.
>
> 1. Blocking QEMU I/O
> Thanks for bringing this to our attention. We acknowledge it as a drawback,
> but we hope that by
On Tue, 10 Aug 2021 at 05:40, David Gibson wrote:
>
> On Mon, Aug 09, 2021 at 10:57:00AM +0100, Peter Maydell wrote:
> >
> > Cleanest fix would be to declare 'path' and 'host' as
> >g_autofree char *path = NULL;
> >g_autofree char *host = NULL;
> > and then you can remove all the manual
On Fri, Aug 6, 2021 at 12:28 AM John Snow wrote:
>
>
> On Fri, Jul 30, 2021 at 4:19 PM G S Niteesh Babu
> wrote:
>
>> Added a draft of AQMP TUI.
>>
>> Implements the follwing basic features:
>> 1) Command transmission/reception.
>> 2) Shows events asynchronously.
>> 3) Shows server status in
Zero-initialize sockaddr_in and sockaddr_un structs that we're about
to fill in and pass to bind() or connect(), to ensure we don't leave
possible implementation-defined extension fields as uninitialized
garbage.
Signed-off-by: Peter Maydell
---
tests/tcg/multiarch/linux-test.c | 4 ++--
1 file
Zero-initialize the sockaddr_in struct that we're about to fill in
and pass to bind(), to ensure we don't leave possible
implementation-defined extension fields as uninitialized garbage.
Signed-off-by: Peter Maydell
---
tests/qtest/ipmi-bt-test.c | 2 +-
1 file changed, 1 insertion(+), 1
We don't currently zero-initialize the 'struct sockaddr_in' that
parse_host_port() fills in, so any fields we don't explicitly
initialize might be left as random garbage. POSIX states that
implementations may define extensions in sockaddr_in, and that those
extensions must not trigger if
The POSIX spec for sockaddr_in says that implementations are allowed
to have implementation-dependent extensions controlled by extra
fields in the struct, and that the way to ensure these are not
accidentally activated is to zero out the whole data structure.
We have several places in our codebase
Zero-initialize sockaddr_in and sockaddr_un structs that we're about
to fill in and pass to bind() or connect(), to ensure we don't leave
possible implementation-defined extension fields as uninitialized
garbage.
Signed-off-by: Peter Maydell
---
gdbstub.c | 4 ++--
1 file changed, 2
> -Original Message-
> From: Peter Maydell
> Sent: Friday, August 13, 2021 3:21 AM
> To: Taylor Simpson
> Cc: QEMU Developers ; Richard Henderson
> ; Philippe Mathieu-Daudé
>
> Subject: Re: [PULL 0/1] Hexagon (disas/hexagon) fix memory leak for early
> exit
>
>
> I'll put this on my
> On Jul 20, 2021, at 10:17 AM, Thanos Makatos
> wrote:
>
>> -Original Message-
>> From: Jagannathan Raman
>> Sent: 19 July 2021 21:00
>> To: qemu-devel@nongnu.org
>> Cc: stefa...@redhat.com; alex.william...@redhat.com;
>> elena.ufimts...@oracle.com; John Levon ;
>>
On Fri, Aug 6, 2021 at 12:41 AM John Snow wrote:
>
>
> On Fri, Jul 30, 2021 at 4:19 PM G S Niteesh Babu
> wrote:
>
>> Added a draft of AQMP TUI.
>>
>> Implements the follwing basic features:
>> 1) Command transmission/reception.
>> 2) Shows events asynchronously.
>> 3) Shows server status in
Hi Corey,
Thank you so much for your feedback. I took some time to discuss these
points with my team.
1. Blocking QEMU I/O
Thanks for bringing this to our attention. We acknowledge it as a drawback,
but we hope that by indicating this clearly in an updated docs, the user
will accept these
The following changes since commit 703e8cd6189cf699c8d5c094bc68b5f3afa6ad71:
Update version for v6.1.0-rc3 release (2021-08-10 19:08:09 +0100)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to
From: Daniel P. Berrangé
machine_set_smp() mistakenly checks 'errp' not '*errp',
and so thinks there is an error every single time it runs.
This causes it to jump to the end of the method, skipping
the max CPUs checks. The caller meanwhile sees no error
and so carries on execution. The result of
From: Philippe Mathieu-Daudé
If dies is not supported by this machine's CPU topology, don't
keep processing options and return directly.
Fixes: 0aebebb561c ("machine: reject -smp dies!=1 for non-PC machines")
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
From: Lara Lazier
~0UL has 64 bits on Linux and 32 bits on Windows.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/512
Reported-by: Volker Rümelin
Signed-off-by: Lara Lazier
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
Use the new force_sig_fault() function instead of setting up
a target_siginfo_t and calling queue_signal().
Signed-off-by: Peter Maydell
---
linux-user/aarch64/cpu_loop.c | 34 +-
1 file changed, 9 insertions(+), 25 deletions(-)
diff --git
In many places in the linux-user code we need to queue a signal for
the guest using the QEMU_SI_FAULT si_type. This requires that the
caller sets up and passes us a target_siginfo, including setting the
appropriate part of the _sifields union for the si_type. In a number
of places the code
When generating a TRAP_BRKPT SIGTRAP, set the siginfo_t addr field
to the PC where the breakpoint/singlestep trap occurred; this is
what the kernel does for this signal for this architecture.
Fixes: Coverity 1459154
Signed-off-by: Peter Maydell
---
linux-user/aarch64/cpu_loop.c | 1 +
1 file
The target_siginfo_t we populate in force_sig() will eventually
get copied onto the target's stack. Zero it out so that any extra
padding in the sifields union is consistently zero when the guest
sees it.
Signed-off-by: Peter Maydell
---
linux-user/signal.c | 2 +-
1 file changed, 1
In the Arm target code, when the fpa11 emulation code tells us we
need to send the guest a SIGFPE, we do this with queue_signal(), but
we are using the wrong si_type, and we aren't setting the _sifields
union members corresponding to either the si_type we are using or the
si_type we should be
Use the new force_sig_fault() function instead of setting up
a target_siginfo_t and calling queue_signal().
Signed-off-by: Peter Maydell
---
I threw in a comment confirming that the si_addr value for the "bad
SWI immediate" SIGILL really is different from the PC value reported
in the ucontext_t
When generating a TRAP_BRKPT SIGTRAP, set the siginfo_t addr field
to the PC where the breakpoint/singlestep trap occurred; this is
what the kernel does for this signal for this architecture.
Signed-off-by: Peter Maydell
---
linux-user/arm/cpu_loop.c | 1 +
1 file changed, 1 insertion(+)
diff
Coverity reported that we don't set the _sifields union when queuing
the SIGTRAP for EXCP_DEBUG events on aarch64. This series fixes that
bug and a few others, and cleans up the way we queue fault signals
to be less error-prone.
The underlying cause of the bug is that when queueing a signal
the
This patch supports namespace management : create and delete operations.
This patch has been tested with the following command and size of image
file for unallocated namespaces is taken as 0GB. ns_create will look into
the list of unallocated namespaces and it will initialize the same and
return
On 12/08/21 19:53, Daniel P. Berrangé wrote:
The machine_set_smp() mistakenly checks 'errp' not '*errp',
and so thinks there is an error every single time it runs.
This causes it to jump to the end of the method, skipping
the max CPUs checks. The caller meanwhile sees no error
and so carries on
On 13/08/21 13:26, Philippe Mathieu-Daudé wrote:
If dies is not supported by this machine's CPU topology, don't
keep processing options and return directly.
Fixes: 0aebebb561c ("machine: reject -smp dies!=1 for non-PC machines")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/machine.c | 1
On 12/08/21 17:15, Peter Maydell wrote:
The realpath() function can return NULL on error, so we need to check
for it to avoid crashing when we try to strstr() into it.
This can happen if we run out of memory, or if /sys/ is not mounted,
among other situations.
Fixes: Coverity 1459913, 1460474
On 13/08/21 13:26, Philippe Mathieu-Daudé wrote:
Just for consistency, following the example documented since
commit e3fe3988d7 ("error: Document Error API usage rules"),
return a boolean value indicating an error is set or not.
Directly pass errp as the local_err is not requested in our
case.
From: Daniel P. Berrangé
The machine_set_smp() mistakenly checks 'errp' not '*errp',
and so thinks there is an error every single time it runs.
This causes it to jump to the end of the method, skipping
the max CPUs checks. The caller meanwhile sees no error
and so carries on execution. The
Just for consistency, following the example documented since
commit e3fe3988d7 ("error: Document Error API usage rules"),
return a boolean value indicating an error is set or not.
Directly pass errp as the local_err is not requested in our
case.
Signed-off-by: Philippe Mathieu-Daudé
---
Respin of Daniel's series checking MachineClass::smp_parse()
return value instead of *errp.
Daniel P. Berrangé (1):
hw/core: fix error checkig in smp_parse
Philippe Mathieu-Daudé (2):
hw/core: Add missing return on error
hw/core: Have MachineClass::smp_parse() return boolean on error
If dies is not supported by this machine's CPU topology, don't
keep processing options and return directly.
Fixes: 0aebebb561c ("machine: reject -smp dies!=1 for non-PC machines")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/machine.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.
Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé
---
Document the cores on which each Loongson-3A CPU is based (see
commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu-defs.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Raise Loongson-3A1000 SEGBITS from 40 to 48.
Philippe Mathieu-Daudé (2):
target/mips: Document Loongson-3A CPU definitions
target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
target/mips/cpu-defs.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--
2.31.1
On 210813 0349, Li Qiuhao wrote:
> Hi Alex,
>
> Recently I was reading the DMA call-back functions in the fuzzer. It seems
> fuzz_dma_read_cb() is inserted into flatview_read_continue() and
> address_space_map() to make the host read changed content between different
> DMA actions.
>
> My
On Wed, 11 Aug 2021 at 00:26, Richard Henderson
wrote:
>
> We need to be able to represent VEX.W on a 32-bit host, where REX.W
> will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385
> Signed-off-by: Richard Henderson
>
On Wed, 11 Aug 2021 at 00:26, Richard Henderson
wrote:
>
> We need to be able to represent VEX.W on a 32-bit host, where REX.W
> will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385
> Signed-off-by: Richard Henderson
On Fri, 13 Aug 2021 at 04:07, Taylor Simpson wrote:
>
> The following changes since commit 703e8cd6189cf699c8d5c094bc68b5f3afa6ad71:
>
> Update version for v6.1.0-rc3 release (2021-08-10 19:08:09 +0100)
>
> are available in the git repository at:
>
> https://github.com/quic/qemu
On Fri, 13 Aug 2021 at 01:57, Alistair Francis wrote:
>
> On Fri, Aug 13, 2021 at 2:17 AM Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Peter,
> >
> > On 8/12/21 4:46 PM, Peter Maydell wrote:
> > > In the riscv virt machine init function, We assemble a string
> > > plic_hart_config which is a
On Thu, 12 Aug 2021 at 21:07, Richard Henderson
wrote:
>
> On 8/12/21 9:10 AM, matheus.fe...@eldorado.org.br wrote:
> > static bool avr_need_swap(CPUPPCState *env)
> > {
> > +bool le;
> > +#if defined(CONFIG_USER_ONLY)
> > +le = false;
> > +#else
> > +le = msr_le;
> > +#endif
>
>
On 8/12/2021 11:06 PM, Peter Maydell wrote:
In the alignment check added to qemu_ram_alloc_from_fd() in commit
ce317be98db0dfdfa, the condition includes a check that 'mr' is not
NULL. This check is unnecessary because we can assume that the
caller always passes us a valid MemoryRegion, and
On 12/08/2021 18:53, Shashi Mallela wrote:
> Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
> translation which triggers an LPI via INT command as well as write
> to GITS_TRANSLATER register,defined enum to differentiate between ITS
> command interrupt trigger and
On 8/12/2021 11:15 PM, Peter Maydell wrote:
The realpath() function can return NULL on error, so we need to check
for it to avoid crashing when we try to strstr() into it.
This can happen if we run out of memory, or if /sys/ is not mounted,
among other situations.
Fixes: Coverity 1459913,
>From f780b0ee2ee36c562ab814915fff0e7217b25e63 Mon Sep 17 00:00:00 2001
From: Jianxian Wen
Date: Tue, 3 Aug 2021 09:44:35 +0800
Subject: [PATCH] hw/dma/pl330: Add memory region to replace default
address_space_memory
PL330 needs a memory region which can connect with SMMU translate IOMMU region
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