Re: [PATCH 1/2] target/riscv: optimize condition assign for scale < 0

On Fri, Mar 25, 2022 at 7:03 PM Weiwei Li wrote: > > for some cases, scale is always equal or less than 0, since lmul is not > larger than 3 > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Thanks! Applied to riscv-to-apply.next Alistair > --- >

[PATCH for-7.0 v2] target/mips: Fix address space range declaration on n32

This bug is probably lurking there for so long, I cannot even git-blame my way to the commit first introducing it. Anyway, because n32 is also TARGET_MIPS64, the address space range cannot be determined by looking at TARGET_MIPS64 alone. Fix this by only declaring 48-bit address spaces for n64,

Re: [PATCH] target/mips: Fix address space range declaration on n32

On 3/26/22 23:34, WANG Xuerui wrote: This bug is probably lurking there for so long, I cannot even git-blame my way to the commit first introducing it. Anyway, because n32 is also TARGET_MIPS64, the address space range cannot be determined by looking at TARGET_MIPS64 alone. Fix this by only

Re: [PATCH V2 4/4] intel-iommu: PASID support

On Thu, Mar 24, 2022 at 4:54 PM Tian, Kevin wrote: > > > From: Jason Wang > > Sent: Monday, March 21, 2022 1:54 PM > > > > This patch introduce ECAP_PASID via "x-pasid-mode". Based on the > > existing support for scalable mode, we need to implement the following > > missing parts: > > > > 1) tag

Re: [PATCH V2 3/4] intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function

On Thu, Mar 24, 2022 at 4:27 PM Tian, Kevin wrote: > > > From: Jason Wang > > Sent: Monday, March 21, 2022 1:54 PM > > @@ -1724,6 +1713,19 @@ out: > > trace_vtd_pt_enable_fast_path(source_id, success); > > } > > > > +static void vtd_qualify_report_fault(IntelIOMMUState *s, > > +

Re: [PATCH V2 1/4] intel-iommu: don't warn guest errors when getting rid2pasid entry

On Thu, Mar 24, 2022 at 4:21 PM Tian, Kevin wrote: > > > From: Jason Wang > > Sent: Monday, March 21, 2022 1:54 PM > > > > We use to warn on wrong rid2pasid entry. But this error could be > > triggered by the guest and could happens during initialization. So > > let's don't warn in this case. > >

Re: [PATCH 1/2] gdbstub: Set current_cpu for memory read write

On Thu, Mar 24, 2022 at 7:52 PM Peter Maydell wrote: > > On Thu, 24 Mar 2022 at 10:33, Alex Bennée wrote: > > I think we need to not use cpu_physical_memory_write (which is > > explicitly the system address space) but have a function that takes cpu > > so it can work out the correct address

[PATCH v2 4/4] migration: Calculate the appropriate throttle for autoconverge

From: Chongyun Wu The current autoconverge algorithm does not obtain the threshold that currently requires the CPU to limit the speed through calculation, but limits the speed of the CPU through continuous attempts. Start from an initial value to limit the speed. If the migration can not be

Re: [PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix

On Mon, Mar 28, 2022 at 7:30 AM Alistair Francis wrote: > On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI > wrote: > > > > Some bits in RISC-V `misa' CSR should not be reflected in the ISA > > string. For instance, `S' and `U' (represents existence of supervisor > > and user mode, respectively) in

[PATCH v2 3/4] kvm: Introduce a dirty rate calculation method based on dirty ring

From: Chongyun Wu A new structure KVMDirtyRingDirtyCounter is introduced in KVMDirtyRingReaper to record the number of dirty pages within a period of time. When kvm_dirty_ring_mark_page collects dirty pages, if it finds that the current dirty pages are not duplicates, it increases the

[PATCH v2 2/4] kvm: Dirty ring autoconverge optmization for kvm_cpu_synchronize_kick_all

From: Chongyun Wu Dirty ring feature need call kvm_cpu_synchronize_kick_all to flush hardware buffers into KVMslots, but when aucoverge run kvm_cpu_synchronize_kick_all calling will become more and more time consuming. This will significantly reduce the efficiency of dirty page queries,

[PATCH v2 1/4] kvm: Dynamically adjust the rate of dirty ring reaper thread

From: Chongyun Wu Dynamically adjust the dirty ring collection thread to reduce the occurrence of ring full, thereby reducing the impact on customers, improving the efficiency of dirty page collection, and thus improving the migration efficiency. Implementation: 1) Define different collection

[PATCH v2 0/4] Dirty ring and auto converge optimization

From: Chongyun Wu v2: -patch 1: remove patch_1 v1: -rebase to qemu/master Overview This series of patches is to optimize the performance of online migration using dirty ring and autoconverge. Mainly through the following aspects to do optimization: 1. Dynamically adjust the dirty

Re: [PATCH 1/2] target/riscv: optimize condition assign for scale < 0

On Fri, Mar 25, 2022 at 7:03 PM Weiwei Li wrote: > > for some cases, scale is always equal or less than 0, since lmul is not > larger than 3 > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvv.c.inc | 8

Re: [PATCH 2/2] target/riscv: optimize helper for vmvr.v

On Fri, Mar 25, 2022 at 7:01 PM Weiwei Li wrote: > > LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share > the same helper > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 5

Re: [PATCH 1/2] hw/core: Sync uboot_image.h from U-Boot v2022.01

On Thu, Mar 24, 2022 at 6:40 PM Bin Meng wrote: > > From: Bin Meng > > Sync uboot_image.h from upstream U-Boot v2022.01 release [1]. > > [1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > >

Re: [PATCH v2 2/2] hw/core: loader: Set is_linux to true for VxWorks uImage

On Thu, Mar 24, 2022 at 11:55 PM Bin Meng wrote: > > From: Bin Meng > > VxWorks 7 uses the same boot interface as the Linux kernel on Arm > (64-bit only), PowerPC and RISC-V architectures. Add logic to set > is_linux to true for VxWorks uImage for these architectures in > load_uboot_image(). > >

Re: [PATCH (PING) 0/1] target/riscv: misa to ISA string conversion fix

On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI wrote: > > [This is the same patch as previous ones] Hello, Thanks for the patch! > > (qemu-riscv only) This never made it to the QEMU mailing list >

Re: [PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix

On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI wrote: > > Some bits in RISC-V `misa' CSR should not be reflected in the ISA > string. For instance, `S' and `U' (represents existence of supervisor > and user mode, respectively) in `misa' CSR must not be copied since > neither `S' nor `U' are valid

Re: [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space

Rémi Denis-Courmont wrote: > The VTCR_EL2 specification says that the NSA bit "behaves as 1 for all > purposes > other than reading back the value of the bit when one of the following is > true > (...) > * The value of VTCR_EL2.NSW is 1. > * The value of VSTCR_EL2.SA is 1." > > Sorry but I

Re: [PATCH] target/mips: Fix address space range declaration on n32

Am Sonntag, 27. März 2022, 07:34:55 CEST schrieb WANG Xuerui: > This bug is probably lurking there for so long, I cannot even git-blame > my way to the commit first introducing it. > > Anyway, because n32 is also TARGET_MIPS64, the address space range > cannot be determined by looking at

Re: QEMU, UEFI and Windows with Bitlocker encryption

I didn’t get any response to this, but found out the solution myself, so I just thought I’d share the solution for anyone with a similar issue. Basically the root of this problem seems to have been TPM-related and not UEFI-related. So switching from a pass through-TPM to a swtpm for my VM

Problem for cross compiling to windows 10

Hi, I don't know at all how to use mingw i tried several days to make cross compile, sometimes under msys2 sometimes under ubuntu or even debian, i saw errors and errors i tried to remove. On Ubuntu i can compile but i have no *.exe at the end, probably a prefix problem but on the wiki page

Re: [PATCH v8 01/46] hw/pci/cxl: Add a CXL component type (interface)

On Fri, Mar 18, 2022 at 03:05:50PM +, Jonathan Cameron wrote: > From: Ben Widawsky > > A CXL component is a hardware entity that implements CXL component > registers from the CXL 2.0 spec (8.2.3). Currently these represent 3 > general types. > 1. Host Bridge > 2. Ports (root, upstream,

Re: [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space

Le sunnuntaina 27. maaliskuuta 2022, 12.34.26 EEST Idan Horowitz a écrit : > As per the AArch64.SS2OutputPASpace() psuedo-code in the ARMv8 ARM when the > PA space of the IPA is non secure, the output PA space is secure if and only > if all of the bits VTCR., VSTCR. are not set. > >

Re: [PATCH v4 2/2] qemu-binfmt-conf.sh: Extend magic to distinguish mips o32 and n32 ABI

On 3/24/22 07:05, Andreas K. Hüttel wrote: This information is given by the EF_MIPS_ABI2 (0x20) bit in the e_flags field of the ELF header (a 4-byte value at offset 0x24 for the here applicable ELFCLASS32). See-also: https://www.mail-archive.com/qemu-devel@nongnu.org/msg732572.html

Re: [PATCH v4 1/2] qemu-binfmt-conf.sh: allow elf EI_ABIVERSION=1 for mips

Hi Andreas, On 3/24/22 07:05, Andreas K. Hüttel wrote: With the command line flag -mplt and a recent toolchain, ELF binaries generated by gcc can obtain EI_ABIVERSION=1, see below, which makes, e.g., gcc three-stage bootstrap in a mips-unknown-linux-gnu qemu-user chroot fail since the

[PATCH 3/3] target/arm: Determine final stage 2 output PA space based on original IPA

As per the AArch64.S2Walk() psuedo-code in the ARMv8 ARM, the final decision as to the output address's PA space based on the SA/SW/NSA/NSA bits needs to take the input IPA's PA space into account, and not the PA space of the result of the stage 2 walk itself. Signed-off-by: Idan Horowitz ---

[PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space

As per the AArch64.SS2OutputPASpace() psuedo-code in the ARMv8 ARM when the PA space of the IPA is non secure, the output PA space is secure if and only if all of the bits VTCR., VSTCR. are not set. Signed-off-by: Idan Horowitz --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH 2/3] target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk

As per the AArch64.SS2InitialTTWState() psuedo-code in the ARMv8 ARM the initial PA space used for stage 2 table walks is assigned based on the SW and NSW bits of the VSTCR and VTCR registers. This was already implemented for the recursive stage 2 page table walks in S1_ptw_translate(), but was

[PATCH 0/3] Bug fixes related to secure 2 stage translation

Idan Horowitz (3): target/arm: Check VSTCR.SW when assigning the stage 2 output PA space target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk target/arm: Determine final stage 2 output PA space based on original IPA target/arm/helper.c | 16 ++-- 1 file

Re: [PATCH 3/4] python/qmp-shell: relicense as LGPLv2+

Hi On Sat, Mar 26, 2022 at 12:04 AM John Snow wrote: > > qmp-shell is presently licensed as GPLv2 (only). I intend to include > this tool as an add-on to an LGPLv2+ library package hosted on > PyPI.org. I've selected LGPLv2+ to maximize compatibility with other > licenses while retaining a