> -Original Message-
> From: Stefano Garzarella [mailto:sgarz...@redhat.com]
> Sent: Monday, March 28, 2022 11:12 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: stefa...@redhat.com; m...@redhat.com; coh...@redhat.com;
> pbonz...@redhat.com; Gonglei (Arei)
> -Original Message-
> From: Stefano Garzarella [mailto:sgarz...@redhat.com]
> Sent: Monday, March 28, 2022 11:00 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: Stefan Hajnoczi ; Michael Tsirkin ;
> Cornelia Huck ; Paolo Bonzini ;
> Gonglei (Arei) ;
> -Original Message-
> From: Stefano Garzarella [mailto:sgarz...@redhat.com]
> Sent: Monday, March 28, 2022 11:00 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: Stefan Hajnoczi ; Michael Tsirkin ;
> Cornelia Huck ; Paolo Bonzini ;
> Gonglei (Arei) ;
在 2022/3/28 下午4:45, Yi Liu 写道:
On 2022/3/21 13:54, Jason Wang wrote:
This patch introduce ECAP_PASID via "x-pasid-mode". Based on the
existing support for scalable mode, we need to implement the following
missing parts:
1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation
在 2022/3/28 下午4:53, Yi Liu 写道:
On 2022/3/28 10:27, Jason Wang wrote:
On Thu, Mar 24, 2022 at 4:21 PM Tian, Kevin
wrote:
From: Jason Wang
Sent: Monday, March 21, 2022 1:54 PM
We use to warn on wrong rid2pasid entry. But this error could be
triggered by the guest and could happens during
On Mon, Mar 28, 2022 at 3:03 PM Tian, Kevin wrote:
>
> > From: Jason Wang
> > Sent: Monday, March 21, 2022 1:54 PM
> >
> > +/*
> > + * vtd-spec v3.4 3.14:
> > + *
> > + * """
> > + * Requests-with-PASID with input address in range 0xFEEx_ are
> > + * translated
On Mon, Mar 28, 2022 at 2:47 PM Tian, Kevin wrote:
>
> > From: Jason Wang
> > Sent: Monday, March 28, 2022 10:31 AM
> >
> > On Thu, Mar 24, 2022 at 4:54 PM Tian, Kevin wrote:
> > >
> > > > From: Jason Wang
> > > > Sent: Monday, March 21, 2022 1:54 PM
> > > >
> > > > This patch introduce
On Mon, Mar 28, 2022 at 5:10 PM Peter Maydell wrote:
>
> On Mon, 28 Mar 2022 at 03:10, Bin Meng wrote:
> > IMHO it's too bad to just ignore this bug forever.
> >
> > This is a valid use case. It's not about whether we intentionally want
> > to inspect the GIC register value from gdb. The case is
On 3/28/22 14:14, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
This RFC is a first attempt at implementing the 128-bit integer
conversion routines in softfloat, as required by the xscv[su]qqp and
xscvqp[su]qz instructions of PowerISA v3.1.
Instead of using int128.h, int-to-float
On 3/28/22 06:57, Xiaojuan Yang wrote:
+ .global _start
+ .align 16
+_start:
+ bl main
You must at least set up the stack. This must work only via some interaction with efi
bios? What we *want* is for this to run by itself on the raw virt machine.
r~
On 3/28/22 06:57, Xiaojuan Yang wrote:
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 4 ++
hw/loongarch/fw_cfg.c| 33 ++
hw/loongarch/fw_cfg.h| 15 +++
hw/loongarch/loongson3.c | 76
On 3/29/22 07:39, Philippe Mathieu-Daudé wrote:
On 28/3/22 22:49, Andreas K. Hüttel wrote:
With the command line flag -mplt and a recent toolchain, ELF binaries
generated by gcc can obtain EI_ABIVERSION=1, which makes, e.g., gcc
three-stage bootstrap in a mips-unknown-linux-gnu qemu-user chroot
On Mon, Mar 28, 2022 at 09:59:16AM -0300, Daniel Henrique Barboza wrote:
> Hi,
>
> This is a memory leak found by Valgrind when testing vcpu
> hotplug/unplug in pSeries guests.
>
> Other vcpu hotplug/unplug leaks are still present in the common code
> (one in the KVM thread loop and another in
On Thu, Mar 10, 2022, Chao Peng wrote:
> @@ -3890,7 +3893,59 @@ static bool kvm_arch_setup_async_pf(struct kvm_vcpu
> *vcpu, gpa_t cr2_or_gpa,
> kvm_vcpu_gfn_to_hva(vcpu, gfn), );
> }
>
> -static bool kvm_faultin_pfn(struct kvm_vcpu *vcpu, struct kvm_page_fault
On Mon, Mar 28, 2022, Nakajima, Jun wrote:
> > On Mar 28, 2022, at 1:16 PM, Andy Lutomirski wrote:
> >
> > On Thu, Mar 10, 2022 at 6:09 AM Chao Peng
> > wrote:
> >>
> >> This is the v5 of this series which tries to implement the fd-based KVM
> >> guest private memory. The patches are based on
On Thu, Mar 10, 2022, Chao Peng wrote:
> @@ -2217,4 +2220,34 @@ static inline void kvm_handle_signal_exit(struct
> kvm_vcpu *vcpu)
> /* Max number of entries allowed for each kvm dirty ring */
> #define KVM_DIRTY_RING_MAX_ENTRIES 65536
>
> +#ifdef CONFIG_MEMFILE_NOTIFIER
> +static inline
On 28/3/22 22:49, Andreas K. Hüttel wrote:
With the command line flag -mplt and a recent toolchain, ELF binaries
generated by gcc can obtain EI_ABIVERSION=1, which makes, e.g., gcc
three-stage bootstrap in a mips-unknown-linux-gnu qemu-user chroot
fail since the binfmt-misc magic does not match
On 3/28/22 06:57, Xiaojuan Yang wrote:
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
softmmu/qdev-monitor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 3/28/22 06:57, Xiaojuan Yang wrote:
+static struct DeviceState *ipi, *extioi;
Static variables can't be right.
These need to be somewhere else, or ...
@@ -107,12 +115,101 @@ static void loongarch_cpu_init(LoongArchCPU *la_cpu, int
cpu_num)
NULL, "iocsr_misc",
On 3/28/22 06:57, Xiaojuan Yang wrote:
+void helper_tlbflush(CPULoongArchState *env)
+{
+int i, index;
+
+index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
+
+if (index < LOONGARCH_STLB) {
+/* STLB. One line per operation */
+for (i = 0; i < 8; i++) {
+
On 3/28/22 06:57, Xiaojuan Yang wrote:
+static uint64_t extioi_ipmap_enable_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+uint8_t ret;
+
+switch (addr) {
+case EXTIOI_IPMAP_START ...
> On Mar 28, 2022, at 1:16 PM, Andy Lutomirski wrote:
>
> On Thu, Mar 10, 2022 at 6:09 AM Chao Peng wrote:
>>
>> This is the v5 of this series which tries to implement the fd-based KVM
>> guest private memory. The patches are based on latest kvm/queue branch
>> commit:
>>
>> d5089416b7fb
On 1/2/22 11:09, David Hildenbrand wrote:
memory_region_readd_subregion() wants to readd a region by first
removing it and then readding it. For readding, it doesn't use one of
the memory_region_add_*() variants, which is why fail to re-increment the
mr->mapped_via_alias counters, resulting in
On 3/28/22 06:57, Xiaojuan Yang wrote:
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 408 +
hw/intc/meson.build
On 28/3/22 05:59, WANG Xuerui wrote:
This bug is probably lurking there for so long, I cannot even git-blame
my way to the commit first introducing it.
Anyway, because n32 is also TARGET_MIPS64, the address space range
cannot be determined by looking at TARGET_MIPS64 alone. Fix this by only
From: Akihiko Odaki
Without this change, The GL output of a console overwrites the
other consoles and makes them unusable.
Signed-off-by: Akihiko Odaki
Reviewed-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220325161216.74582-1-akihiko.od...@gmail.com>
From: Philippe Mathieu-Daudé
The following changes since commit 27fc9f365d6f60ff86c2e2be57289bb47a2be882:
Merge tag 'pull-ppc-20220326' of https://github.com/legoater/qemu into
staging (2022-03-28 10:16:33 +0100)
are available in the Git repository at:
https://github.com/philmd/qemu.git
From: Philippe Mathieu-Daudé
Since commit 0439c5a462 ("block/block-backend.c: assertions for
block-backend") QEMU crashes when using Cocoa on Darwin hosts.
Example on macOS:
$ qemu-system-i386
Assertion failed: (qemu_in_main_thread()), function blk_all_next, file
block-backend.c, line
From: Akihiko Odaki
Signed-off-by: Akihiko Odaki
Fixes: 4797adce5f ("ui/cocoa: add option to swap Option and Command")
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220317152949.68666-1-akihiko.od...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
ui/cocoa.m | 3 ++-
1 file
From: Philippe Mathieu-Daudé
Apple's Git distribution actually carries a similar file which
annotates *.m:
https://github.com/apple-opensource/Git/blob/73/gitattributes
See comments in commit 29cf16db23 ("buildsys: Help git-diff
adding .gitattributes config file") for details.
Signed-off-by:
On 28/3/22 17:20, Stefano Garzarella wrote:
Replace vpda with vdpa.
Signed-off-by: Stefano Garzarella
---
hw/virtio/vhost-vdpa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 28/3/22 16:02, Paolo Bonzini wrote:
Just check the target name instead.
Signed-off-by: Paolo Bonzini
---
tests/tcg/Makefile.target | 8
tests/tcg/configure.sh| 12 +++-
2 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/tests/tcg/configure.sh
On 28/3/22 16:02, Paolo Bonzini wrote:
Just check the target name instead.
Signed-off-by: Paolo Bonzini
---
tests/tcg/configure.sh | 2 --
tests/tcg/multiarch/Makefile.target | 2 +-
tests/tcg/x86_64/Makefile.target| 2 +-
3 files changed, 2 insertions(+), 4 deletions(-)
On 28/3/22 16:02, Paolo Bonzini wrote:
No need to go through the shell when we already have the test and images at
the point where the targets are declared.
Signed-off-by: Paolo Bonzini
---
tests/docker/Makefile.include | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
On Thu, Mar 10, 2022, Chao Peng wrote:
> This new KVM exit allows userspace to handle memory-related errors. It
> indicates an error happens in KVM at guest memory range [gpa, gpa+size).
> The flags includes additional information for userspace to handle the
> error. Currently bit 0 is defined as
On 25/3/22 17:12, Akihiko Odaki wrote:
Without this change, The GL output of a console overwrites the
other consoles and makes them unusable.
Signed-off-by: Akihiko Odaki
Reviewed-by: Marc-André Lureau
---
ui/console.c | 21 +
1 file changed, 21 insertions(+)
Thanks,
On 17/3/22 14:03, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
See comments in commit 29cf16db23 ("buildsys: Help git-diff
adding .gitattributes config file") for details.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitattributes | 1 +
1 file changed, 1 insertion(+)
Not a
On 25/3/22 19:37, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Since commit 0439c5a462 ("block/block-backend.c: assertions for
block-backend") QEMU crashes when using Cocoa on Darwin hosts.
Example on macOS:
$ qemu-system-i386
Assertion failed: (qemu_in_main_thread()),
On 17/3/22 16:29, Akihiko Odaki wrote:
Signed-off-by: Akihiko Odaki
---
ui/cocoa.m | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Thanks, queued to darwin-fixes.
On Thu, Mar 10, 2022, Chao Peng wrote:
> @@ -4476,14 +4477,23 @@ static long kvm_vm_ioctl(struct file *filp,
> break;
> }
> case KVM_SET_USER_MEMORY_REGION: {
> - struct kvm_userspace_memory_region kvm_userspace_mem;
> + struct
On 3/28/22 06:57, Xiaojuan Yang wrote:
+typedef struct LoongArchIPI {
+SysBusDevice parent_obj;
+IPICore core[MAX_IPI_CORE_NUM];
+MemoryRegion ipi_mmio[MAX_IPI_CORE_NUM];
+} LoongArchIPI;
Why does this have an array of cores?
Surely the IPI device itself should not have this, but
On 23/3/22 12:45, Daniel P. Berrangé wrote:
The config key names were all wrong,
Since commit 2b678923bb@repo-lockdown (22 Aug 2020, 2 years ago...):
feat: move to GitHub Actions
BREAKING CHANGE: The deployment method and configuration
options have changed.
On 3/28/22 06:57, Xiaojuan Yang wrote:
+static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+IPICore *s = opaque;
+int index = 0;
+
+addr &= 0xff;
+trace_loongarch_ipi_write(size, (uint64_t)addr, val);
+
On 25/3/22 17:12, Akihiko Odaki wrote:
Without this change, The GL output of a console overwrites the
other consoles and makes them unusable.
Signed-off-by: Akihiko Odaki
Reviewed-by: Marc-André Lureau
---
ui/console.c | 21 +
1 file changed, 21 insertions(+)
On 25/3/22 19:23, Max Filippov wrote:
Don't disable all big-endian tests, instead check whether $(CORE) is
supported by the configured $(QEMU) and enable tests if it is.
Signed-off-by: Max Filippov
---
MAINTAINERS| 1 +
On Thu, Mar 10, 2022, Chao Peng wrote:
> Extend the memslot definition to provide fd-based private memory support
> by adding two new fields (private_fd/private_offset). The memslot then
> can maintain memory for both shared pages and private pages in a single
> memslot. Shared pages are provided
On 3/25/22 19:33, Fabiano Rosas wrote:
Before:
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
On Thu, Mar 10, 2022, Chao Peng wrote:
> Extend the memslot definition to provide fd-based private memory support
> by adding two new fields (private_fd/private_offset). The memslot then
> can maintain memory for both shared pages and private pages in a single
> memslot. Shared pages are provided
The command "query-init-properties" is needed to get values of properties
after initialization (not only default value). It makes sense, for example,
when working with x86_64-cpu.
All machine types (and x-remote-object, because its init uses machime
type's infrastructure) should be skipped,
This script makes the information that can be obtained from
query-init-properties and query-machines easy to read.
Note: some init values from the devices can't be available like properties
from virtio-9p when configure has --disable-virtfs. Such values are
replaced by "DEFAULT". Another
Fixes some possible issues with finalization. For example, finalization
immediately after instance_init fails on the assert.
Signed-off-by: Maxim Davydov
---
net/colo-compare.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/net/colo-compare.c
Attempt to finalize msmouse after initalization brings to segmentation
fault in QTAILQ_REMOVE.
Signed-off-by: Maxim Davydov
---
chardev/msmouse.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/chardev/msmouse.c b/chardev/msmouse.c
index eb9231dcdb..2cc1b16561 100644
---
Attempt to finalize msmouse after initalization brings to segmentation
fault in QTAILQ_REMOVE.
Signed-off-by: Maxim Davydov
---
chardev/wctablet.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/chardev/wctablet.c b/chardev/wctablet.c
index e8b292c43c..43bdf6b608 100644
Attempt to get address after initialization shouldn't fail on assert in
the qapi automatically generated code. As a possible solution, it can
return null type.
Signed-off-by: Maxim Davydov
---
chardev/char-socket.c | 9 +
1 file changed, 9 insertions(+)
diff --git
This patch adds the ability to get all the compat_props of the
corresponding supported machines for their comparison.
Example:
{ "execute" : "query-machines", "arguments" : { "is-full" : true } }
Signed-off-by: Maxim Davydov
---
hw/core/machine-qmp-cmds.c | 25 +++-
Call pci_bus_get_w64_range can fail with the segmentation fault. For
example, this can happen during attempt to get pci-hole64-end immediately
after initialization.
Signed-off-by: Maxim Davydov
---
hw/pci-host/i440fx.c | 17 +++--
hw/pci-host/q35.c| 17 +++--
2 files
Attempt to get memory region if the device doesn't have hostmem may not be
an error. This can be happen immediately after initialization (getting
value without default one).
Signed-off-by: Maxim Davydov
---
hw/i386/sgx-epc.c | 5 -
hw/mem/nvdimm.c | 6 ++
hw/mem/pc-dimm.c | 5 +
We need to be able to check machine type after its definition. It's
necessary when using complicated inheritance of compatible features. For
instance, this tool can help to find bugs in the machine type definition
if the name of the device has been changed. Also, this tool was created
to help with
On 28/03/2022 21:49, Richard Henderson wrote:
On 3/28/22 06:57, Xiaojuan Yang wrote:
+static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
+{
+ uint64_t feature = 0UL;
+
+ switch (addr) {
+ case FEATURE_REG:
+ feature |= 1UL << IOCSRF_MSI | 1UL <<
On 3/28/22 06:57, Xiaojuan Yang wrote:
+#define N_IRQS 14
There are only 13 irqs, according to ESTAT.
r~
On 3/28/22 06:57, Xiaojuan Yang wrote:
+static void loongarch_cpu_set_irq(void *opaque, int irq, int level)
+{
+LoongArchCPU *cpu = opaque;
+CPULoongArchState *env = >env;
+CPUState *cs = CPU(cpu);
+
+if (irq < 0 || irq > N_IRQS) {
+return;
+}
+
+if (level) {
+
On 3/28/22 06:57, Xiaojuan Yang wrote:
+static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
+{
+uint64_t feature = 0UL;
+
+switch (addr) {
+case FEATURE_REG:
+feature |= 1UL << IOCSRF_MSI | 1UL << IOCSRF_EXTIOI |
+ 1UL <<
With the command line flag -mplt and a recent toolchain, ELF binaries
generated by gcc can obtain EI_ABIVERSION=1, which makes, e.g., gcc
three-stage bootstrap in a mips-unknown-linux-gnu qemu-user chroot
fail since the binfmt-misc magic does not match anymore. Also other
values are technically
On 28/03/2022 13:57, Xiaojuan Yang wrote:
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 75 +
hw/intc/meson.build
On 3/28/22 06:57, Xiaojuan Yang wrote:
1.This patch Add loongarch interrupt and exception handle.
2.Rename the user excp to the exccode from the csr defintions.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
linux-user/loongarch64/cpu_loop.c | 8 +-
On 3/28/22 06:57, Xiaojuan Yang wrote:
+int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+CPULoongArchState *env = >env;
+target_ulong tmp = ldtul_p(mem_buf);
+
+if (0 <= n && n < 32) {
+return
On Thu, Mar 10, 2022 at 6:09 AM Chao Peng wrote:
>
> This is the v5 of this series which tries to implement the fd-based KVM
> guest private memory. The patches are based on latest kvm/queue branch
> commit:
>
> d5089416b7fb KVM: x86: Introduce KVM_CAP_DISABLE_QUIRKS2
Can this series be run
On 3/28/22 06:57, Xiaojuan Yang wrote:
+#ifndef CONFIG_USER_ONLY
+static bool gen_rdtime(DisasContext *ctx, arg_rr *a,
+ bool word, bool high)
+{
+TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
+TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
+
+if
On 28/03/2022 13:57, Xiaojuan Yang wrote:
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
MAINTAINERS | 2 +
hw/intc/Kconfig | 3 +
hw/intc/loongarch_ipi.c | 164
On 3/28/22 06:57, Xiaojuan Yang wrote:
+void helper_idle(CPULoongArchState *env)
+{
+CPUState *cs = env_cpu(env);
+
+cs->halted = 1;
+cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
+do_raise_exception(env, EXCP_HLT, 0);
+}
Why are you messing with CPU_INTERRUPT_WAKE?
You only
On 28/03/2022 13:57, Xiaojuan Yang wrote:
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 408 +
hw/intc/meson.build
From: Matheus Ferst
Implements parts_float_to_int2 based on parts_float_to_int logic. The
new methods return the lower part of the result through the "lo"
pointer.
Signed-off-by: Matheus Ferst
---
fpu/softfloat-parts.c.inc | 75 +++
fpu/softfloat.c
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
xscvqpsqz: VSX Scalar Convert with round to zero Quad-Precision to
Signed Quadword
xscvqpuqz: VSX Scalar Convert with round to zero Quad-Precision to
Unsigned Quadword
Signed-off-by: Matheus Ferst
---
From: Matheus Ferst
Based on parts_uint_to_float, implements parts_uint_to_float2 that
receives a 128-bit integer through a pair of uint64_t values.
Signed-off-by: Matheus Ferst
---
fpu/softfloat-parts.c.inc | 19 +++
fpu/softfloat.c | 30
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
xscvsqqp: VSX Scalar Convert with round Signed Quadword to
Quad-Precision
xscvuqqp: VSX Scalar Convert with round Unsigned Quadword to
Quad-Precision format
Signed-off-by: Matheus Ferst
---
On 28/03/2022 13:57, Xiaojuan Yang wrote:
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 488
hw/intc/meson.build
From: Matheus Ferst
This RFC is a first attempt at implementing the 128-bit integer
conversion routines in softfloat, as required by the xscv[su]qqp and
xscvqp[su]qz instructions of PowerISA v3.1.
Instead of using int128.h, int-to-float routines receive the 128-bit
numbers through a pair of
From: Matheus Ferst
Based on parts_sint_to_float, implements parts_sint_to_float2 that
receives a 128-bit signed integer via int64_t and uint64_t arguments.
Signed-off-by: Matheus Ferst
---
fpu/softfloat-parts.c.inc | 37 +
fpu/softfloat.c | 30
From: Matheus Ferst
Implements parts_float_to_uint2 based on parts_float_to_uint logic. The
new methods return the lower part of the result through the "lo"
pointer.
Signed-off-by: Matheus Ferst
---
fpu/softfloat-parts.c.inc | 71 +++
fpu/softfloat.c
On 3/28/22 06:57, Xiaojuan Yang wrote:
+static void output_empty(DisasContext *ctx, arg_empty *a,
+ const char *mnemonic)
+{
+}
No, you must still do
output(ctx, mnemonic, "");
+static bool trans_tlbwr(DisasContext *ctx, arg_tlbwr *a)
+{
+if (check_plv(ctx))
On Sat, 26 Mar 2022 14:02:21 +0800
"Longpeng(Mike)" wrote:
> From: Longpeng
>
> Hi guys,
>
> In vfio migration resume phase, the cost would increase if the
> vfio device has more unmasked vectors. We try to optimize it in
> this series.
>
> You can see the commit message in PATCH 6 for
On Wed, 23 Mar 2022 21:31:19 +0100
Eric Auger wrote:
> The CRB command buffer currently is a RAM MemoryRegion and given
> its base address alignment, it causes an error report on
> vfio_listener_region_add(). This region could have been a RAM device
> region, easing the detection of such safe
On 3/28/22 06:57, Xiaojuan Yang wrote:
+bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+MMUAccessType access_type, int mmu_idx,
+bool probe, uintptr_t retaddr)
+{
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+
On 3/28/22 06:57, Xiaojuan Yang wrote:
+void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
+ uint64_t value)
+{
+CPULoongArchState *env = >env;
+uint64_t now, next;
+
+env->CSR_TCFG = value;
+if (value &
On 3/28/22 06:57, Xiaojuan Yang wrote:
+++ b/target/loongarch/cpu.h
@@ -11,6 +11,7 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "hw/registerfields.h"
+#include "cpu-csr.h"
Do you need this include here?
I would hope that there would be only a few extra files
On Mon, Mar 28, 2022, Quentin Perret wrote:
> Hi Sean,
>
> Thanks for the reply, this helps a lot.
>
> On Monday 28 Mar 2022 at 17:13:10 (+), Sean Christopherson wrote:
> > On Thu, Mar 24, 2022, Quentin Perret wrote:
> > > For Protected KVM (and I suspect most other confidential computing
>
On 3/28/22 06:57, Xiaojuan Yang wrote:
+uint64_t helper_iocsr_read(CPULoongArchState *env, target_ulong r_addr,
+ uint32_t size)
+{
+int cpuid = env_cpu(env)->cpu_index;
+CPUState *cs = qemu_get_cpu(cpuid);
+env = cs->env_ptr;
+uint64_t ret;
+
+/*
+
On 26/2/22 12:59, Akihiko Odaki wrote:
Otherwise, the audio subsystem tries to use the voice and
eventually aborts due to the maximum number of samples in the
buffer is not set.
Signed-off-by: Akihiko Odaki
Reviewed-by: Christian Schoenebeck
---
audio/coreaudio.c | 2 ++
1 file changed, 2
On 3/28/22 06:57, Xiaojuan Yang wrote:
+#define CSR_OFF(X) \
+ [LOONGARCH_CSR_##X] = offsetof(CPULoongArchState, CSR_##X)
+#define CSR_OFF_ARRAY(X, N) \
+ [LOONGARCH_CSR_##X(N)] = offsetof(CPULoongArchState, CSR_##X[N])
+
+static const int csr_offsets[] = {
You cannot put
On 3/28/22 06:57, Xiaojuan Yang wrote:
This series patch add softmmu support for LoongArch.
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
The latest uefi:
* https://github.com/loongson/edk2
* https://github.com/loongson/edk2-platforms
The manual:
*
On 3/28/22 11:31, Idan Horowitz wrote:
While not mentioned anywhere in the actual specification text, the
HCR_EL2.ATA bit is treated as '1' when EL2 is disabled at the current
security state. This can be observed in the psuedo-code implementation
of AArch64.AllocationTagAccessIsEnabled().
Hi Sean,
Thanks for the reply, this helps a lot.
On Monday 28 Mar 2022 at 17:13:10 (+), Sean Christopherson wrote:
> On Thu, Mar 24, 2022, Quentin Perret wrote:
> > For Protected KVM (and I suspect most other confidential computing
> > solutions), guests have the ability to share some of
On Mon, 21 Mar 2022 10:14:57 +0100
Michal Prívozník wrote:
> On 3/20/22 22:38, Andrew Deason wrote:
> > The code for guest-network-get-interfaces needs a couple of small
> > adjustments for Solaris:
> >
> > - The results from SIOCGIFHWADDR are documented as being in ifr_addr,
> > not
While not mentioned anywhere in the actual specification text, the
HCR_EL2.ATA bit is treated as '1' when EL2 is disabled at the current
security state. This can be observed in the psuedo-code implementation
of AArch64.AllocationTagAccessIsEnabled().
Signed-off-by: Idan Horowitz
---
On 3/28/22 18:44, Alex Bennée wrote:
Paolo Bonzini writes:
Signed-off-by: Paolo Bonzini
---
tests/docker/Makefile.include | 18 --
1 file changed, 18 deletions(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index a6a5a20949..8248cfdb4f
On 3/28/22 18:18, Alex Bennée wrote:
debian-powerpc-user-cross was the only linux-user powered cross builder
and it was removed in commit 80394ccf21 ("tests/docker: remove
debian-powerpc-user-cross", 2019-09-26). Remove all the infrastructure
around it since it is now unused.
It doesn't
On 3/28/22 17:53, Richard Henderson wrote:
This is also a first step towards moving the cross-compilation
infrastructure from tests/tcg to all of QEMU, so that it can be
used to build firmware binaries.
Yay!
However, the tricore special cases broke:
Silly pasto:
diff --git
Accesses to henvcfg, henvcfgh and senvcfg are allowed
only if corresponding bit in mstateen0/hstateen0 is
enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 82 ++
1 file changed, 76
If smstateen is implemented then accesses to AIA
registers CSRS, IMSIC CSRs and other IMSIC registers
is controlled by setting of corresponding bits in
mstateen/hstateen registers. Otherwise an illegal
instruction trap or virtual instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
---
If smstateen is implemented and sstateen0.fcsr is clear
then the floating point operations must return illegal
instruction exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/riscv/csr.c
1 - 100 of 275 matches
Mail list logo
