The machine name already contains the words "ccw" and "virtio", so
using "VirtIO-ccw" in the description likely does not really help
the average user to get an idea what this machine type is about.
Thus let's switch to "Virtual s390x machine" now, since "virtual
machine" should be a familiar term,
> -Original Message-
> From: Christian Schoenebeck
> Sent: 2022年5月5日 19:44
> To: qemu-devel@nongnu.org; Shi, Guohuai ; Greg Kurz
>
> Cc: Meng, Bin ; Bin Meng
> Subject: Re: [PATCH 5/9] hw/9pfs: Add a 'local' file system backend driver for
> Windows
>
> [Please note: This e-mail is fro
From: Klaus Jensen
Pass the right constant to nvme_smart_event(). The NVME_AER* values hold
the bit position in the SMART byte, not the shifted value that we expect
it to be in nvme_smart_event().
Fixes: c62720f137df ("hw/block/nvme: trigger async event during injecting smart
warning")
Signed-o
Have you considered extending the emulation to include a AST1030 SoC
in a larger machine ?
The AST1030 SoC is merged and I think that QEMU could run a cortex-m4
CPU and a A7 CPU. A + R CPUs is supported (Xilinx boards).
As a matter of fact yes! I tested booting our OpenBIC Zephyr kernel las
On 5/4/22 18:34, Peter Delevoryas wrote:
On May 4, 2022, at 12:39 AM, Cédric Le Goater wrote:
On 5/4/22 00:59, Peter Delevoryas wrote:
Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace
i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB.
Referen
On 5/6/22 05:15, Jamin Lin wrote:
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/system/arm/aspeed.rst | 61 ++
1 file changed, 61 insertions(+)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index
The alternative small firmware needs a few words of what it can and
absolutely cannot do; this adds those words.
Signed-off-by: Alexey Kardashevskiy
---
docs/system/ppc/pseries.rst | 28
1 file changed, 28 insertions(+)
diff --git a/docs/system/ppc/pseries.rst b/doc
Jag Raman writes:
>> On May 5, 2022, at 10:42 AM, Markus Armbruster wrote:
>>
>> Jag Raman writes:
>>
On May 5, 2022, at 3:44 AM, Markus Armbruster wrote:
Jag Raman writes:
>> On May 4, 2022, at 7:42 AM, Markus Armbruster wrote:
>>
>> Jagannathan Raman w
On 05/05/2022 21.36, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This way there is at least some contact point for incoming patches.
We'll see whether the code still gets just a random patch a few times
a year or whether it requires a permanent maintainer to take care of it.
Signed
On 06/05/2022 01.32, Brad Smith wrote:
tests/vm/openbsd: Update to release 7.1
Signed-off-by: Brad Smith
---
tests/vm/openbsd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/vm/openbsd b/tests/vm/openbsd
index 337fe7c303..dc34b2718b 100755
--- a/tests/vm/openbsd
From: eopXD
Vector whole register load instructions have EEW encoded in the opcode,
so we shouldn't take SEW here. Vector whole register store instructions
are always EEW=8.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 58 +
vhost_net_start() missed a corresponding stop_one() upon error from
vhost_set_vring_enable(). While at it, make the error handling for
err_start more robust. No real issue was found due to this though.
Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
---
hw/net/vhost_net.c | 4 +++-
1 file change
When the control virtqueue feature is absent or not negotiated,
vhost_net_start() still tries to set up vhost_dev and install
vhost notifiers for the control virtqueue, which results in
erroneous ioctl calls with incorrect queue index sending down
to driver. Do that only when needed.
Fixes: 22288f
virtio_queue_host_notifier_read() tends to read pending event
left behind on ioeventfd in the vhost_net_stop() path, and
attempts to handle outstanding kicks from userspace vq handler.
However, in the ctrl_vq handler, virtio_net_handle_mq() has a
recursive call into virtio_net_set_status(), which m
Hi,
This patch series attempt to fix a few issues in vhost-vdpa multiqueue
functionality.
Patch #1 and #2 are the formal submission for RFC patch in:
https://lore.kernel.org/qemu-devel/c3e931ee-1a1b-9c2f-2f59-cb4395c23...@oracle.com/
Patch #3 through #5 are obviously small bug fixes. Please fin
With MQ enabled vdpa device and non-MQ supporting guest e.g.
booting vdpa with mq=on over OVMF of single vqp, below assert
failure is seen:
../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion `idx >=
dev->vq_index && idx < dev->vq_index + dev->nvqs' failed.
0 0x7f8ce3ff3387 in
... such that no memory leaks on dangling net clients in case of
error.
Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 1e9fe47..df1e69e 100644
--- a/net/vhost-vd
The vhost_vdpa_one_time_request() branch in
vhost_vdpa_set_backend_cap() incorrectly sends down
ioctls on vhost_dev with non-zero index. This may
end up with multiple VHOST_SET_BACKEND_FEATURES
ioctl calls sent down on the vhost-vdpa fd that is
shared between all these vhost_dev's.
To fix it, send
On 06/05/2022 01:50, Fabiano Rosas wrote:
Alexey Kardashevskiy writes:
On 5/5/22 05:16, Fabiano Rosas wrote:
Alexey Kardashevskiy writes:
tl;dr: This allows Big Endian zImage booting via -kernel + x-vof=on.
QEMU loads the kernel at 0x40 by default which works most of
the time as Li
On Thu, May 5, 2022 at 10:38 PM Brad Smith wrote:
> The checksum can be found here...
>
> https://cdn.openbsd.org/pub/OpenBSD/7.1/amd64/SHA256
>
> SHA256 (install71.iso) =
> d3a7c5b9bf890bc404304a1c96f9ee72e1d9bbcf9cc849c1133bdb0d67843396
>
Indeed. Then they do match. :)
Warner
> On 5/5/2022 1
The checksum can be found here...
https://cdn.openbsd.org/pub/OpenBSD/7.1/amd64/SHA256
SHA256 (install71.iso) =
d3a7c5b9bf890bc404304a1c96f9ee72e1d9bbcf9cc849c1133bdb0d67843396
On 5/5/2022 10:45 PM, Warner Losh wrote:
On Thu, May 5, 2022 at 5:32 PM Brad Smith wrote:
tests/vm/openbsd:
Hello all,
thank you for the responses, I ran 3 runs per each commit using 5 iteration of
fio-nbd using
f9fc8932b11f3bcf2a2626f567cb6fdd36a33a94
f9fc8932b11f3bcf2a2626f567cb6fdd36a33a94 + Stefan's commit
d7482ffe9756919531307330fd1c6dbec66e8c32
using the regressed f9fc8932b11f3bcf2a2626f567cb6
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/lasi.c | 2 ++
hw/hppa/lasi.h | 2 ++
2 files changed, 4 insertions(+)
Reviewed-by: Richard Henderson
r~
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/lasi.c | 44 +-
hw/hppa/lasi.h | 58 ++
2 files changed, 59 insertions(+), 43 deletions(-)
create
On 5/4/22 04:25, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/hppa/lasi.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r!
On 5/5/22 13:49, Daniel Henrique Barboza wrote:
The following changes since commit e91b8994115d2f093e7556c9af2d051a26a98cfb:
Merge tag 'pull-target-arm-20220505' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-05-05
11:30:33 -0500)
are available in the Git
On Thu, May 5, 2022 at 4:24 PM Daniel P. Berrangé wrote:
>
> On Thu, May 05, 2022 at 07:36:51PM +1000, Alistair Francis wrote:
> > On Tue, May 3, 2022 at 5:57 PM Atish Patra wrote:
> > >
> > > On Tue, Apr 19, 2022 at 5:26 PM Atish Patra wrote:
> > > >
> > > > On Tue, Apr 19, 2022 at 9:51 AM Dani
Signed-off-by: Jamin Lin
---
docs/system/arm/aspeed.rst | 61 ++
1 file changed, 61 insertions(+)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 60ed94f187..6f2e4fb53d 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/as
- v1:
add minibmc section in aspeed document
Jamin Lin (1):
docs: add minibmc section in aspeed document
docs/system/arm/aspeed.rst | 61 ++
1 file changed, 61 insertions(+)
--
2.17.1
On Thu, May 5, 2022 at 5:32 PM Brad Smith wrote:
> tests/vm/openbsd: Update to release 7.1
>
> Signed-off-by: Brad Smith
>
Reviewed-by: Warner Losh
Though i didn't verify the csum.
Warner
> ---
> tests/vm/openbsd | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a
Gently ping
On 4/27/22 9:12 AM, liuyd.f...@fujitsu.com wrote:
> [+cc qemu-trivial]
>
> On 4/14/22 8:19 PM, Vivek Goyal wrote:
>> On Wed, Apr 13, 2022 at 12:20:54PM +0800, Liu Yiding wrote:
>>> Refer to 26ec190964 virtiofsd: Do not use a thread pool by default
>>>
>>> Signed-off-by: Liu Yiding
>>
When CONFIG_MOS6522 is not set, building ppc64-softmmu target fails:
/usr/bin/ld: libqemu-ppc64-softmmu.fa.p/monitor_misc.c.o:(.data+0x1158):
undefined reference to `hmp_info_via'
Make devices configuration available in hmp-commands*.hx and check for
CONFIG_MOS6522.
Fixes: 409e9f7131e5 (mos
tests/vm/openbsd: Update to release 7.1
Signed-off-by: Brad Smith
---
tests/vm/openbsd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/vm/openbsd b/tests/vm/openbsd
index 337fe7c303..dc34b2718b 100755
--- a/tests/vm/openbsd
+++ b/tests/vm/openbsd
@@ -22,8 +22,8 @@ c
On Thu, May 5, 2022 at 1:35 PM Alistair Francis wrote:
>
> On Thu, May 5, 2022 at 8:04 PM Daniel P. Berrangé wrote:
> >
> > On Thu, May 05, 2022 at 07:36:51PM +1000, Alistair Francis wrote:
> > > On Tue, May 3, 2022 at 5:57 PM Atish Patra wrote:
> > > >
> > > > On Tue, Apr 19, 2022 at 5:26 PM At
On 5/5/22 06:26, Paolo Bonzini wrote:
-machine graphics=off is the usual way to tell the firmware or the OS that the
user wants a serial console. The pseries machine however does not support
this, and never adds the stdout-path node to the device tree if a VGA device
is provided. This is in a
It only needs to update the scanouts containing the rect area
coming with the resource-flush request from the guest.
Cc: Gerd Hoffmann
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
hw/display/virtio-gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/display/virtio-gpu.c b/hw/
On Thu, May 5, 2022 at 2:37 AM Alistair Francis wrote:
>
> On Tue, May 3, 2022 at 5:57 PM Atish Patra wrote:
> >
> > On Tue, Apr 19, 2022 at 5:26 PM Atish Patra wrote:
> > >
> > > On Tue, Apr 19, 2022 at 9:51 AM Daniel P. Berrangé
> > > wrote:
> > > >
> > > > On Mon, Apr 11, 2022 at 07:10:06PM
On Thu, May 5, 2022 at 8:04 PM Daniel P. Berrangé wrote:
>
> On Thu, May 05, 2022 at 07:36:51PM +1000, Alistair Francis wrote:
> > On Tue, May 3, 2022 at 5:57 PM Atish Patra wrote:
> > >
> > > On Tue, Apr 19, 2022 at 5:26 PM Atish Patra wrote:
> > > >
> > > > On Tue, Apr 19, 2022 at 9:51 AM Dani
From: "Maciej S. Szmigiero"
This way there is at least some contact point for incoming patches.
We'll see whether the code still gets just a random patch a few times
a year or whether it requires a permanent maintainer to take care of it.
Signed-off-by: Maciej S. Szmigiero
---
Resending, s
From: Víctor Colombo
Today we have the issue where MSR_* values are the 'inverted order'
bit numbers from what the ISA specifies. e.g. MSR_LE is bit 63 but
is defined as 0 in QEMU.
Add a macro to be used to convert from QEMU order to ISA order.
This solution requires less changes than to use th
From: Víctor Colombo
msr_hv macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.115
From: Víctor Colombo
Add FIELDs macros for msr bits that had an unused msr_* before.
Signed-off-by: Víctor Colombo
Acked-by: Richard Henderson
Message-Id: <20220504210541.115256-22-victor.colo...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu.h | 25 ++
From: Víctor Colombo
msr_ir macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
From: Víctor Colombo
msr_ts macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.115
From: Víctor Colombo
msr_ce macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
From: Víctor Colombo
msr_fe0 and msr_fe1 macros hide the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220
From: Víctor Colombo
msr_de macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.115
From: Víctor Colombo
msr_gs macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
From: Víctor Colombo
msr_cm macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
From: Víctor Colombo
msr_ep macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
From: Víctor Colombo
msr_me macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
From: Víctor Colombo
msr_ile macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.115
From: Víctor Colombo
msr_fp macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
This extension concerns cache speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm/
From: Víctor Colombo
msr_dr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
From: Víctor Colombo
msr_ee macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
From: Víctor Colombo
msr_pow macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.115
Check for and defer any pending virtual SError.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Retain m-profile check; improve comments.
---
target/arm/helper.h| 1 +
target/arm/a32.decode | 16 --
target/arm/t32.decode | 18
From: Víctor Colombo
msr_le macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
Enable the n1 for virt and sbsa board use.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 66
4 files changed,
From: Víctor Colombo
msr_pr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
From: Frederic Barrat
The Post Interrupt Priority Register (PIPR) is not restored like the
other OS-context related fields of the TIMA when pushing an OS context
on the CPU. It's not needed because it can be calculated from the
Interrupt Pending Buffer (IPB), which is saved and restored. The PIPR
Enable the a76 for virt and sbsa board use.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 66
4 files changed,
There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy access_scxtnu
From: Víctor Colombo
msr_ds macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220504210541.1152
This extension concerns not merging memory access, which TCG does
not implement. Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/syste
Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 37c5e42bc0.
This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
2 files
This extension concerns branch speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm
From: Víctor Colombo
Some msr_* macros are not used anywhere. Remove them as part of
the work to remove all hidden usage of *env.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
Message-Id: <20220504210541.115256-3-victor.colo...@eldorado.org.br>
S
Add only the system registers required to implement zero error
records. This means that all values for ERRSELR are out of range,
which means that it and all of the indexed error record registers
need not be implemented.
Add the EL2 registers required for injecting virtual SError.
Reviewed-by: Pe
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm/cpu_tcg.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/a
From: Víctor Colombo
fpscr_* defined macros are hiding the usage of *env behind them.
Substitute the usage of these macros with `env->fpscr & FP_*` to make
the code cleaner.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
Message-Id: <2022050421054
From: Murilo Opsfelder Araujo
The correct name of the macro is TARGET_PPC64.
Fixes: 27598393a232 ("Lift max memory slots limit imposed by vhost-user")
Reported-by: Fabiano Rosas
Signed-off-by: Murilo Opsfelder Araujo
Cc: Raphael Norwitz
Cc: Peter Turschmid
Reviewed-by: Daniel Henrique Barboz
From: Bin Meng
Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug
Event" and chapter 8.4.5 "Instruction Complete Debug Event":
"A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT]
are set ... Branch taken debug events are not recognized if MSR[DE]
is cleared
From: Frederic Barrat
When pulling or pushing an OS context from/to a CPU, we should
re-evaluate the state of the External interrupt signal. Otherwise, we
can end up catching the External interrupt exception in hypervisor
mode, which is unexpected.
The problem is best illustrated with the follow
This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU. Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.
Reviewed-by: Peter Maydell
Signed-off-by: Richard
Init 'sregs' to avoid Valgrind complaints about uninitialized bytes
from kvmppc_put_books_sregs():
==54059== Thread 3:
==54059== Syscall param ioctl(generic) points to uninitialised byte(s)
==54059==at 0x55864E4: ioctl (in /usr/lib64/libc.so.6)
==54059==by 0xD1FA23: kvm_vcpu_ioctl (kvm-all
Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 2 +
target/arm/cpu64.c | 50 +-
target/arm/cpu_tcg.c | 114 +++
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE. The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Hende
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Honor EAE for reporting VSERR to aa32.
---
target/arm/cpu.h | 2 ++
target/arm/internals.h | 8 +
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 55 ++---
1 file change
We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 4
1 file changed, 4 insertions(+)
diff -
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
in
Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Create impdef sysr
Init the struct to avoid Valgrind complaints about unitialized bytes,
such as this one:
==39549== Syscall param ioctl(generic) points to uninitialised byte(s)
==39549==at 0x55864E4: ioctl (in /usr/lib64/libc.so.6)
==39549==by 0xD1F7EF: kvm_vm_ioctl (kvm-all.c:3035)
==39549==by 0xAF8F5B
Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 100 +---
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo,
and the local vpidr_regs definition, and rely on the
squasing to ARM_CP_CONST while registering.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 158
1 file changed, 13 insertions(+), 14
'lpcr' is used as an input of kvm_get_one_reg(). Valgrind doesn't
understand that and it returns warnings as such for this function:
==55240== Thread 1:
==55240== Conditional jump or move depends on uninitialised value(s)
==55240==at 0xB011E4: kvmppc_enable_cap_large_decr (kvm.c:2546)
==55240=
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Rely on EL3-no-EL2 squashing during registration.
---
target/arm/helper.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/hel
The following changes since commit e91b8994115d2f093e7556c9af2d051a26a98cfb:
Merge tag 'pull-target-arm-20220505' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-05-05
11:30:33 -0500)
are available in the Git repository at:
https://gitlab.com/danielhb/qem
More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
either discard, squash to res0, const, or keep unchanged.
Per rule RJFFP, mark the 4 aarch32 hypervisor access re
Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.
This will shortly be used from cpu_tcg.c also.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: New patch.
---
target/arm/i
Implement the handling of FEAT_S2FWB; the meat of this is in the new
combined_attrs_fwb() function which combines S1 and S2 attributes
when HCR_EL2.FWB is set.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 5 +++
target/arm/helper.c | 84 +++--
2
Valgrind isn't convinced that we are initializing the values we assign
to env->spr[spr] because it doesn't understand that the 'val' union is
being written by the kvm_vcpu_ioctl() that follows (via struct
kvm_one_reg).
This results in Valgrind complaining about uninitialized values every
time we u
In the original Arm v8 two-stage translation, both stage 1 and stage
2 specify memory attributes (memory type, cacheability,
shareability); these are then combined to produce the overall memory
attributes for the whole stage 1+2 access. In QEMU we implement this
by having get_phys_addr() fill in a
In the original Arm v8 two-stage translation, both stage 1 and stage
2 specify memory attributes (memory type, cacheability,
shareability); these are then combined to produce the overall memory
attributes for the whole stage 1+2 access.
The new FEAT_S2FWB feature allows the guest to enable a diffe
Changes for v4:
* Rebase on master, where the second third is upstream.
* Add ARM_CP_EL3_NO_EL2_C_NZ flag, and use that in the
two cpregs called out by rule RJFFP that become constant
but not zero.
* Set SCTLR_EL1.TSCXT for user-only.
Patches lacking review:
01-target-arm-Handle-cp
Factor out the part of combine_cacheattrs() that is specific to
handling HCR_EL2.FWB == 0. This is the part where we combine the
memory type and cacheability attributes.
The "force Outer Shareable for Device or Normal Inner-NC Outer-NC"
logic remains in combine_cacheattrs() because it holds regar
Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that
CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the
inherited CLIDR_EL1 value from the Cortex-A57 has them as 1).
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c|
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