> On 2 Jun 2022, at 21:36, Liviu Ionescu wrote:
>
> ... SYS_HEAPINFO...
>
> 0x0400 - heap base
> 0x0800 - heap limit
> 0x0800 - stack base
> 0x0 - stack limit
For Cortex-A72 I see similar values:
0x4400
0x4800
0x4800
0x4000
just that in this case the memory is w
On 6/2/22 21:19, Klaus Jensen wrote:
On Jun 2 17:40, Cédric Le Goater wrote:
On 6/2/22 16:29, Jae Hyun Yoo wrote:
Hi Klaus,
On 6/2/2022 6:50 AM, Cédric Le Goater wrote:
On 6/2/22 10:21, Klaus Jensen wrote:
There is an outstanding issue with the SLAVE_ADDR_RX_MATCH interrupt bit
(bit 7). Re
On 03/06/2022 02.56, Richard Henderson wrote:
On 6/2/22 17:03, Richard Henderson wrote:
Ho hum. So... the first time I try to do any actual debugging after this
has gone in, and I am reminded exactly how terrible capstone 4.0.1 is for
anything except x86. There was a reason I had chosen a dev
On 6/2/22 17:03, Richard Henderson wrote:
Ho hum. So... the first time I try to do any actual debugging after this has gone in, and
I am reminded exactly how terrible capstone 4.0.1 is for anything except x86. There was a
reason I had chosen a development branch snapshot, and that's because it
On 5/23/22 05:15, Thomas Huth wrote:
On 19/05/2022 13.41, Peter Maydell wrote:
On Mon, 16 May 2022 at 16:22, Thomas Huth wrote:
Now that we allow compiling with Capstone v3.05 again, all our supported
build hosts should provide at least this version of the disassembler
library, so we do not n
The DEFINE_PROP* macros in pnv files are using extra spaces for no good
reason.
Cc: Mark Cave-Ayland
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb3.c | 8
hw/pci-host/pnv_phb4.c | 10 +-
hw/pci-host/pnv_phb4_pec.c | 10 +-
3 files changed, 14 i
Fold the return value setting into the goto, so each
point of failure need not do both.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch
Add "sve" to the sve prctl functions, to distinguish
them from the coming "sme" prctls with similar names.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_prctl.h | 8
linux-user/syscall.c | 12 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5cb9f9f02c..13b008547e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 590f2258b2..711fd19701 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -340,6 +340,
On Thu, 2 Jun 2022 15:31:38 -0600
Alex Williamson wrote:
> On Mon, 7 Feb 2022 17:20:02 +0100
> Thomas Huth wrote:
>
> > On 07/02/2022 16.50, Alex Williamson wrote:
> > > On Sat, 5 Feb 2022 10:49:35 +
> > > Peter Maydell wrote:
> > >
> > >> On Thu, 3 Feb 2022 at 22:38, Alex Williamso
These prctl set the Streaming SVE vector length, which may
be completely different from the Normal SVE vector length.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_prctl.h | 48 +++
linux-user/syscall.c | 16 +++
2 files changed,
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 20 +
target/arm/translate-sve.c | 57 ++
2 files changed, 77 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index bbdaac6ac7..bf561c270a 100644
--- a/targe
There's no reason to set CPACR_EL1.ZEN if SVE disabled.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 75295a14a3..5cb9f9f02c 100644
--- a/target/arm/cpu.c
+++ b/target/arm
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 20
1 file changed, 20 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index f7eae357f4..8135960305 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -601,6 +601,18 @@ enum {
Move the checks out of the parsing loop and into the
restore function. This more closely mirrors the code
structure in the kernel, and is slightly clearer.
Reject rather than silently skip incorrect VL and SVE record sizes.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 51
We can handle both exception entry and exception return by
hooking into aarch64_sve_change_el.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7396be4352.
Set the SM bit in the SVE record on signal delivery, create the ZA record.
Restore SM and ZA state according to the records present on return.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 158 ++--
1 file changed, 149 insertions(+), 9 deletio
In parse_user_sigframe, the kernel rejects duplicate sve records,
or records that are smaller than the header. We were silently
allowing these cases to pass, dropping the record.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 5 -
1 file changed, 4 insertions(+), 1 delet
Make sure to zero the currently reserved fields.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 30e89f67c8..08a9746ace 100644
--- a/linux-
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_cpu.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h
index 97a477bd3e..f90359faf2 100644
--- a/linux-user/aarch64/target_cpu.h
+++ b/linux-user
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 18 +++
target/arm/sve.decode | 5 ++
target/arm/translate-sve.c | 102 +
target/arm/vec_helper.c| 24 +
4 files changed, 149 insertions(+)
diff --git a/target/arm/helpe
Signed-off-by: Richard Henderson
---
linux-user/aarch64/cpu_loop.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 3b273f6299..4af6996d57 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
We cannot reuse the SVE functions for LD[1-4] and ST[1-4],
because those functions accept only a Zreg register number.
For SME, we want to pass a pointer into ZA storage.
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 82 +
target/arm/sme.decode | 9 +
target/arm/s
Add a TCGv_ptr base argument, which will be cpu_env for SVE.
We will reuse this for SME save and restore array insns.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 3 +++
target/arm/translate-sve.c | 48 --
2 files changed, 39 insertions(+
This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16.
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 16
target/arm/sme.decode | 10 +
target/arm/sme_helper.c| 82 ++
target/arm/translate-sme.c | 14 +++
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 2 ++
target/arm/sve.decode | 1 +
target/arm/sve_helper.c| 16
target/arm/translate-sve.c | 2 ++
4 files changed, 21 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 2 ++
target/arm/translate-a64.h | 1 +
target/arm/sme.decode | 4
target/arm/sme_helper.c| 25 +
target/arm/translate-a64.c | 15 +++
target/arm/translate-sme.c | 13 +++
Note that SME remains effectively disabled for user-only,
because we do not yet set CPACR_EL1.SMEN. This needs to
wait until the kernel ABI is implemented.
Signed-off-by: Richard Henderson
---
docs/system/arm/emulation.rst | 4
target/arm/cpu64.c| 11 +++
2 files chang
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 5 +++
target/arm/sme.decode | 9 +
target/arm/sme_helper.c| 67 ++
target/arm/translate-sme.c | 33 +++
4 files changed, 114 insertions(+)
diff --git a/target/arm
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 2 ++
target/arm/sme.decode | 1 +
target/arm/sme_helper.c| 74 ++
target/arm/translate-sme.c | 2 ++
4 files changed, 79 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/
This includes the build rules for the decoder, and the
new file for translation, but excludes any instructions.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 1 +
target/arm/sme.decode | 20
target/arm/translate-a64.c | 7 ++-
target/arm/transl
Rename from cpu_arm_{get,set}_sve_default_vec_len,
and take the pointer to default_vq from opaque.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
ind
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 2 ++
target/arm/sme.decode | 2 ++
target/arm/sme_helper.c| 52 ++
target/arm/translate-sme.c | 29 +
4 files changed, 85 insertions(+)
diff --git a/target/arm/he
We need SVL separate from VL for RDSVL at al, as well as
ZA storage loads and stores, which do not require PSTATE.SM.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 12
target/arm/translate.h | 1 +
target/arm/helper.c| 8 +++-
target/arm/transla
We can reuse the SVE functions for implementing moves to/from
horizontal tile slices, but we need new ones for moves to/from
vertical tile slices.
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 11
target/arm/helper-sve.h| 2 +
target/arm/translate-a64.h | 9 +++
Mirror the properties for SVE. The main difference is
that any arbitrary set of powers of 2 may be supported,
and not the stricter constraints that apply to SVE.
Include a property to control FEAT_SME_FA64, as failing
to restrict the runtime to the proper subset of insns
could be a major point fo
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 5 +++
target/arm/sme.decode | 11 +
target/arm/sme_helper.c| 90 ++
target/arm/translate-sme.c | 30 +
4 files changed, 136 insertions(+)
diff --git a/target/arm/helpe
This new behaviour is in the ARM pseudocode function
AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
the trap would be delivered is in AArch64 mode.
Given that ARMv9 drops support for AArch32 outside EL0,
the trap EL detection ought
Keep all of the error messages together. This does mean that
when setting many sve length properties we'll only generate
one error, but we only really need one.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --
We can reuse the SVE functions for LDR and STR, passing in the
base of the ZA vector and a zero offset.
Signed-off-by: Richard Henderson
---
target/arm/sme.decode | 7 +++
target/arm/translate-sme.c | 23 +++
2 files changed, 30 insertions(+)
diff --git a/target/ar
Rename from cpu_arm_{get,set}_sve_vq, and take the
ARMVQMap as the opaque parameter.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 0a2f4f317
When Streaming SVE mode is enabled, the size is taken from
SMCR_ELx instead of ZCR_ELx. The format is shared, but the
set of vector lengths is not. Further, Streaming SVE does
not require any particular length to be supported.
Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM
to the
Implement the streaming mode identification register, and the
two streaming priority registers. For QEMU, they are all RES0.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/target/arm/helper.c b/targ
Place this late in the resettable section of the structure,
to keep the most common element offsets from being > 64k.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8
target/arm/machine.c | 36
2 files changed, 44 insertions(+)
diff -
These SME instructions are nominally within the SVE decode space,
so we add them to sve.decode and translate-sve.c.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 1 +
target/arm/sve.decode | 5 -
target/arm/translate-a64.c | 15 +++
target/arm/translate
These cpregs control the streaming vector length and whether the
full a64 instruction set is allowed while in streaming mode.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 8 ++--
target/arm/helper.c | 41 +
2 files changed, 47 insertions
This cpreg is used to access two new bits of PSTATE
that are not visible via any other mechanism.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 6 ++
target/arm/helper.c | 13 +
2 files changed, 19 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
inde
We will need these functions in translate-sme.c.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 38 ++
target/arm/translate-sve.c | 36
2 files changed, 38 insertions(+), 36 deletions(-)
diff --git a/tar
This will be used for raising various traps for SME.
Signed-off-by: Richard Henderson
---
target/arm/syndrome.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index 0cb26dde7d..4792df0f0f 100644
--- a/target/arm/syndrome.h
+++ b/t
These are required to determine if various insns
are allowed to issue.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 4
target/arm/helper.c| 4
target/arm/translate-a64.c | 2 ++
4 files changed, 12 insertions(+)
diff --gi
Pull the three sve_vq_* values into a structure.
This will be reused for SME.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 29 ++---
target/arm/cpu64.c | 22 +++---
target/arm/helper.c | 2 +-
target/arm/kvm64.c | 2 +-
4 files changed, 2
This will be used for controlling access to SME cpregs.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h| 5 +
target/arm/translate-a64.c | 18 ++
2 files changed, 23 insertions(+)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index d9b678c2f1..d307
The ARM pseudocode function NVL uses this predicate now,
and I think it's a bit clearer. Simplify the pseudocode
condition by noting that IsInHost is always false for EL1.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 3 +--
1 file changed, 1 insertion(+
These functions are not used outside cpu64.c,
so make them static.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 3 ---
target/arm/cpu64.c | 4 ++--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3999152f1a..60f84ba033 100644
This register is allocated from the existing block of id registers,
so it is already RES0 for cpus that do not implement SME.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 25 +
target/arm/helper.c | 4 ++--
target/arm/kvm64.c | 9 +
3 files change
This is CheckSMEAccess, which is the basis for a set of
related tests for various SME cpregs and instructions.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 1 +
target/arm/helper.c| 52 ++
targe
Drop the aa32-only inline fallbacks,
and just use a couple of ifdefs.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 --
target/arm/internals.h | 3 +++
target/arm/cpu.c | 2 ++
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/ar
Move the data to vec_helper.c and the inline to vec_internal.h.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/vec_internal.h | 7 +++
target/arm/sve_helper.c | 29 -
target/arm/vec_helper.c | 26 ++
3 file
This register is part of SME, but isn't closely related to the
rest of the extension.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 +
target/arm/helper.c | 32
2 files changed, 33 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
in
We will need this over in sme_helper.c.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/vec_internal.h | 13 +
target/arm/vec_helper.c | 2 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/arm/vec_internal.h b/target/arm/vec_inte
Put the inline function near the array declaration.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/vec_internal.h | 8 +++-
target/arm/sve_helper.c | 9 -
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/target/arm/vec_internal.h b/target
This function is used only once, and will need modification
for Streaming SVE mode.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 11 ---
target/arm/helper.c| 30 +++---
2 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/target/ar
These two instructions are aliases of MSR (immediate).
Use the two helpers to properly implement svcr_write.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 +
target/arm/helper-sme.h| 21 +
target/arm/helper.h| 1 +
target/arm/helper.c| 6 +
Use the function instead of the array directly.
Because the function performs its own masking, via the uint8_t
parameter, we need to do nothing extra within the users: the bits
above the first 2 (_uh) or 4 (_uw) will be discarded by assignment
to the local bmask variables, and of course _uq uses t
This will be used for implementing FEAT_SME.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cb37787c35..f6d114aad7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4043,6 +4043,11 @@
Begin creation of sve_ldst_internal.h by moving the primitives
that access host and tlb memory.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/sve_ldst_internal.h | 127 +
target/arm/sve_helper.c| 107 +-
We don't need to constrain the value set in zcr_el[1],
because it will be done by sve_zcr_len_for_el.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d2bd74c2ed..0621944167 10064
This (newish) ARM pseudocode function is easier to work with
than open-coded tests for HCR_E2H etc. Use of the function
will be staged into the code base in parts.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 2 ++
target/arm/helper.c| 28 ++
This will be used for both Normal and Streaming SVE, and the value
does not necessarily come from ZCR_ELx. While we're at it, emphasize
the units in which the value is returned.
Patch produced by
git grep -l sve_zcr_len_for_el | \
xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g'
Instead of checking these bits in fp_exception_el and
also in sve_exception_el, document that we must compare
the results. The only place where we have not already
checked that FP EL is zero is in rebuild_hflags_a64.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 58 +++-
The bitmap need only hold 15 bits; bitmap is over-complicated.
We can simplify operations quite a bit with plain logical ops.
The introduction of SVE_VQ_POW2_MAP eliminates the need for
looping in order to search for powers of two. Simply perform
the logical ops and use count leading or trailing
This check is buried within arm_hcr_el2_eff(), but since we
have to have the explicit check for CPTR_EL2.TZ, we might as
well just check it once at the beginning of the block.
Once this is done, we can test HCR_EL2.{E2H,TGE} directly,
rather than going through arm_hcr_el2_eff().
Signed-off-by: Ri
Export all of the support functions for performing bulk
fault analysis on a set of elements at contiguous addresses
controlled by a predicate.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/sve_ldst_internal.h | 94 ++
target/arm/sve_h
With SME, the vector length does not only come from ZCR_ELx.
Comment that this is either NVL or SVL, like the pseudocode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Renamed from SVE_LEN to VL.
---
target/arm/cpu.h | 3 ++-
target/arm/translate-a64.h | 2 +-
ta
The ARM pseudocode function CheckNormalSVEEnabled uses this
predicate now, and I think it's a bit clearer.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 135c3e790c.
We handle this routing in raise_exception. Promoting the value early
means that we can't directly compare FPEXC_EL and SVEEXC_EL.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helpe
Implement FEAT_SME and most optional extensions, which are really
pretty trivial compared to the main feature. FEAT_EBF16 is still
on the to-do list.
Includes linux-user support, based on Mark Brown's code that has been
merged into linux 5.19-rc1.
Mark's kselftest suite is in fact all of the tes
Add an interface function to extract the digested vector length
rather than the raw zcr_el[1] value. This fixes an incorrect
return from do_prctl_set_vl where we didn't take into account
the set of vector lengths supported by the cpu.
Signed-off-by: Richard Henderson
---
v2: Add sve_vq_cached ra
Delay writing PIO output until io_buffer is filled or ATA command
completion, rather than when interrupts are generated. As an example
of the new behavior, issuing WRITE SECTOR(S) with a sector count of
256 will result in only a single call to blk_aio_pwritev rather than
after each of the 256 sect
Hello,
Is there any mechanism within QEMU for an emulated device to handle
string IO instructions (e.g., insw) directly?
I have noticed that PIO transfers seem rather slow (~240 kb/s) when
running QEMU on my computer, despite using a raw block device (SSD),
aio=io_uring, and file.cache.direct=on.
On Mon, 7 Feb 2022 17:20:02 +0100
Thomas Huth wrote:
> On 07/02/2022 16.50, Alex Williamson wrote:
> > On Sat, 5 Feb 2022 10:49:35 +
> > Peter Maydell wrote:
> >
> >> On Thu, 3 Feb 2022 at 22:38, Alex Williamson
> >> wrote:
> >>>
> >>> The following changes since commit
> >>> 8f3e5ce
On Saturday, May 28, 2022, Bernhard Beschow wrote:
> Am 13. Mai 2022 18:09:54 UTC schrieb Bernhard Beschow :
>>v2:
>>* Have pci_xen_ide_unplug() return void (Paul Durrant)
>>* CC Xen maintainers (Michael S. Tsirkin)
>>
>>v1:
>>This patch series first removes the redundant "piix3-ide-xen" device
cl
Ping
Am 29. Mai 2022 18:40:03 UTC schrieb Bernhard Beschow :
>v3:
>* "iobase" is now u16 (Philippe)
>
>v2:
>* Explicitly fail with &error_abort rather than NULL (Mark)
>* Explicitly fail with &error_abort rather than NULL in existing code (me)
>* Unexport rather than remove RTC_ISA_BASE (Mark)
>*
Am 30. Mai 2022 11:27:07 UTC schrieb "Philippe Mathieu-Daudé"
:
>From: Philippe Mathieu-Daudé
>
>This series moves the outstanding logic from piix4_pm_init() into
>the relevant instance init() and realize() functions, changes the
>IRQs to use qdev gpios, and then finally removes the now-unused
>p
On 6/2/22 13:16, Frederic Barrat wrote:
On 31/05/2022 23:49, Daniel Henrique Barboza wrote:
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and i
One method to enable PCI bus mastering for IDE controllers, often used
by x86 firmware, is to write 0x7 to the PCI command register. Neither
the PIIX3 specification nor actual hardware (a Tyan S1686D system)
permit modification of the Memory Space Enable (MSE) bit, 1, and thus
the command register
On 6/2/22 04:18, Mark Cave-Ayland wrote:
On 31/05/2022 22:49, Daniel Henrique Barboza wrote:
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and i
On 02/06/2022 16:10, Daniel Henrique Barboza wrote:
Commit c29018cc7395 added an env->fpscr OR operation using a ternary
that checks if 'error' is not zero:
env->fpscr |= error ? FP_FEX : 0;
However, in the current body of do_fpscr_check_status(), 'error' is
granted to be always non-zero
On Thu, Jun 02, 2022 at 09:08:52PM +0200, Geert Uytterhoeven wrote:
> Hi Joel,
>
> On Thu, Jun 2, 2022 at 1:42 PM Joel Stanley wrote:
> > On Fri, 27 May 2022 at 17:27, Stafford Horne wrote:
> > > This patch add the OpenRISC virtual machine 'virt' for OpenRISC. This
> > > platform allows for a c
On Thu, 2 Jun 2022 at 11:28, Sam Li wrote:
>
> Stefan Hajnoczi 于2022年6月2日周四 16:05写道：
> >
> > On Thu, 2 Jun 2022 at 06:43, Sam Li wrote:
> > >
> > > Hi Stefan,
> > >
> > > Stefan Hajnoczi 于2022年6月1日周三 19:43写道：
> > > >
> > > > On Wed, 1 Jun 2022 at 06:47, Damien Le Moal
> > > > wrote:
> > > > >
On Jun 2 17:40, Cédric Le Goater wrote:
> On 6/2/22 16:29, Jae Hyun Yoo wrote:
> > Hi Klaus,
> >
> > On 6/2/2022 6:50 AM, Cédric Le Goater wrote:
> > > On 6/2/22 10:21, Klaus Jensen wrote:
> > > >
> > > > There is an outstanding issue with the SLAVE_ADDR_RX_MATCH interrupt bit
> > > > (bit 7). R
Commit c29018cc7395 added an env->fpscr OR operation using a ternary
that checks if 'error' is not zero:
env->fpscr |= error ? FP_FEX : 0;
However, in the current body of do_fpscr_check_status(), 'error' is
granted to be always non-zero at that point. The result is that Coverity
is less than
Hi Joel,
On Thu, Jun 2, 2022 at 1:42 PM Joel Stanley wrote:
> On Fri, 27 May 2022 at 17:27, Stafford Horne wrote:
> > This patch add the OpenRISC virtual machine 'virt' for OpenRISC. This
> > platform allows for a convenient CI platform for toolchain, software
> > ports and the OpenRISC linux k
I'm experiencing some issues with the startup code for an emulated Cortex-a15
machine I plan to use for running unit-tests.
I'm starting QEMU with:
.../qemu-system-arm "--machine" "virt" "--cpu" "cortex-a15" "--nographic" "-d"
"unimp,guest_errors" "--semihosting-config"
"enable=on,target=nati
On 6/2/22 14:06, Frederic Barrat wrote:
On 02/06/2022 19:00, Cédric Le Goater wrote:
On 6/2/22 18:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID regi
On Wed, Jun 1, 2022, 3:29 AM Thomas Huth wrote:
> On 31/05/2022 20.28, John Snow wrote:
> > On Mon, May 30, 2022 at 3:33 AM Thomas Huth wrote:
> >>
> >> On 26/05/2022 02.09, John Snow wrote:
> >>> This is needed to be able to add a venv-building step to 'make check';
> >>> the clang-user job in
On Wed, Jun 1, 2022, 6:06 AM Paolo Bonzini wrote:
> On 5/27/22 16:27, John Snow wrote:
> > Paolo: I assume this falls under your jurisdiction...ish, unless Cleber
> > (avocado) or Alex (tests more broadly) have any specific inputs.
> >
> > I'm fine with waiting for reviews, but don't know whose b
On 26/05/2022 13.07, Daniel P. Berrangé wrote:
This converts the main build and container jobs to use the
base job rules, defining the following new variables
- QEMU_JOB_SKIPPED - jobs that are known to be currently
broken and should not be run. Can still be manually
launched if desire
On 02/06/2022 19:00, Cédric Le Goater wrote:
On 6/2/22 18:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do the data structure
l
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