On Thu, Oct 27, 2022 at 2:47 PM Eugenio Perez Martin
wrote:
>
> On Thu, Oct 27, 2022 at 6:32 AM Jason Wang wrote:
> >
> >
> > 在 2022/10/26 17:53, Eugenio Pérez 写道:
> > > Now that qemu can handle and emulate it if the vdpa backend does not
> > > support it we can offer it always.
> > >
> > > Signe
On Thu, Oct 27, 2022 at 6:32 AM Jason Wang wrote:
>
>
> 在 2022/10/26 17:53, Eugenio Pérez 写道:
> > Now that qemu can handle and emulate it if the vdpa backend does not
> > support it we can offer it always.
> >
> > Signed-off-by: Eugenio Pérez
>
>
> I may miss something but isn't more easier to si
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of shpc_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci-bridge/pci_bridge_dev.c | 2 +-
hw/pci-bridge/pcie_pci_bridg
On 26/10/2022 01.50, Philippe Mathieu-Daudé wrote:
We use the .h.inc extension to include C headers. To be consistent
with the rest of the codebase, rename the C headers using the .def
extension.
IDE/tools using our .editorconfig / .gitattributes will leverage
this consistency.
Signed-off-by: P
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msi_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msi.c | 9 +
1 file changed, 1 insertion(+), 8 deletion
Le 26/10/2022 à 17:25, Michael Tokarev a écrit :
27.09.2022 15:43, Laurent Vivier wrote:
Use exec_path to re-execute the binary from /proc/self/exe
Fix do_openat() that should not use execfd.
v2:
- don't use execfd as it can't be closed and is usable by the child
Why can't it be closed? I me
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
The
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci-bridge/i82801b11.c | 14 ++
h
On 26/10/2022 18.05, Cornelia Huck wrote:
Signed-off-by: Cornelia Huck
---
tests/qtest/arm-cpu-features.c | 76 ++
1 file changed, 76 insertions(+)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 5a145273860c..e264d2178a8b 10
The code generating errors in pci_add_capability has a comment which
says:
> Verify that capabilities don't overlap. Note: device assignment
> depends on this check to verify that the device is not broken.
> Should never trigger for emulated devices, but it's helpful for
> debugging these.
Indeed
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msix_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msix.c | 8 ++--
1 file changed, 2 insertions(+), 6 deleti
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 29 +++--
include/hw/pci/pci.h | 12 ++--
2 files changed, 9 insertions(+), 32 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 8ee2171011..8ff71e4553 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of slotid_cap_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/slotid_cap.c | 8 ++--
1 file changed, 2 insertions(
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of a PCIe function which calls
pci_add_capability() in turn is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
Acked-by: Jonathan Cameron (for CXL parts)
---
docs/pcie_sriov.txt
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
The
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
vfio_add_std_cap() is designed to ensure that capabilities do not
overlap, but it failed to do so for MSI and MSI-X capabilities.
Ensure MSI and MSI-X capabilities do not overlap with others by omitting
other overlapping capabilities.
Signed-off-by: Akihiko Odaki
---
hw/vfio/pci.c | 55
On Thu, Oct 27, 2022 at 11:26:09AM +0800, Yicong Yang wrote:
> From: Yicong Yang
>
> This series mainly change the policy for building a cluster topology node
> in PPTT. Previously we'll always build a cluster node in PPTT without
> asking the user, after this set the cluster node will be built o
The fid instruction (Floating-Point Identify) puts the FPU model and
revision into the Status Register. Since those values shouldn't be 0,
store values there which a PCX-L2 (for 32-bit) or a PCX-W2 (for 64-bit)
would return.
Signed-off-by: Helge Deller
diff --git a/target/hppa/insns.decode b/tar
On Thu, 27 Oct 2022 at 04:40, Michael S. Tsirkin wrote:
>
> On Tue, Oct 25, 2022 at 10:55:18AM -0600, Alex Williamson wrote:
> > On Wed, 26 Oct 2022 00:37:33 +0800
> > Cindy Lu wrote:
> > > diff --git a/softmmu/memory.c b/softmmu/memory.c
> > > index 7ba2048836..03940c551d 100644
> > > --- a/soft
On Tue, Oct 11, 2022 at 01:17:31PM +0200, Julia Suvorova wrote:
> Changes in the tables (for 275 cores):
> FACP:
> + Use APIC Cluster Model (V4) : 1
>
> APIC:
> +[02Ch 0044 1]Subtable Type : 00 [Processor Local APIC]
> +[02Dh 0045 1] Length
Markus Armbruster writes:
> Thomas Huth writes:
>
>> On 12/10/2022 17.38, Markus Armbruster wrote:
>>> When you try to set qtest property "log" while the qtest object is
>>> active, the error message blames "insufficient permission":
>>>
>>> $ qemu-system-x86_64 -S -display none -nodefault
Just noticed this when disassembling:
Parsing completed
ACPI Warning: NsLookup: Type mismatch on ODAT (RegionField), searching for
(Buffer) (20210604/nsaccess-760)
Disassembly completed
ASL Output:/tmp/old-asl2/tests/data/acpi/virt/SSDT.memhp.dsl - 14945 bytes
Did not look into this yet but
Am 31.03.22 um 10:25 schrieb Christian Borntraeger:
Am 31.03.22 um 09:44 schrieb Christian Borntraeger:
Am 21.02.22 um 11:27 schrieb Christian Borntraeger:
Am 10.02.22 um 18:44 schrieb Vladimir Sementsov-Ogievskiy:
10.02.2022 20:13, Thomas Huth wrote:
On 10/02/2022 15.51, Christian Bo
Akihiko Odaki writes:
> Omitting errp for pci_add_capability() causes it to abort if
> capabilities overlap. This behavior is appropriate heare because all of
Typo: here
Same for later patches.
> the capabilities set in this device are defined in the program and
> their overlap should not happ
Sync headers with kernel commit 247f34f7b803
Signed-off-by: Mayuresh Chitale
---
include/standard-headers/drm/drm_fourcc.h | 34 -
include/standard-headers/linux/ethtool.h | 63 +++-
include/standard-headers/linux/fuse.h | 6 +-
.../linux/input-event-codes.h
Currently the single and multi letter ISA extensions exposed to the guest
vcpu don't confirm to the KVM policies. This patchset updates the kvm headers
and applies policies set in KVM to the extensions exposed to the guest.
Mayuresh Chitale (3):
update-linux-headers: Version 6.1-rc2
target/ris
Currently the ISA string for a CPU is generated from two different
arrays, one for single letter extensions and another for multi letter
extensions. Add all the single letter extensions to the isa_ext_data
array and use it for generating the ISA string. Also drop 'P' and 'Q'
extensions from the lis
Set the state of each ISA extension on the vcpu depending on what
is set in the CPU property and what is allowed by KVM for that extension.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 11 -
target/riscv/kvm.c | 88 ++--
target/risc
On Tue, Oct 25, 2022 at 6:49 PM BALATON Zoltan wrote:
> Since only one week is left until freeze starts I've included some
> more patches in this version that I've intended to submit after the
> clean ups but we're running out of time now. The last 3 patches could
> be squashed together, I've jus
在 2022/10/26 17:53, Eugenio Pérez 写道:
Now that qemu can handle and emulate it if the vdpa backend does not
support it we can offer it always.
Signed-off-by: Eugenio Pérez
I may miss something but isn't more easier to simply remove the
_F_STATUS from vdpa_feature_bits[]?
Thanks
---
On Thu, Oct 6, 2022 at 12:52 AM Christoph Muellner
wrote:
>
> This patch adds support for the Zawrs ISA extension.
> Given the current (incomplete) implementation of reservation sets
> there seems to be no way to provide a full emulation of the WRS
> instruction (wake on reservation set invalidati
From: Yicong Yang
This series mainly change the policy for building a cluster topology node
in PPTT. Previously we'll always build a cluster node in PPTT without
asking the user, after this set the cluster node will be built only the
the user specify through "-smp clusters=X".
One problem is rel
From: Yicong Yang
Add *.topology tables for the aarch64's topology test.
Signed-off-by: Yicong Yang
---
tests/data/acpi/virt/APIC.topology | Bin 0 -> 700 bytes
tests/data/acpi/virt/DSDT.topology | Bin 0 -> 5398 bytes
tests/data/acpi/virt/PPTT.topology | Bin 0 -> 336 bytes
3 files changed, 0
From: Yicong Yang
Update the ACPI tables according to the acpi aml_build change.
Signed-off-by: Yicong Yang
---
tests/data/acpi/virt/PPTT | Bin 96 -> 76 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/tests/data/acpi/virt/PPTT b/tests/data/acpi/virt/PPTT
index
f56ea63b369
From: Yicong Yang
Add test for aarch64's ACPI topology building for all the supported
levels.
Signed-off-by: Yicong Yang
---
tests/qtest/bios-tables-test.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.
From: Yicong Yang
Currently we'll always generate a cluster node no matter user has
specified '-smp clusters=X' or not. Cluster is an optional level
and will participant the building of Linux scheduling domains and
only appears on a few platforms. It's unncessary to always build
it which cannot r
On Thu, Oct 6, 2022 at 12:52 AM Christoph Muellner
wrote:
>
> This patch adds support for the Zawrs ISA extension.
> Given the current (incomplete) implementation of reservation sets
> there seems to be no way to provide a full emulation of the WRS
> instruction (wake on reservation set invalidati
Hi Michael,
On 2022/10/26 22:52, Michael S. Tsirkin wrote:
> On Thu, Sep 22, 2022 at 09:11:39PM +0800, Yicong Yang wrote:
>> From: Yicong Yang
>>
>> This series mainly change the policy for building a cluster topology node
>> in PPTT. Previously we'll always build a cluster node in PPTT without
>
Xiaojuan,
can you modify the tile like "Load FDT table into dram memory space"
rather than "change base addr to 2MiB" ?
regards
bibo,mao
在 2022/10/21 11:54, Xiaojuan Yang 写道:
> Change FDT base addr to 2 MiB in lowmem region. Since lowmem
> region starts from 0, FDT base address is located at 2 M
Hi Kevin,
On Sat, Sep 24, 2022 at 9:19 AM Bin Meng wrote:
>
> Hi,
>
> On Wed, Sep 21, 2022 at 8:10 PM Meng, Bin wrote:
> >
> > -Original Message-
> > From: Philippe Mathieu-Daudé On Behalf
> > Of Philippe Mathieu-Daudé
> > Sent: Sunday, September 18, 2022 5:32 AM
> > To: Bin Meng ; qem
Hi, All,
This is a "ping" email~.
It seems that the newest version of our patch has been ignored. So I
"ping" this patchset again.
All comments and suggestions have been revised and updated in this V6
version patch, and link for the patch is below:
https://lore.kernel.org/q
Parameter "uint32_t bit" is not used in function feature_word_description(),
so remove it.
Signed-off-by: Wang, Lei
---
target/i386/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e98780773c..0083a2a7f7 100644
--- a/target
This series aims to add a new CPU model SapphireRapids, and tries to
address the problem stated in
https://lore.kernel.org/all/20220812055751.14553-1-lei4.w...@intel.com/T/#mcf67dbd1ad37c65d7988c36a2b267be9afd2fb30,
so that named CPU model can define its own AMX values, and QEMU won't
pass the wron
Some feature words, e.g., feature words in AMX-related CPUID leaf 0x1D and
0x1E are not bit-wise but multiple bits represents one value. Handle this
situation when the values specified are not the same as which are reported
by KVM. The handling includes:
- The responsibility of masking bits and g
The AMX-related CPUID value, i.e., CPUID(0x1D,1):EAX, CPUID(0x1D,1):EBX,
CPUID(0x1D,1):ECX and CPUID(0x1E,0):EBX are hard-coded to Sapphire Rapids
without considering future platforms.
Replace these hard-coded values with env->features[], so QEMU can pass the
right value to KVM.
Signed-off-by: Wa
Some features use multiple CPUID bits to form a value to be used, e.g.,
CPUID(0x1E,0):EBX[23:08] is regarded as the tmul_maxn value for AMX.
Introduce a new struct "MultiBitFeatureInfo" to hold the information for
those features and create a corresponding member in struct FeatureWordInfo,
so that t
The new CPU model mostly inherits features from Icelake-Server, while
adding new features:
- AMX (Advance Matrix eXtensions)
- Bus Lock Debug Exception
and new instructions:
- AVX VNNI (Vector Neural Network Instruction):
- VPDPBUS: Multiply and Add Unsigned and Signed Bytes
- VPDPBUSDS:
CPUID leaf 0x1D and 0x1E enumerate tile and TMUL information for AMX.
Introduce FeatureWord FEAT_1D_1_EAX, FEAT_1D_1_EBX, FEAT_1D_1_ECX and
FEAT_1E_0_EBX. Thus these features of AMX can be expanded when
"-cpu host/max" and can be configured in named CPU model.
Signed-off-by: Wang, Lei
---
targe
On Wed, 2022-10-26 at 10:45 -0400, Michael S. Tsirkin wrote:
> On Thu, Sep 22, 2022 at 08:21:55PM +0800, Robert Hoo wrote:
> > And empty bios-tables-test-allowed-diff.h.
> >
> > Diff of ASL form, from qtest testlog.txt:
> >
> > --- /tmp/asl-RFWZS1.dsl 2022-09-22 18:25:06.191519589 +0800
> > +
On 10/26/2022 7:57 PM, Zhong, Yang wrote:
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES
On Thu, 27 Oct 2022 05:15:25 +0900
Akihiko Odaki wrote:
> The code generating errors in pci_add_capability has a comment which
> says:
> > Verify that capabilities don't overlap. Note: device assignment
> > depends on this check to verify that the device is not broken.
> > Should never trigger f
On Tue, Oct 25, 2022 at 11:13:43PM +0800,
Chao Peng wrote:
> A memslot with KVM_MEM_PRIVATE being set can include both fd-based
> private memory and hva-based shared memory. Architecture code (like TDX
> code) can tell whether the on-going fault is private or not. This patch
> adds a 'is_private'
On 10/26/22 16:51, B wrote:
Am 26. Oktober 2022 17:18:14 UTC schrieb Daniel Henrique Barboza
:
Hi,
Since this is being sent to qemu-ppc and has to do with e500 I decided to
take a look. I acked the e500 related patches, 5 and 7. Patch 6 LGTM as well
but I'd rather not ack it it's SD speci
On Wed, Oct 26, 2022 at 9:46 PM Philippe Mathieu-Daudé
wrote:
> IRQRC[A:D] registers reset value is 0x80. We were forcing
> the MIPS Malta machine routing to be able to boot a Linux
> kernel without any bootloader.
> We now have these registers initialized in the Malta machine
> write_bootloader(
On Wed, Oct 26, 2022 at 04:11:29PM -0400, Michael S. Tsirkin wrote:
> He does but in the end he sends patches not pull requests.
> I don't care really as long as someone will send it up.
>
Jonathan will submit this, it's not a critical issue so it can wait for
the larger feature set.
Early-boot e820 records will be inserted by the bios/efi/early boot
software and be reported to the kernel via insert_resource. Later, when
CXL drivers iterate through the regions again, they will insert another
resource and make the RESERVED memory area a child.
This RESERVED memory area causes
On Thu, Oct 20, 2022 at 05:52:47PM +0200, Eugenio Pérez wrote:
> Event idx helps to reduce the number of notifications between the device
> and the driver. It allows them to specify an index on the circular
> descriptors rings where to issue the notification, instead of a single
> binary indicator.
On Wed, Oct 26, 2022 at 11:53:00AM +0200, Eugenio Pérez wrote:
> The net config space is already copied from the device so it can me modified
> by qemu. In particular, this is already done to fix cases where the NIC does
> not expose the right fields.
>
> It's trivial to emulate _F_STATE with qemu
On Wed, Oct 26, 2022 at 04:20:40PM -0400, Michael S. Tsirkin wrote:
> On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> > Submitted as an extention to the multi-feature branch maintained
> > by Jonathan Cameron at:
> > https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24
> >
>
> I
On Wed, Oct 26, 2022 at 08:13:24PM +, Adam Manzanares wrote:
> On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> > Submitted as an extention to the multi-feature branch maintained
> > by Jonathan Cameron at:
> > https://urldefense.com/v3/__https://gitlab.com/jic23/qemu/-/tree/cxl
On Thu, Oct 20, 2022 at 12:34:22PM +0200, Eugenio Pérez wrote:
> A gratuitous ARP is recommended after a live migration to reduce the amount of
> time needed by the network links to be aware of the new location. A hypervisor
> may not have the knowledge of the guest network configuration, and this
On Tue, Oct 25, 2022 at 11:13:42PM +0800,
Chao Peng wrote:
> When private/shared memory are mixed in a large page, the lpage_info may
> not be accurate and should be updated with this mixed info. A large page
> has mixed pages can't be really mapped as large page since its
> private/shared pages
On Tue, Oct 25, 2022 at 10:55:18AM -0600, Alex Williamson wrote:
> On Wed, 26 Oct 2022 00:37:33 +0800
> Cindy Lu wrote:
> > diff --git a/softmmu/memory.c b/softmmu/memory.c
> > index 7ba2048836..03940c551d 100644
> > --- a/softmmu/memory.c
> > +++ b/softmmu/memory.c
> ...
> > +/*
> > +
On Tue, Oct 25, 2022 at 08:47:34PM -0400, Gregory Price wrote:
> Early-boot e820 records will be inserted by the bios/efi/early boot
> software and be reported to the kernel via insert_resource. Later, when
> CXL drivers iterate through the regions again, they will insert another
> resource and ma
On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> Submitted as an extention to the multi-feature branch maintained
> by Jonathan Cameron at:
> https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24
>
I am not supposed to merge this patchset yet, right?
That branch has a bunch of patc
On Fri, Oct 14, 2022 at 02:21:08PM +0100, Alex Bennée wrote:
> During migration the virtio device state can be restored before we
> restart the VM. As no devices can be running while the VM is paused it
> makes sense to bail out early in that case.
>
> This returns the order introduced in:
>
> 9
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of a PCIe function which calls
pci_add_capability() in turn is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
Acked-by: Jonathan Cameron (for CXL parts)
---
docs/pcie_sriov.txt
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
On Fri, Oct 14, 2022 at 03:20:02PM +0200, Laurent Vivier wrote:
> When virtio_net_flush_tx() reaches the tx_burst value all the queue is
> not flushed and nothing restart the timer or the bottom half function.
>
> For BH, this is only missing in the virtio_net_tx_complete() function.
> For the tim
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of slotid_cap_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/slotid_cap.c | 8 ++--
1 file changed, 2 insertions(
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of shpc_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci-bridge/pci_bridge_dev.c | 2 +-
hw/pci-bridge/pcie_pci_bridg
I believe this was dropped from my line because Jonathan carried a similar
commit on his branch.
Happy to push it up again as a separate commit if that is what you want.
Noted for the future on upstreams
-Original Message-
From: Michael S. Tsirkin
Sent: Wednesday, October 26, 2022 4:0
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
The code generating errors in pci_add_capability has a comment which
says:
> Verify that capabilities don't overlap. Note: device assignment
> depends on this check to verify that the device is not broken.
> Should never trigger for emulated devices, but it's helpful for
> debugging these.
Indeed
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msix_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msix.c | 8 ++--
1 file changed, 2 insertions(+), 6 deleti
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msi_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msi.c | 9 +
1 file changed, 1 insertion(+), 8 deletion
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
The
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci-bridge/i82801b11.c | 14 ++
h
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 29 +++--
include/hw/pci/pci.h | 12 ++--
2 files changed, 9 insertions(+), 32 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 8ee2171011..8ff71e4553 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
The
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> Submitted as an extention to the multi-feature branch maintained
> by Jonathan Cameron at:
> https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24
BTW pls set subject prefix for all patches, and put it before the patch #.
-v parameter
On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> Submitted as an extention to the multi-feature branch maintained
> by Jonathan Cameron at:
> https://urldefense.com/v3/__https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24__;!!EwVzqGoTKBqv-0DWAJBm!RyiGL5B1XmQnVFwgxikKJeosPMKtoO1cTr61
On Wed, Oct 12, 2022 at 05:37:57PM +0200, Markus Armbruster wrote:
> Markus Armbruster (4):
> qom: Improve error messages when property has no getter or setter
> backends: Improve error messages when property can no longer be set
> qtest: Improve error messages when property can not be set ri
He does but in the end he sends patches not pull requests.
I don't care really as long as someone will send it up.
On Wed, Oct 26, 2022 at 08:09:45PM +, Gregory Price wrote:
> I believe this was dropped from my line because Jonathan carried a similar
> commit on his branch.
>
> Happy to pus
On Thu, Oct 06, 2022 at 07:37:01PM -0400, Gregory Price wrote:
> Current code sets to STORAGE_EXPRESS and then overrides it.
>
> Signed-off-by: Gregory Price
If you expect me to merge it you need to CC me.
Also, do we need this separately from the series?
> ---
> hw/mem/cxl_type3.c | 3 +--
>
Am 24. Oktober 2022 07:35:48 UTC schrieb "Philippe Mathieu-Daudé"
:
>Hi Bernhard,
>
>On 22/10/22 17:04, Bernhard Beschow wrote:
>> Having an i8259 proxy allows for ISA PICs to be created and wired up in
>> southbridges. This is especially interesting for PIIX3 for two reasons:
>> First, the sou
Am 26. Oktober 2022 17:18:14 UTC schrieb Daniel Henrique Barboza
:
>Hi,
>
>Since this is being sent to qemu-ppc and has to do with e500 I decided to
>take a look. I acked the e500 related patches, 5 and 7. Patch 6 LGTM as well
>but I'd rather not ack it it's SD specific code.
>
>I'll send a Pow
IRQRC[A:D] registers reset value is 0x80. We were forcing
the MIPS Malta machine routing to be able to boot a Linux
kernel without any bootloader.
We now have these registers initialized in the Malta machine
write_bootloader(), so we can use the correct reset values.
Signed-off-by: Philippe Mathie
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