Re: [PATCH-for-8.0 v2 6/6] hw/virtio: Extract QMP related code virtio-qmp.c

On 19/12/22 14:31, Jonah Palmer wrote: On 12/13/22 06:17, Philippe Mathieu-Daudé wrote: The monitor decoders are the only functions using the CONFIG_xxx definitions declared in the target specific CONFIG_DEVICES header. Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/meson.build | 2 +

[PATCH] chardev: clean up chardev-parallel.c

Replace HAVE_CHARDEV_PARPORT with a Meson conditional, remove unnecessary defines, and close the file descriptor on FreeBSD/DragonFly. Signed-off-by: Paolo Bonzini --- chardev/char-parallel.c | 15 ++- chardev/meson.build | 5 - include/qemu/osdep.h| 5 - 3 files ch

[PATCH v21 06/10] virtio: add support for configure interrupt

Add the functions to support the configure interrupt in virtio The function virtio_config_guest_notifier_read will notify the guest if there is an configure interrupt. The function virtio_config_set_guest_notifier_fd_handler is to set the fd hander for the notifier Signed-off-by: Cindy Lu --- hw

Re: [PATCH v3 0/5] coroutine: Clean up includes

On 22/12/22 06:21, Markus Armbruster wrote: Philippe Mathieu-Daudé writes: PS: While looking for commits that caused these conflicts, I saw commit 28b629ab4aa93b9b7ec79c7e480611e4554586be Signed-off-by: Philippe Mathieu-Daudé mailto:phi...@linaro.org";> commit 697791

[PATCH v21 07/10] vhost: add support for configure interrupt

Add functions to support configure interrupt. The configure interrupt process will start in vhost_dev_start and stop in vhost_dev_stop. Also add the functions to support vhost_config_pending and vhost_config_mask. Signed-off-by: Cindy Lu --- hw/virtio/vhost.c | 78 ++

[PATCH v21 08/10] virtio-net: add support for configure interrupt

Add functions to support configure interrupt in virtio_net Add the functions to support vhost_net_config_pending and vhost_net_config_mask. Signed-off-by: Cindy Lu --- hw/net/vhost_net-stub.c | 9 + hw/net/vhost_net.c | 9 + hw/net/virtio-net.c | 4 ++-- include/net/vhos

[PATCH v21 09/10] virtio-mmio: add support for configure interrupt

Add configure interrupt support in virtio-mmio bus. add function to set configure guest notifier. Signed-off-by: Cindy Lu --- hw/virtio/virtio-mmio.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index d240efef9

[PATCH v21 10/10] virtio-pci: add support for configure interrupt

Add process to handle the configure interrupt, The function's logic is the same with vq interrupt.Add extra process to check the configure interrupt Signed-off-by: Cindy Lu --- hw/virtio/virtio-pci.c | 118 +++-- include/hw/virtio/virtio-pci.h | 4 +- 2 file

[PATCH v21 05/10] vhost-vdpa: add support for config interrupt

Add new call back function in vhost-vdpa, The function vhost_set_config_call can set the event fd to kernel. This function will be called in the vhost_dev_start and vhost_dev_stop Signed-off-by: Cindy Lu --- hw/virtio/trace-events | 1 + hw/virtio/vhost-vdpa.c | 8 2 files changed, 9 in

[PATCH v21 03/10] virtio-pci: decouple the single vector from the interrupt process

To reuse the interrupt process in configure interrupt Need to decouple the single vector from the interrupt process. We add new function kvm_virtio_pci_vector_use_one and _release_one. These functions are used for the single vector, the whole process will finish in the loop with vq number. Signed-

[PATCH v21 01/10] virtio: introduce macro VIRTIO_CONFIG_IRQ_IDX

To support configure interrupt for vhost-vdpa Introduce VIRTIO_CONFIG_IRQ_IDX -1 as configure interrupt's queue index, Then we can reuse the functions guest_notifier_mask and guest_notifier_pending. Add the check of queue index in these drivers, if the driver does not support configure interrupt, t

[PATCH v21 00/10] vhost-vdpa: add support for configure interrupt

These patches introduced the support for configure interrupt These codes are tested on x86_64 and aarch64 platforms. the test scenario is based on vp-vdpa/vdpa_sim_net /vhost/vhost_user/testpmd, with/without irqfd. Tested in virtio-pci bus and virtio-mmio bus Change in v2: Add support for v

[PATCH v21 04/10] vhost: introduce new VhostOps vhost_set_config_call

This patch introduces new VhostOps vhost_set_config_call. This function allows the qemu to set the config event fd to kernel driver. Signed-off-by: Cindy Lu --- include/hw/virtio/vhost-backend.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/hw/virtio/vhost-backend.h b/include/h

[PATCH v21 02/10] virtio-pci: decouple notifier from interrupt process

To reuse the notifier process. We add the virtio_pci_get_notifier to get the notifier and vector. The INPUT for this function is IDX, The OUTPUT is the notifier and the vector Signed-off-by: Cindy Lu --- hw/virtio/virtio-pci.c | 88 +++--- 1 file changed, 57 i

Re: [PATCH 0/5] include/hw/pci include/hw/cxl: Clean up includes

"Michael S. Tsirkin" writes: > On Fri, Dec 09, 2022 at 02:47:57PM +0100, Markus Armbruster wrote: >> Back in 2016, we discussed[1] rules for headers, and these were >> generally liked: >> >> 1. Have a carefully curated header that's included everywhere first. We >>got that already thanks to

Re: [PATCH] meson: Clean up some dependencies regarding qemu-system

On 12/21/22 08:49, Michael Tokarev wrote: 20.12.2022 23:56, Helge Deller wrote: .. Given that info, would it then make sense to keep as is:     --enable-system     --enable-user     --enable-tools -> qemu-bridge-helper, vhost-user-gpu, virtfs-proxy-helper, virtiofsd     --enable-guest-agent ->

Re: [PATCH v3 0/5] coroutine: Clean up includes

Philippe Mathieu-Daudé writes: > On 21/12/22 14:14, Markus Armbruster wrote: >> v3: >> * PATCH 4: Unnecessary hunks dropped >> v2: >> * Rebased >> * PATCH 4: Rewritten [Paolo] >> * PATCH 5: New >> Markus Armbruster (5): >>coroutine: Clean up superfluous inclusion of qemu/coroutine.h >>cor

[PATCH] linux-user: Allow 64-bit offsets in mmap2() syscall on 32-bit targets

The mmap2() syscall allows 32-bit guests to specify the offset into a mapping in 4096-byte units (instead of bytes, as is done by mmap(2)). This enables applications that use a 32-bit off_t to map large files (up to 2^44 bytes). So when emulating the mmap2 syscall the offset parameter is shifted b

Re: [PATCH v3 3/4] vdpa: handle VIRTIO_NET_CTRL_ANNOUNCE in vhost_vdpa_net_handle_ctrl_avail

On Wed, Dec 21, 2022 at 7:50 PM Eugenio Pérez wrote: > > Since this capability is emulated by qemu shadowed CVQ cannot forward it > to the device. Process all that command within qemu. > > Signed-off-by: Eugenio Pérez Acked-by: Jason Wang Thanks > --- > net/vhost-vdpa.c | 15 ---

Re: [PATCH v3 2/4] virtio_net: copy VIRTIO_NET_S_ANNOUNCE if device model has it

On Wed, Dec 21, 2022 at 7:50 PM Eugenio Pérez wrote: > > Status part of the emulated feature. It will follow device model, so we > must copy it as long as NIC device model has it set. > > Signed-off-by: Eugenio Pérez Acked-by: Jason Wang Thanks > --- > v3: Add virtio byte swapping writing net

[PATCH v2 8/8] hw/cxl/events: Add in inject general media event

To facilitate testing provide a QMP command to inject a general media event. The event can be added to the log specified. Signed-off-by: Ira Weiny --- Changes from RFC: Add all fields for this event irq happens automatically when log transitions from 0 to 1 --- hw/mem/cxl_type3

[PATCH v2 0/8] QEMU CXL Provide mock CXL events and irq support

events.h | 126 ++ include/qemu/bswap.h| 40 +++ include/qemu/uuid.h | 12 +++ qapi/cxl.json | 25 + 11 files changed, 785 insertions(+), 45 deletions(-) --- base-commit: 1b4133103d20fc3fea05c7ceca4a242468a5179d change-id: 20221221-ira-cxl-events-2022-11-17-fef53f9b9ac2 Best regards, -- Ira Weiny

[PATCH v2 4/8] hw/cxl/events: Add event status register

The device status register block was defined. However, there were no individual registers nor any data wired up. Define the event status register [CXL 3.0; 8.2.8.3.1] as part of the device status register block. Wire up the register and initialize the event status for each log. To support CXL 3

[PATCH v2 6/8] hw/cxl/events: Add event interrupt support

Replace the stubbed out CXL Get/Set Event interrupt policy mailbox commands. Enable those commands to control interrupts for each of the event log types. Skip the standard input mailbox length on the Set command due to DCD being optional. Perform the checks separately. Signed-off-by: Ira Weiny

[PATCH v2 1/8] qemu/bswap: Add const_le64()

Gcc requires constant versions of cpu_to_le* calls. Add a 64 bit version. Reviewed-by: Jonathan Cameron Reviewed-by: Peter Maydell Signed-off-by: Ira Weiny --- Changes from RFC: Peter Change order of the definitions, 64-32-16 --- include/qemu/bswap.h | 10 ++

[PATCH v2 2/8] qemu/uuid: Add UUID static initializer

UUID's are defined as network byte order fields. No static initializer was available for UUID's in their standard big endian format. Define a big endian initializer for UUIDs. Reviewed-by: Jonathan Cameron Signed-off-by: Ira Weiny --- include/qemu/uuid.h | 12 1 file changed, 12

[PATCH v2 5/8] hw/cxl/events: Wire up get/clear event mailbox commands

CXL testing is benefited from an artificial event log injection mechanism. Add an event log infrastructure to insert, get, and clear events from the various logs available on a device. Replace the stubbed out CXL Get/Clear Event mailbox commands with commands that operate on the new infrastructur

[PATCH v2 3/8] hw/cxl/mailbox: Use new UUID network order define for cel_uuid

The cel_uuid was programatically generated previously because there was no static initializer for network order UUIDs. Use the new network order initializer for cel_uuid. Adjust cxl_initialize_mailbox() because it can't fail now. Update specification reference. Signed-off-by: Ira Weiny --- Ch

[PATCH v2 7/8] bswap: Add the ability to store to an unaligned 24 bit field

CXL has 24 bit unaligned fields which need to be stored to. CXL is specified as little endian. Define st24_le_p() and the supporting functions to store such a field from a 32 bit host native value. The use of b, w, l, q as the size specifier is limiting. So "24" was used for the size part of th

Re: [RFC PATCH-for-8.0 2/3] hw/ppc/spapr: Replace tswap64(HPTE) by cpu_to_be64(HPTE)

On Wed, Dec 21, 2022 at 10:15:28PM +, Peter Maydell wrote: > On Wed, 21 Dec 2022 at 16:03, Cédric Le Goater wrote: > > > > On 12/21/22 13:33, Peter Maydell wrote: > > > On Wed, 21 Dec 2022 at 01:35, David Gibson > > > wrote: > > >> On Mon, Dec 19, 2022 at 10:39:40AM +, Peter Maydell wrot

Re: [PATCH-for-8.0 4/4] hw/ppc/spapr_ovec: Avoid target_ulong spapr_ovec_parse_vector()

On Wed, Dec 21, 2022 at 10:26:51AM -0300, Daniel Henrique Barboza wrote: > > > On 12/21/22 06:46, Cédric Le Goater wrote: > > On 12/16/22 17:47, Daniel Henrique Barboza wrote: > > > > > > > > > On 12/13/22 09:35, Philippe Mathieu-Daudé wrote: > > > > spapr_ovec.c is a device, but it uses target

Re: [PATCH v20 08/10] virtio-net: add support for configure interrupt

On Wed, 21 Dec 2022 at 19:25, Michael S. Tsirkin wrote: > > On Mon, Dec 12, 2022 at 01:20:40AM +0800, Cindy Lu wrote: > > Add functions to support configure interrupt in virtio_net > > Add the functions to support vhost_net_config_pending > > and vhost_net_config_mask. > > > > Signed-off-by: Cindy

Re: Re: [for-8.0 v2 00/11] Refactor cryptodev

On 12/20/22 23:36, Michael S. Tsirkin wrote: On Tue, Nov 22, 2022 at 10:07:45PM +0800, zhenwei pi wrote: v1 -> v2: - fix coding style and use 'g_strjoin()' instead of 'char services[128]' (suggested by Dr. David Alan Gilbert) - wrapper function 'cryptodev_backend_account' to record statist

Re: [PATCH v10 1/9] mm: Introduce memfd_restricted system call to create restricted user memory

On Wed, 2022-12-21 at 21:39 +0800, Chao Peng wrote: > > On Tue, Dec 20, 2022 at 08:33:05AM +, Huang, Kai wrote: > > > > On Tue, 2022-12-20 at 15:22 +0800, Chao Peng wrote: > > > > > > On Mon, Dec 19, 2022 at 08:48:10AM +, Huang, Kai wrote: > > > > > > > > On Mon, 2022-12-19 at 15:53 +0800,

Re: [PATCH v4 00/30] This series consolidates the implementations of the PIIX3 and PIIX4 south

Am 21. Dezember 2022 19:15:04 UTC schrieb "Philippe Mathieu-Daudé" : >On 21/12/22 17:59, Bernhard Beschow wrote: >> code as possible and to bring both device models to feature parity such that >> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. >> This >> could resol

[PULL v2 45/45] hw/intc: sifive_plic: Fix the pending register range check

From: Bin Meng The pending register upper limit is currently set to plic->num_sources >> 3, which is wrong, e.g.: considering plic->num_sources is 7, the upper limit becomes 0 which fails the range check if reading the pending register at pending_base. Fixes: 1e24429e40df ("SiFive RISC-V PLIC Bl

[PULL v2 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order

From: Bin Meng SHAKTI_C machine Kconfig option was inserted in disorder. Fix it. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Wilfred Mallawa Message-Id: <20221211030829.802437-4-bm...@tinylab.org> Signed-off-by: Alistair Francis ---

[PATCH 0/4] exagon (target/hexagon) Add overrides for COF insns

The idef-parser skips the change-of-flow (COF) instructions, so add overrides Taylor Simpson (4): Hexagon (target/hexagon) Add overrides for jumpr31 instructions Hexagon (target/hexagon) Add overrides for callr Hexagon (target/hexagon) Add overrides for endloop1/endloop01 Hexagon (target/h

[PULL v2 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser

From: Bin Meng At present the PLIC config parser can only handle legal config string like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is given the parser won't get the correct configuration. This commit improves the config parser to make it more robust. Signed-off-by: Bin Meng A

[PULL v2 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro

From: Wilfred Mallawa use the `FIELD32_1CLEAR` macro to implement register `rw1c` functionality to `ibex_spi`. This change was tested by running the `SPI_HOST` from TockOS. Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Message-Id: <20221017054950.317584-3-wilfred.mall...@openso

[PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured

From: Bin Meng The priv spec v1.12 says: If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails. Failed accesses generate an instruction, load, or store access-fault ex

[PULL v2 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC

From: Bin Meng Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build") the IBEX PLIC model was replaced with the SiFive PLIC model in the 'opentitan' machine but we forgot the add the dependency there. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alis

[PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn

From: Richard Henderson Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-sta...@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis

[PULL v2 09/45] target/riscv: Add smstateen support

From: Mayuresh Chitale Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale Reviewed-by

[PULL v2 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC

From: Bin Meng Per chapter 6.5.2 in [1], the number of interupt sources including interrupt source 0 should be 187. [1] PolarFire SoC MSS TRM: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pd

[PULL v2 38/45] hw/intc: sifive_plic: Update "num-sources" property default value

From: Bin Meng At present the default value of "num-sources" property is zero, which does not make a lot of sense, as in sifive_plic_realize() we see s->bitfield_words is calculated by: s->bitfield_words = (s->num_sources + 31) >> 5; if the we don't configure "num-sources" property its defaul

[PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState

From: LIU Zhiwei Avoid calling riscv_itrigger_enabled() when calculate the tbflags. As the itrigger enable status can only be changed when write tdata1, migration load or itrigger fire, update env->itrigger_enabled at these places. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Messag

[PULL v2 35/45] hw/intc: sifive_plic: Drop PLICMode_H

From: Bin Meng H-mode has been removed since priv spec 1.10. Drop it. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis Message-Id: <20221211030829.802437-6-bm...@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/intc/sifive_plic.h | 1 - hw/intc/s

[PULL v2 12/45] target/riscv: Add itrigger support when icount is not enabled

From: LIU Zhiwei When icount is not enabled, there is no API in QEMU that can get the guest instruction number. Translate the guest code in a way that each TB only has one instruction. After executing the instruction, decrease the count by 1 until it reaches 0 where the itrigger fires. Note tha

[PATCH 1/4] Hexagon (target/hexagon) Add overrides for jumpr31 instructions

Add overrides for SL2_jumpr31Unconditional SL2_jumpr31_t Predicated true (old value) SL2_jumpr31_f Predicated false (old value) SL2_jumpr31_tnew Predicated true (new value) SL2_jumpr31_fnew Predicated false (new value) Signed-off-by: Ta

[PATCH 2/4] Hexagon (target/hexagon) Add overrides for callr

Add overrides for J2_callr J2_callrt J2_callrf Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 6 ++ target/hexagon/macros.h | 10 -- target/hexagon/genptr.c | 20 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/target

[PULL v2 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization

From: Bin Meng "hartid-base" and "priority-base" are zero by default. There is no need to initialize them to zero again. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis Message-Id: <20221211030829.802437-15-bm...@tinylab.org> Signed-off-by: Alistair Francis

[PULL v2 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()

From: Bin Meng The realize() callback has an errp for us to propagate the error up. While we are here, correct the wrong multi-line comment format. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221211030829.802437-8-bm...@tinylab.org>

[PATCH 4/4] Hexagon (target/hexagon) Add overrides for dealloc-return instructions

These instructions perform a deallocframe+return (jumpr r31) Add overrides for L4_return SL2_return L4_return_t L4_return_f L4_return_tnew_pt L4_return_fnew_pt L4_return_tnew_pnt L4_return_fnew_pnt SL2_return_t SL2_return_f SL2_return_tnew SL2_return

[PULL v2 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers

From: Bin Meng hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in both riscv_aplic_realize() and riscv_imsic_realize(). Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC. Signed-off-by: Bi

[PULL v2 13/45] target/riscv: Add itrigger support when icount is enabled

From: LIU Zhiwei The max count in itrigger can be 0x3FFF, which will cause a no trivial translation and execution overload. When icount is enabled, QEMU provides API that can fetch guest instruction number. Thus, we can set an timer for itrigger with the count as deadline. Only when timer expir

[PULL v2 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb

From: Bin Meng Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which is VIRTIO_NDEV and also used as the value of "riscv,ndev" property in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM

[PULL v2 10/45] target/riscv: smstateen check for h/s/envcfg

From: Mayuresh Chitale Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20

[PULL v2 27/45] target/riscv: Simplify helper_sret() a little bit

From: Bin Meng There are 2 paths in helper_sret() and the same mstatus update codes are replicated. Extract the common parts to simplify it a little bit. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20221207090037.281452-1-bm...@tinylab.org> Signed-off-by: Alistair Franci

[PULL v2 08/45] hw/riscv/opentitan: add aon_timer base unimpl

From: Wilfred Mallawa Adds the updated `aon_timer` base as an unimplemented device. This is used by TockOS, patch ensures the guest doesn't hit load faults. Signed-off-by: Wilfred Mallawa Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20221025043335.339815-3-wilfred.mall...@

[PULL v2 40/45] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC

From: Bin Meng Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003 supports 52 interrupt sources while G000 supports 51 interrupt sources. We use the value of G002 and G003, so it is 53 (including source 0). [1] G000 manual: https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c

[PULL v2 29/45] RISC-V: Add Zawrs ISA extension support

From: Christoph Muellner This patch adds support for the Zawrs ISA extension. Given the current (incomplete) implementation of reservation sets there seems to be no way to provide a full emulation of the WRS instruction (wake on reservation set invalidation or timeout or interrupt). Therefore, we

[PULL v2 07/45] hw/riscv/opentitan: bump opentitan

From: Wilfred Mallawa This patch updates the OpenTitan model to match the specified register layout as per [1]. Which is also the latest commit of OpenTitan supported by TockOS. Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes any references to Padctrl. Note: OpenT

[PULL v2 11/45] target/riscv: generate virtual instruction exception

From: Mayuresh Chitale This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-I

[PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented

From: Conor Dooley The Fabric Interconnect Controllers provide interfaces between the FPGA fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered 0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and does not show up on the MSS memory map. FIC4 is dedicated to th

[PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode

From: Jim Shu let tlb_fill() function also increments PMU counter when it is from two-stage translation, so QEMU could also monitor these PMU events when CPU runs in VS/VU mode (like running guest OS). Signed-off-by: Jim Shu Reviewed-by: Alistair Francis Message-Id: <20221123090635.6574-1-jim.

[PULL v2 34/45] hw/riscv: spike: Remove misleading comments

From: Bin Meng PLIC is not included in the 'spike' machine. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis Message-Id: <20221211030829.802437-5-bm...@tinylab.org> Signed-off-by: Alistair Francis --- hw/riscv/spike.c | 1 - 1 file changed, 1 deletion(-) d

[PULL v2 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0

From: Bin Meng At present the SiFive PLIC model "priority-base" expects interrupt priority register base starting from source 1 instead source 0, that's why on most platforms "priority-base" is set to 0x04 except 'opentitan' machine. 'opentitan' should have set "priority-base" to 0x04 too. Note

[PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()

From: Bin Meng sstatus register dump is currently missing in riscv_cpu_dump_state(). As sstatus is a copy of mstatus, which is described in the priv spec, it seems redundant to print the same information twice. Add some comments for this to let people know this is intentional. Signed-off-by: Bi

[PULL v2 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+

From: Bin Meng Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when leaving M-mode. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20221207090037.281452-2-bm...@tinylab.org> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 6 ++ 1 file change

[PULL v2 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC

From: Bin Meng hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt controllers regardless of how MSI is implemented. msi_nonbroken is initialized to true in sifive_plic_realize(). Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from RISC-V machines. Signed-off-by: Bin

[PULL v2 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2

From: Richard Henderson There was a typo using opc_addi instead of opc_add with the two registers. While we're at it, simplify the gating test to al == bl to improve dynamic scheduling even when the output register does not overlap the inputs. Reported-by: LIU Zhiwei Signed-off-by: Richard Hen

[PULL v2 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12

From: Richard Henderson We were matching a signed 13-bit range, not a 12-bit range. Expand the commentary within the function and be explicit about all of the ranges. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <2

[PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support

From: Frédéric Pétrot Commit 40244040a7a changed the way the S irqs are numbered. This breaks when using numa configuration, e.g.: ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \ -m 2G -smp cpus=16 \ -object memory-backend-ram,id=

[PULL v2 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"

From: Bin Meng At present magic number is used to create "riscv,ndev" property in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that is used to instantiate the PLIC model instead. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis Message-Id: <20221211

[PULL v2 18/45] hw/riscv: virt: Remove the redundant ipi-id property

From: Atish Patra The imsic DT binding[1] has changed and no longer require an ipi-id. The latest IMSIC driver dynamically allocates ipi id if slow-ipi is not defined. Get rid of the unused dt property which may lead to confusion. [1] https://lore.kernel.org/lkml/2022044207.1478350-5-apa..

[PATCH 3/4] Hexagon (target/hexagon) Add overrides for endloop1/endloop01

Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 4 ++ target/hexagon/genptr.c | 79 2 files changed, 83 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 231654e6c1..1ac23b75a0 100644 --- a/target/hexagon/

[PULL v2 01/45] target/riscv: Fix PMP propagation for tlb

From: LIU Zhiwei Only the pmp index that be checked by pmp_hart_has_privs can be used by pmp_get_tlb_size to avoid an error pmp index. Before modification, we may use an error pmp index. For example, we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there is an pmp rule, valid r

[PULL v2 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro

From: Wilfred Mallawa Adds a helper macro that implements the register `w1c` functionality. Ex: uint32_t data = FIELD32_1CLEAR(val, REG, FIELD); If ANY bits of the specified `FIELD` is set then the respective field is cleared and returned to `data`. If the field is cleared (0), then no chang

[PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller as unimplemented

From: Conor Dooley The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for stori

[PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb

From: Conor Dooley On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by "Clock Conditioning Circuitry" in the FPGA. The specific clock depends on the FPGA bitstream & can be locked to one particular {D,P}LL - in the Icicle Kit Reference Design v2022.09 or later this is/will be

[PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array

From: Jim Shu If the number of interrupt is not multiple of 32, PLIC will have out-of-bound access to source_priority array. Compute the number of interrupt in the last word to avoid this out-of-bound access of array. Signed-off-by: Jim Shu Reviewed-by: Bin Meng Message-Id: <20221127165753.305

[PULL v2 14/45] target/riscv: Enable native debug itrigger

From: LIU Zhiwei When QEMU is not in icount mode, execute instruction one by one. The tdata1 can be read directly. When QEMU is in icount mode, use a timer to simulate the itrigger. The tdata1 may be not right because of lazy update of count in tdata1. Thus, We should pack the adjusted count int

[PULL v2 17/45] target/riscv: Typo fix in sstc() predicate

From: Anup Patel We should use "&&" instead of "&" when checking hcounteren.TM and henvcfg.STCE bits. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <20221108125703.1463577-2-apa...@ventanamicro.com> Signed-off-by:

[PULL v2 00/45] riscv-to-apply queue

From: Alistair Francis The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b: Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging (2022-12-21 18:08:09 +) are available in the Git repository at: https://github.com/alistair2

[PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st

From: Richard Henderson When guest_base != 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-extend, and it keeps the r

Re: [RFC PATCH-for-8.0 2/3] hw/ppc/spapr: Replace tswap64(HPTE) by cpu_to_be64(HPTE)

On Wed, 21 Dec 2022 at 16:03, Cédric Le Goater wrote: > > On 12/21/22 13:33, Peter Maydell wrote: > > On Wed, 21 Dec 2022 at 01:35, David Gibson > > wrote: > >> On Mon, Dec 19, 2022 at 10:39:40AM +, Peter Maydell wrote: > >>> OK. I still think we should consistently change all the places tha

Re: [PULL v2 00/14] ppc queue

#x27; of https://gitlab.com/rth7680/qemu into > staging (2022-12-21 14:15:18 +) > > are available in the Git repository at: > > https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20221221 > > for you to fetch changes up to 4091fabfeb54f02762bdecba7344353c56533873: > &g

Re: [PATCH v3 0/5] coroutine: Clean up includes

On 21/12/22 14:14, Markus Armbruster wrote: v3: * PATCH 4: Unnecessary hunks dropped v2: * Rebased * PATCH 4: Rewritten [Paolo] * PATCH 5: New Markus Armbruster (5): coroutine: Clean up superfluous inclusion of qemu/coroutine.h coroutine: Move coroutine_fn to qemu/osdep.h, trim includes

Re: [PATCH v2 1/5] exec/memory: Expose memory_region_access_valid()

On Sat, 2022-12-17 at 16:24 +0100, Philippe Mathieu-Daudé wrote: > Instead of having hardware device poking into memory > internal API, expose memory_region_access_valid(). > > Reviewed-by: Richard Henderson > Signed-off-by: Philippe Mathieu-Daudé That's the only memory_region_ function s390 ca

RE: [PATCH v2] Hexagon (target/hexagon) implement mutability mask for GPRs

> > +#define WRITE_REG_IN_PACKET(reg_name, output, input) \ > > +asm volatile("{ " reg_name " = %1 }\n\t" \ > > This is no different from the WRITE_REG above. Instructions on a line with > no curly braces are a single packet. > Understood. The feedback on Brian's patch said to write tests t

Re: [PATCH v3 1/2] tpm: convert tpmdev options processing to new visitor format

On Wed, 2022-12-21 at 16:32 +, Daniel P. Berrangé wrote: > This isn't a valid change todo, as it affects the public facing > data structure for the  query-tpm command. > > I understand why you're doing it though, to get rid fo the > extra nesting, which is a hangover from earlier QAPI days > w

RE: [PATCH v2] Hexagon (target/hexagon) implement mutability mask for GPRs

> -Original Message- > From: Marco Liebel > Sent: Wednesday, December 21, 2022 1:34 PM > To: Taylor Simpson ; Marco Liebel (QUIC) > ; qemu-devel@nongnu.org > Cc: Brian Cain > Subject: RE: [PATCH v2] Hexagon (target/hexagon) implement mutability > mask for GPRs > > > > +#define WRITE_R

[PATCH RFC v2 0/1] tests: add wasmtime testsuite

Hi, I made some updates based on the feedback from Alex. At the moment it mostly works for me on top of 6394578984da: aarch64, riscv64 and s390x are clean, but there are some failures on x86_64. With qemu-user vma rework it unfortunately fails in more places; I haven't analyzed these failures yet

[PATCH RFC v2 1/1] tests: add wasmtime testsuite

wasmtime is a WebAssembly runtime, which includes a large testsuite. This testsuite uses qemu-user (aarch64, riscv64, s390x and x86_64 are supported) in order to exercise foreign architectures. Over time it found several regressions in qemu itself, and it would be beneficial to catch the similar on

Re: [PATCH v4 00/30] This series consolidates the implementations of the PIIX3 and PIIX4 south

On 21/12/22 17:59, Bernhard Beschow wrote: code as possible and to bring both device models to feature parity such that perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this list before. The s

Re: [PATCH v2 0/7] Clean up dependencies of ACPI controllers

On Wed, Dec 21, 2022 at 05:56:56PM +, Bernhard Beschow wrote: > > > Am 16. Dezember 2022 13:03:48 UTC schrieb Bernhard Beschow > : > >This small series establishes consistency between ICH9, PIIX4 and VT82C686 > >ACPI > > > >controllers to select ACPI, ACPI_SMBUS and APM since they are provi

Re: [RFC PATCH 3/6] hw/cxl/cxl-events: Add CXL mock events

On Mon, Dec 19, 2022 at 10:07:23AM +, Jonathan Cameron wrote: > On Mon, 10 Oct 2022 15:29:41 -0700 > ira.we...@intel.com wrote: > > > From: Ira Weiny > > > > To facilitate testing of guest software add mock events and code to > > support iterating through the event logs. > > > > Signed-off-

[PATCH] hw/net: Fix read of uninitialized memory in imx_fec.

Size is used at lines 1088/1188 for the loop, which reads the last 4 bytes from the crc_ptr so it does need to get increased, however it shouldn't be increased before the buffer is passed to CRC computation, or the crc32 function will access uninitialized memory. This was pointed out to me by c...

[PATCH 01/15] tests/avocado: add RISC-V opensbi boot test

This test is used to do a quick sanity check to ensure that we're able to run the existing QEMU FW image. 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | RISCV32_BIOS_BIN firmware with minimal options. Cc: C

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