On 1/24/23 00:38, Sean Christopherson wrote:
> On Mon, Jan 23, 2023, Huang, Kai wrote:
>> On Mon, 2023-01-23 at 15:03 +0100, Vlastimil Babka wrote:
>>> On 12/22/22 01:37, Huang, Kai wrote:
>> I argue that this page pinning (or page migration prevention) is not
>> tied to where the page
Hello,
On 23.01.2023 19:14, Daniil Tatianin wrote:
On 1/23/23 4:47 PM, Daniel P. Berrangé wrote:
On Mon, Jan 23, 2023 at 04:30:03PM +0300, Daniil Tatianin wrote:
On 1/23/23 11:57 AM, David Hildenbrand wrote:
On 20.01.23 14:47, Daniil Tatianin wrote:
This series introduces new
Am 23.01.23 um 08:43 schrieb Philippe Mathieu-Daudé:
On 21/1/23 10:47, Volker Rümelin wrote:
The currently used default playback settings in the ALSA audio
backend are a bit unfortunate. With a few emulated audio devices,
audio playback does not work properly. Here is a short part of
the debug
On 1/24/23 07:20, Joel Stanley wrote:
The model includes aspeed_scu.h but doesn't appear to require it.
Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/misc/aspeed_sdmc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/misc/aspeed_sdmc.c
On 23/01/2023 22.22, Fabiano Rosas wrote:
Thomas Huth writes:
On 23/01/2023 14.32, Fabiano Rosas wrote:
Thomas Huth writes:
On 20/01/2023 20.44, Fabiano Rosas wrote:
These leaks can be avoided:
759 bytes in 61 blocks are still reachable in loss record 56 of 60
at 0x4034744:
Hi
On Tue, Jan 24, 2023 at 7:48 AM Anton Kochkov wrote:
>
> This is necessary for Muon build system compatibility and
> prevents the following error:
>
> meson.build:4:8: error module 'i18n' is unimplemented,
> If you would like to make your build files portable to muon,
> use
translate.c functions use RAMPZ for RAM access. This register
is also used for ROM reads. However, in MCUs with 64k RAM support
RAMPZ is used for ROM only. Therefore when RAMPZ is set,
addressing the RAM becomes incorrect in the emulator.
This patch adds LARGE RAM feature which can be used in
AVR ELPMX instruction (and some others) use three registers to
form long 24-bit address from RAMPZ and two 8-bit registers.
RAMPZ stores shifted 8 bits like ff to simplify address calculation.
This patch fixes full address calculation in function gen_get_addr
by changing the mess in offsets of
Interrupt bit vector has 64 bits, but interrupt vector is found with ctz32
function. This patch replaces it with ctz64.
Signed-off-by: Pavel Dovgalyuk
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/avr/helper.c |4 ++--
1 file changed, 2 insertions(+), 2
This set of patches includes multiple changes for AVR target.
v2 changes:
- fixed instruction translation in icount mode
---
Pavel Dovgalyuk (5):
target/avr: fix long address calculation
target/avr: implement small RAM/large RAM feature
target/avr: fix avr features processing
Icount mode requires correct can_do_io flag management for checking
that IO operations are performed only in the last TB instruction.
This patch sets this flag before every helper which can lead to
virtual hardware access. It enables deterministic execution
in icount mode for AVR.
Signed-off-by:
Bit vector for features has 64 bits. This patch fixes bit shifts in
avr_feature and set_avr_feature functions to be 64-bit too.
Signed-off-by: Pavel Dovgalyuk
Reviewed-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/avr/cpu.h |4 ++--
1
On 24/01/2023 05.31, Akihiko Odaki wrote:
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 958915f227..3b648a89d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2218,6 +2218,8 @@ R: Akihiko Odaki
S:
+ Frediano
Hi Gerd,
>
> Hi,
>
> > Here is the flow of things from the Qemu side:
> > - Call gl_scanout (to update the fd) and gl_draw_async just like
> > in the local display case.
>
> Ok.
>
> > - Additionally, create an update with the cmd set to QXL_CMD_DRAW
> > to trigger the
The model includes aspeed_scu.h but doesn't appear to require it.
Signed-off-by: Joel Stanley
---
hw/misc/aspeed_sdmc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index d2a3931033b3..abb272793393 100644
--- a/hw/misc/aspeed_sdmc.c
+++
On 2023/01/16 17:01, Jason Wang wrote:
On Sat, Jan 14, 2023 at 12:10 PM Akihiko Odaki wrote:
Based-on: <20230114035919.35251-1-akihiko.od...@daynix.com>
([PATCH 00/19] e1000x cleanups (preliminary for IGB))
igb is a family of Intel's gigabit ethernet controllers. This series implements
82576
This automates ethtool tests for igb registers, interrupts, etc.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 1 +
.../org.centos/stream/8/x86_64/test-avocado | 1 +
tests/avocado/igb.py | 38 +++
3 files changed,
Currently igb functions identically with e1000e.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
---
hw/net/Kconfig | 5 +
hw/net/meson.build | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
index
e1000e understands ethernet header so fabricate something convincing.
Signed-off-by: Akihiko Odaki
---
tests/qtest/e1000e-test.c | 17 +++--
tests/qtest/libqos/e1000e.h | 2 ++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/tests/qtest/e1000e-test.c
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 1 +
docs/system/device-emulation.rst | 1 +
docs/system/devices/igb.rst | 71
3 files changed, 73 insertions(+)
create mode 100644 docs/system/devices/igb.rst
diff --git a/MAINTAINERS
Start off igb test implementation by copying e1000e code first as igb
resembles e1000e.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 2 +
tests/qtest/igb-test.c | 242 +++
tests/qtest/libqos/igb.c | 226
Some definitions in the header files are invalid for igb so extract
them to new header files to keep igb from referring to them.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 1 +
Signed-off-by: Akihiko Odaki
---
tests/qtest/fuzz/generic_fuzz_configs.h | 5 +
tests/qtest/igb-test.c | 67 ++--
tests/qtest/libqos/igb.c| 139 +---
tests/qtest/libqos/meson.build | 1 +
tests/qtest/meson.build
They will be useful for igb testing.
Signed-off-by: Akihiko Odaki
---
tests/qtest/libqos/e1000e.c | 12
tests/qtest/libqos/e1000e.h | 12
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c
index
Rename identifiers of definitions which will be modified later for igb.
This will also allow to build igb along with e1000e.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
---
hw/net/igb.c| 368 +-
hw/net/igb_common.h |6 +-
Based-on: <20230124043143.5515-1-akihiko.od...@daynix.com>
([PATCH v2 00/26] e1000x cleanups (preliminary for IGB))
igb is a family of Intel's gigabit ethernet controllers. This series implements
82576 emulation in particular. You can see the last patch for the documentation.
Note that there is
Start off igb implementation by copying e1000e code first as igb
resembles e1000e.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
---
MAINTAINERS |5 +
hw/net/igb.c| 727 +
hw/net/igb_common.h | 102 ++
hw/net/igb_core.c
igb can use this function to change its behavior depending on the
number of virtual functions currently enabled.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/pcie_sriov.c | 5 +
Expose the ethernet header so that igb can utilize it to perform the
internal routing among its SR-IOV functions.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
---
hw/net/net_tx_pkt.c | 6 ++
hw/net/net_tx_pkt.h | 8
2 files changed, 14
The definitions of SW Semaphore Register were copied from:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000e/defines.h?h=v6.0.9#n374
Signed-off-by: Akihiko Odaki
---
hw/net/e1000_regs.h | 7 +++
hw/net/e1000e_core.c | 49
The new function qemu_get_using_vnet_hdr() allows to automatically
determine if virtio-net header is used.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e_core.c | 3 +--
hw/net/net_tx_pkt.c | 19 ++-
hw/net/net_tx_pkt.h | 3 +--
hw/net/vmxnet3.c | 6 ++
4 files
e1000x_is_vlan_packet() had a pointer to uint8_t as a parameter, but
it does not have to be uint8_t. Change the type to void *.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000x_common.c | 2 +-
hw/net/e1000x_common.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
hw/net/mii.h provides common definitions for MII.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 86 ++--
hw/net/e1000_regs.h| 46
hw/net/e1000e.c| 1 +
hw/net/e1000e_core.c | 99
This is part of recent efforts of refactoring e1000 and e1000e.
DeviceClass's reset member is deprecated so migrate to ResettableClass.
There is no behavioral difference.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 13
I want to know to be notified when there is a new change for e1000e
as e1000e is similar to igb and such a change may also be applicable for
igb.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Before this change, e1000e_write_packet_to_guest() allocated the
receive descriptor buffer as an array of uint8_t. This does not ensure
the buffer is sufficiently aligned.
Introduce e1000_rx_desc_union type, a union type of all receive
descriptor types to correct this.
Signed-off-by: Akihiko
The definitions for E1000_VFTA_ENTRY_SHIFT, E1000_VFTA_ENTRY_MASK, and
E1000_VFTA_ENTRY_BIT_SHIFT_MASK were copied from:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000/e1000_hw.h?h=v6.0.9#n306
The definitions for E1000_NUM_UNICAST,
igb implementation first starts off by copying e1000e code. Correct the
code style before that.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 41
hw/net/e1000e.c| 72 ++--
hw/net/e1000e_core.c
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 958915f227..3b648a89d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2218,6 +2218,8 @@ R: Akihiko Odaki
S: Maintained
F: hw/net/e1000e*
F:
filter-dump specifiees Ethernet as PCAP LinkType, which does not expect
virtio-net header. Having virtio-net header in such PCAP file breaks
PCAP unconsumable. Unfortunately currently there is no LinkType for
virtio-net so for now strip virtio-net header to convert the output to
Ethernet.
When virtio-net header is not set, net_rx_pkt_get_vhdr() returns
zero-filled virtio_net_hdr, which is actually valid. In fact, tap device
uses zero-filled virtio_net_hdr when virtio-net header is not provided
by the peer. Therefore, we can just remove net_rx_pkt_has_virt_hdr() and
always assume
When a register has effective bits fewer than their width, the old code
inconsistently masked when writing or reading. Make the code consistent
by always masking when writing, and remove some code duplication.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e_core.c | 94
e1000e didn't perform software segmentation for loopback if virtio-net
header is enabled, which is wrong.
To fix the problem, introduce net_tx_pkt_send_custom(), which allows the
caller to specify whether offloading should be assumed or not.
net_tx_pkt_send_custom() also allows the caller to
There was no proper implementation of TCP segmentation before this
change, and net_tx_pkt relied solely on IPv4 fragmentation. Not only
this is not aligned with the specification, but it also resulted in
corrupted IPv6 packets.
This is particularly problematic for the igb, a new proposed device
When a register has effective bits fewer than their width, the old code
inconsistently masked when writing or reading. Make the code consistent
by always masking when writing, and remove some code duplication.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000.c | 84
Use memcpy instead of memmove to initialize registers. The initial
register templates and register table instances will never overlap.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index
They are duplicate of running throttling timer flags and incomplete as
the flags are not cleared when the interrupts are fired or the device is
reset.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e.c | 5 ++---
hw/net/e1000e_core.c | 19 +++
hw/net/e1000e_core.h | 2 --
e1000e_write_packet_to_guest() passes the reference of variable ba as a
pointer to an array, and that pointer indirection is just unnecessary;
all functions which uses the passed reference performs no pointer
operation on the pointer and they simply dereference the passed
pointer. Remove the extra
This change makes e1000e reset more things when software reset was
triggered. Some registers are exempted from software reset in the
datasheet and this change also implements the behavior accordingly.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e_core.c | 24 +++-
1 file
Use memcpy instead of memmove to initialize registers. The initial
register templates and register table instances will never overlap.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e_core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/e1000e_core.c
hw/net/mii.h provides common definitions for MII.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/fsl_etsec/etsec.c | 11 ++-
hw/net/fsl_etsec/etsec.h | 17 -
hw/net/fsl_etsec/miim.c | 5 +++--
include/hw/net/mii.h | 1 +
4 files
We are adding a new device named igb, yet another Intel NIC. As the new
implementation derives from e1000e, overhaul e1000e implementation first.
e1000 has many commonalities with e1000e so we also apply the corresponding
changes to the device if possible.
This was spun off from:
net_tx_pkt_build_vheader() inspects TCP header but had no check for
the header size, resulting in an undefined behavior. Check the header
size and drop the packet if the header is too small.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e_core.c | 19 ++-
hw/net/net_tx_pkt.c |
The definitions will be used by igb.
Signed-off-by: Akihiko Odaki
---
include/hw/net/mii.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
index 4ae4dcce7e..c6a767a49a 100644
--- a/include/hw/net/mii.h
+++
This keeps Windows driver 12.18.9.23 from generating an event with ID
30. The description of the event is as follows:
> Intel(R) 82574L Gigabit Network Connection
> PROBLEM: The network adapter is configured for auto-negotiation but
> the link partner is not. This may result in a duplex
This is part of recent efforts of refactoring e1000 and e1000e.
DeviceClass's reset member is deprecated so migrate to ResettableClass.
There is no behavioral difference.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000e.c | 10
This is necessary for Muon build system compatibility and
prevents the following error:
meson.build:4:8: error module 'i18n' is unimplemented,
If you would like to make your build files portable to muon,
use `import('i18n', required: false)`,
and then check the .found() method before use.
han
# bad: [00b1faea41d283e931256aa78aa975a369ec3ae6] Merge tag
'pull-target-arm-20230123' of https://git.linaro.org/people/pmaydell/qemu-arm
into staging
# good: [886fb67020e32ce6a2cf7049c6f017acf1f0d69a] Merge tag
'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm
into staging
From: Rui Wang
diff:
Imm Before After
addi.w rd, zero, 0 addi.w rd, zero, 0
lu52i.d rd, zero, 0
f800lu12i.w rd, -1 addi.w rd, zero, -2048
ori rd, rd, 2048
Adjust the constraints to allow any int32_t for immediate
addition. Split immediate adds into addu16i + addi, which
covers quite a lot of the immediate space. For the hole in
the middle, load the constant into TMP0 instead.
Reviewed-by: WANG Xuerui
Signed-off-by: Richard Henderson
---
Regenerate with ADDU16I included:
$ cd loongarch-opcodes/scripts/go
$ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc
Reviewed-by: WANG Xuerui
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-insn-defs.c.inc | 10
Signed-off-by: Richard Henderson
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20220729172141.1789105-2-richard.hender...@linaro.org>
---
common-user/host/ppc/safe-syscall.inc.S | 107
1 file changed, 107 insertions(+)
create mode 100644
Second try's the charm today, right?
r~
The following changes since commit 00b1faea41d283e931256aa78aa975a369ec3ae6:
Merge tag 'pull-target-arm-20230123' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-01-23
13:40:28 +)
are available in the Git repository
The old implementation replaces two insns, swapping between
b
nop
and
pcaddu18i tmp,
jirl zero, tmp, & 0x
There is a race condition in which a thread could be stopped at
the jirl, i.e. with the top of the address loaded, and when
restarted we
This commit re-enables ppc32 as a linux-user host,
as existance of the directory is noted by configure.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1097
Signed-off-by: Richard Henderson
Reviewed-by: Daniel Henrique Barboza
Message-Id:
Although we still can't use ldrd and strd for all operations,
increase the chances by getting the register allocation correct.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-con-set.h | 7 ---
tcg/arm/tcg-target-con-str.h | 2 ++
tcg/arm/tcg-target.c.inc | 28
Print both the raw field and the resolved pc-relative
address, as we do for branches.
Reviewed-by: WANG Xuerui
Signed-off-by: Richard Henderson
---
target/loongarch/disas.c | 37 +
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git
Take the w^x split into account when computing the
pc-relative distance to an absolute pointer.
Reviewed-by: WANG Xuerui
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Split out a helper function, tcg_out_setcond_int, which
does not always produce the complete boolean result, but
returns a set of flags to do so.
Accept all int32_t as constant input, so that LE/GT can
adjust the constant to LT.
Reviewed-by: WANG Xuerui
Signed-off-by: Richard Henderson
---
Marking helpers __attribute__((noinline)) prevents an issue
with GCC's ipa-split pass under --enable-lto.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1454
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Idan Horowitz
Signed-off-by: Richard Henderson
---
include/exec/helper-proto.h
While jirl shares the same instruction format as bne etc,
it is not assembled the same. In particular, rd is printed
first not second and the immediate is not pc-relative.
Decode into the arg_rr_i structure, which prints correctly.
This changes the "offs" member to "imm", to update translate.
Reuse the decodetree based disassembler from
target/loongarch/ for tcg/loongarch64/.
The generation of decode-insns.c.inc into ./libcommon.fa.p/ could
eventually result in conflict, if any other host requires the same
trick, but this is good enough for now.
Reviewed-by: WANG Xuerui
Reviewed-by:
We have a test for one of TCG_TARGET_HAS_mulu2_i32 or
TCG_TARGET_HAS_muluh_i32 being defined, but the test
became non-functional when we changed to always define
all of these macros.
Replace this with a build-time test in tcg_gen_mulu2_i32.
Fixes: 25c4d9cc845 ("tcg: Always define all of the
Reviewed-by: WANG Xuerui
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.h | 4 ++--
tcg/loongarch64/tcg-target.c.inc | 33
3 files changed, 36 insertions(+), 2 deletions(-)
diff --git
> From: Alistair Francis
>
> If the CSRs and CSR instructions are disabled because the Zicsr
> extension isn't enabled then we want to make sure we don't run any CSR
> instructions in the boot ROM.
>
> This patches removes the CSR instructions from the reset-vec if the
> extension isn't enabled.
On Tue, 24 Jan 2023, Howard Spoelstra wrote:
From a Mac OS guest perspective, via=cuda is needed for Mac OS 9.0.4 due to
the 2 usb devices (mouse/kbd) issue. And for 10.0/10.1 (my guess would be
that these suffer the same usb issue)
The real powermac3,1 AGP has no adb.
And do these OSes run on
On Mon, 23 Jan 2023 at 14:54, Stefan Hajnoczi wrote:
>
> On Mon, Jan 23, 2023 at 06:27:23PM +, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Sun, Jan 22, 2023 at 06:09:40PM +0200, Anton Kuchin wrote:
> > > >
> > > > On 22/01/2023 16:46, Michael S.
On Tue, Jan 24, 2023 at 11:24 AM Bin Meng wrote:
>
> On Mon, Jan 23, 2023 at 11:58 AM Alistair Francis
> wrote:
> >
> > From: Alistair Francis
> >
> > If the CSRs and CSR instructions are disabled because the Zicsr
> > extension isn't enabled then we want to make sure we don't run any CSR
> >
On Thu, Jan 19, 2023, Isaku Yamahata wrote:
> On Thu, Jan 19, 2023 at 03:25:08PM +,
> Sean Christopherson wrote:
>
> > On Thu, Jan 19, 2023, Isaku Yamahata wrote:
> > > On Sat, Jan 14, 2023 at 12:37:59AM +,
> > > Sean Christopherson wrote:
> > >
> > > > On Fri, Dec 02, 2022, Chao Peng
On Mon, 23 Jan 2023, Mark Cave-Ayland wrote:
On 22/01/2023 22:07, BALATON Zoltan wrote:
On Sun, 22 Jan 2023, Mark Cave-Ayland wrote:
On 12/01/2023 23:51, BALATON Zoltan wrote:
On Thu, 12 Jan 2023, Howard Spoelstra wrote:
On Wed, Jan 11, 2023 at 1:15 AM BALATON Zoltan
wrote:
On Tue, 10 Jan
On Mon, Jan 23, 2023 at 11:58 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> If the CSRs and CSR instructions are disabled because the Zicsr
> extension isn't enabled then we want to make sure we don't run any CSR
> instructions in the boot ROM.
>
> This patches removes the CSR
On Fri, Jan 20, 2023 at 11:01 PM Anup Patel wrote:
>
> This series mainly includes fixes discovered while developing nested
> virtualization running on QEMU.
>
> These patches can also be found in the riscv_nested_fixes_v3 branch at:
> https://github.com/avpatel/qemu.git
>
> Changes since v2:
>
On Mon, Jan 23, 2023 at 7:09 PM Alexandre Ghiti wrote:
>
> Currently, the max satp mode is set with the only constraint that it must be
> implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constraint: what the hw is
> actually capable of,
On Mon, 23 Jan 2023, Mark Cave-Ayland wrote:
On 22/01/2023 21:48, BALATON Zoltan wrote:
On Sun, 22 Jan 2023, Mark Cave-Ayland wrote:
On 11/01/2023 00:36, BALATON Zoltan wrote:
On Tue, 10 Jan 2023, Mark Cave-Ayland wrote:
On 04/01/2023 21:59, BALATON Zoltan wrote:
Secondly it's not clear to
On Mon, Jan 23, 2023 at 7:08 PM Alexandre Ghiti wrote:
>
> The 'mmu-type' should reflect what the hardware is capable of so use the
> new satp_mode field in RISCVCPUConfig to do that.
>
> Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c | 19
On Wed, Jan 18, 2023 at 3:03 AM Marc-André Lureau
wrote:
>
> Hi
>
> On Wed, Jan 18, 2023 at 2:36 AM John Snow wrote:
> >
> > On Wed, Jan 11, 2023 at 3:01 AM wrote:
> > >
> > > From: Marc-André Lureau
> > >
> > > When no monitor address is given, establish the QMP communication through
> > > a
On 1/23/23 02:53, Peter Maydell wrote:
On Fri, 6 Jan 2023 at 19:45, Richard Henderson
wrote:
Do not encode the pointer as a constant in the opcode stream.
This pointer is specific to the cpu that first generated the
translation, which runs into problems with both hot-pluggable
cpus and
On Mon, 23 Jan 2023, Mark Cave-Ayland wrote:
On 22/01/2023 22:16, BALATON Zoltan wrote:
The problem you are ultimately trying to solve though is that OpenBIOS is
loading the NDRV for all VGA PCI devices, so why not just fix
drivers/vga.fs so that the NDRV is loaded only for the QEMU VGA
With FEAT_RME, there are four physical address spaces.
For now, just define the symbols, and mention them in
the same spots as the other Phys indexes in ptw.c.
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 17 +++--
target/arm/ptw.c
Add input and output space members to S1Translate.
Set and adjust them in S1_ptw_translate, and the
various points at which we drop secure state.
Initialize the space in get_phys_addr; for now
leave get_phys_addr_with_secure considering only
secure vs non-secure spaces.
Signed-off-by: Richard
It will be helpful to have ARMMMUIdx_Phys_* to be in the same
relative order as ARMSecuritySpace enumerators. This requires
the adjustment to the nstable check. While there, check for being
in secure state rather than rely on clearing the low bit making
no change to non-secure state.
With Realm security state, bit 55 of a block or page descriptor during
the stage2 walk becomes the NS bit; during the stage1 walk the bit 5
NS bit is RES0. With Root security state, bit 11 of the block or page
descriptor during the stage1 walk becomes the NSE bit.
Rather than collecting an NS
On Mon, Jan 23, 2023 at 7:06 PM Alexandre Ghiti wrote:
>
> This array is actually used as a boolean so swap its current char type
> to a boolean and at the same time, change the type of validate_vm to
> bool since it returns valid_vm_1_10_[32|64].
>
> Signed-off-by: Alexandre Ghiti
Reviewed-by:
Add a cpu property to set GPCCR_EL3.L0GPTSZ, for testing
various possible configurations.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
On Fri, Jan 20, 2023 at 11:01 PM Anup Patel wrote:
>
> We should call decode_save_opc() for all relevant instructions which
> can potentially generate a virtual instruction fault or a guest page
> fault because generating transformed instruction upon guest page fault
> expects opcode to be
Do not provide a fast-path for physical addresses,
as those will need to be validated for GPC.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 35 ++-
1 file changed, 14 insertions(+), 21 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
While Root and Realm may read and write data from other spaces,
neither may execute from other pa spaces.
This happens for Stage1 EL3, EL2, EL2&0, but stage2 EL1&0.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 66 ++--
1 file changed, 58
The function takes the fields as filled in by
the Arm ARM pseudocode for TakeGPCException.
Signed-off-by: Richard Henderson
---
target/arm/syndrome.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index 73df5e3793..3fa926d115 100644
Handle GPC Fault types in arm_deliver_fault, reporting as
either a GPC exception at EL3, or falling through to insn
or data aborts at various exception levels.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 +
target/arm/internals.h | 27
target/arm/helper.c
Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF
to be set, and invalidate TLBs when NSE changes.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 5 +++--
target/arm/helper.c | 10 --
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git
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