[PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault

decode_save_opc() will not work for generate_exception(), since 0 is passed to riscv_raise_exception() as pc in helper_raise_exception(), and bins will not be restored in this case. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_rvh.c.inc | 2 ++ 1 file

[PATCH v11 2/3] tpm: Extend common APIs to support TPM TIS I2C

From: Ninad Palsule Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. This commit includes changes for the common code. - Added support for the new checksum registers which are required for the I2C support. The checksum

[PATCH v11 1/3] docs: Add support for TPM devices over I2C bus

From: Ninad Palsule This is a documentation change for I2C TPM device support. Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. Signed-off-by: Ninad Palsule Reviewed-by: Stefan Berger Reviewed-by: Cédric Le Goater

[PATCH v11 0/3] Add support for TPM devices over I2C bus

Hello, Incorporated review comments from Stefan. Please review. This drop adds support for the TPM devices attached to the I2C bus. It only supports the TPM2 protocol. You need to run it with the external TPM emulator like swtpm. I have tested it with swtpm. I have refered to the work done by

[PATCH v11 3/3] tpm: Add support for TPM device over I2C bus

From: Ninad Palsule Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. I2C model only supports TPM2 protocol. This commit includes changes for the common code. - Added I2C emulation model. Logic was added in the model to

Re: [PATCH v3] linux-user,bsd-user: preserve incoming order of environment variables in the target

On Wed, Mar 29, 2023, 9:00 AM Andreas Schwab wrote: > Do not reverse the order of environment variables in the target environ > array relative to the incoming environ order. Some testsuites depend on a > specific order, even though it is not defined by any standard. > > Signed-off-by: Andreas

Re: [PATCH v3 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data

On 2023/3/30 01:28, Daniel Henrique Barboza wrote: We don't have MISA extensions in isa_edata_arr[] anymore. Remove the redundant 'multi_letter' field from isa_ext_data. Suggested-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li

Re: [PATCH v2 5/5] target/riscv: Add pointer mask support for instruction fetch

On 2023/3/30 00:36, Richard Henderson wrote: On 3/28/23 20:23, Weiwei Li wrote: Transform the fetch address in cpu_get_tb_cpu_state() when pointer mask for instruction is enabled. Enable PC-relative translation when J is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---  

Re: [PATCH v2 4/5] target/riscv: Add support for PC-relative translation

On 2023/3/30 00:27, Richard Henderson wrote: On 3/28/23 20:23, Weiwei Li wrote:   static bool trans_auipc(DisasContext *ctx, arg_auipc *a)   { -    gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next); +    assert(ctx->pc_save != -1); +    if (tb_cflags(ctx->base.tb) & CF_PCREL) { +   

Re: [PATCH v2 3/5] target/riscv: Sync cpu_pc before update badaddr

On 2023/3/29 23:33, Richard Henderson wrote: On 3/28/23 20:23, Weiwei Li wrote: We should sync cpu_pc before storing it into badaddr when mis-aligned exception is triggered. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---   target/riscv/insn_trans/trans_rvi.c.inc | 1 +  

[RFC PATCH 3/5] ebpf: Added declaration/initialization routines.

Now, the binary objects may be retrieved by id/name. It would require for future qmp commands that may require specific eBPF blob. Signed-off-by: Andrew Melnychenko --- ebpf/ebpf.c | 48 ebpf/ebpf.h | 25 +

[RFC PATCH 2/5] virtio-net: Added property to load eBPF RSS with fds.

eBPF RSS program and maps may now be passed during initialization. Initially was implemented for libvirt to launch qemu without permissions, and initialized eBPF program through the helper. Signed-off-by: Andrew Melnychenko --- hw/net/virtio-net.c| 77

[RFC PATCH 5/5] ebpf: Updated eBPF program and skeleton.

Updated section name, so libbpf should init/gues proper program type without specifications during open/load. Signed-off-by: Andrew Melnychenko --- ebpf/rss.bpf.skeleton.h | 1469 --- tools/ebpf/rss.bpf.c|2 +- 2 files changed, 741 insertions(+), 730

[RFC PATCH 4/5] qmp: Added new command to retrieve eBPF blob.

Added command "request-ebpf". This command returns eBPF program encoded base64. The program taken from the skeleton and essentially is an ELF object that can be loaded in the future with libbpf. Signed-off-by: Andrew Melnychenko --- monitor/qmp-cmds.c | 17 + qapi/misc.json

[RFC PATCH 1/5] ebpf: Added eBPF initialization by fds and map update.

Changed eBPF map updates through mmaped array. Mmaped arrays provide direct access to map data. It should omit using bpf_map_update_elem() call, which may require capabilities that are not present. Signed-off-by: Andrew Melnychenko --- ebpf/ebpf_rss-stub.c | 6 +++ ebpf/ebpf_rss.c | 120

[RFC PATCH 0/4] eBPF RSS through QMP support.

This series of patches provides the ability to retrieve eBPF program through qmp, so management application may load bpf blob with proper capabilities. Now, virtio-net devices can accept eBPF programs and maps through properties as external file descriptors. Access to the eBPF map is direct

Re: Audio playback speed issue on sam460ex and pegasos2

On Wed, 29 Mar 2023, Volker Rümelin wrote: Am 29.03.23 um 21:20 schrieb BALATON Zoltan: On Tue, 28 Mar 2023, Volker Rümelin wrote: it seems your Mac uses a 48kHz sample rate, although QEMU requested a 44.1kHz sample rate. Could you add -audiodev coreaudio,id=audio0,out.frequency=48000 to your

Re: Audio playback speed issue on sam460ex and pegasos2

Am 29.03.23 um 21:20 schrieb BALATON Zoltan: On Tue, 28 Mar 2023, Volker Rümelin wrote: it seems your Mac uses a 48kHz sample rate, although QEMU requested a 44.1kHz sample rate. Could you add -audiodev coreaudio,id=audio0,out.frequency=48000 to your command line and test if the playback

Re: [RFC PATCH 2/2] virtio-gpu: Add an option to connect all outputs on startup

On 2023/03/08 11:25, Damian Hobson-Garcia wrote: When multiple outputs are enabled using the "max_outputs" attribute, only the first connector appears as "Connected" in the guest DRM device. Additional connectors must be enabled from the host side UI frontend before they are usable by the

Re: [RFC PATCH] tests/avocado: Test Xen guest support under KVM

Alex Bennée writes: > From: David Woodhouse > > Exercise guests with a few different modes for interrupt delivery. In > particular we want to cover: > > • Xen event channel delivery via GSI to the I/O APIC > • Xen event channel delivery via GSI to the i8259 PIC > • MSIs routed to PIRQ

Re: [PATCH v6 0/9] target/riscv: rework CPU extensions validation

On 3/29/23 17:08, Daniel Henrique Barboza wrote: Hi, This series contains changes proposed by Weiwei Li in v5. All patches are acked. I forgot to mention: this series is based on: "[PATCH v3 00/20] remove MISA ext_N flags from cpu->cfg" Daniel Changes from v5: - patch 9: - remove

[PATCH v6 6/9] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()

Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max != env->misa_mlx. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li ---

[PATCH v6 4/9] target/riscv: add PRIV_VERSION_LATEST

All these generic CPUs are using the latest priv available, at this moment PRIV_VERSION_1_12_0: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll make it easier to update everything

[PATCH v6 5/9] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers

We're doing env->priv_spec validation and assignment at the start of riscv_cpu_realize(), which is fine, but then we're doing a force disable on extensions that aren't compatible with the priv version. This second step is being done too early. The disabled extensions might be re-enabled again in

[PATCH v6 8/9] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()

We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should

[PATCH v6 0/9] target/riscv: rework CPU extensions validation

Hi, This series contains changes proposed by Weiwei Li in v5. All patches are acked. Changes from v5: - patch 9: - remove ext_ifencei setting from rv64_thead_c906_cpu_init() - v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg06740.html Daniel Henrique Barboza (9):

[PATCH v6 7/9] target/riscv/cpu.c: validate extensions before riscv_timer_init()

There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 11 --- 1 file

[PATCH v6 9/9] target/riscv: rework write_misa()

write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Our validation is done with riscv_cpu_validate_set_extensions(), but we need a small tweak first. When enabling RVG we're doing:

[PATCH v6 1/9] target/riscv/cpu.c: add riscv_cpu_validate_v()

The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(), after we've already set some extensions that are dependent on RVV. Let's put it in its own function and do it earlier. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU

[PATCH v6 2/9] target/riscv/cpu.c: remove set_vext_version()

This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/riscv/cpu.c

[PATCH v6 3/9] target/riscv/cpu.c: remove set_priv_version()

The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 29 - 1 file changed, 12 insertions(+), 17 deletions(-) diff --git

Re: Audio playback speed issue on sam460ex and pegasos2

Am 29.03.23 um 14:03 schrieb Rene Engel: After short tests with the command line -audiodev coreaudio,id=audio0,out.frequency=48000 the sound output runs in the correct speed. Tested with one and the same mp3 file under AmigaOs4.1 and MacOs with es1370 and ac97 on Pegasos 2 emulation This

[PATCH v3 20/20] target/riscv/cpu.c: redesign register_cpu_props()

The function is now a no-op for all cpu_init() callers that are setting a non-zero misa value in set_misa(), since it's no longer used to sync cpu->cfg props with env->misa_ext bits. Remove it in those cases. While we're at it, rename the function to match what it's actually doing: create user

[PATCH v3 11/20] target/riscv: remove cpu->cfg.ext_m

Create a new "m" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are replaced with riscv_has_ext(env, RVM). Remove the old "m" property and 'ext_m' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 19/20] target/riscv: add RVG and remove cpu->cfg.ext_g

We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it the same way we did with the others: create a "g" RISCVCPUMisaExtConfig property, remove the old "g" property, remove all instances of 'cfg.ext_g' and use riscv_has_ext(env, RVG). The caveat is that we don't have RVG, so add

[PATCH v3 16/20] target/riscv: remove cpu->cfg.ext_v

Create a new "v" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are replaced with riscv_has_ext(env, RVV). Remove the old "v" property and 'ext_v' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 02/20] target/riscv: remove MISA properties from isa_edata_arr[]

The code that disables extensions if there's a priv version mismatch uses cpu->cfg.ext_N properties to do its job. We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split the MISA related verifications in a new function, removing it from isa_edata_arr[]. We're also erroring it out

[PATCH v3 09/20] target/riscv: remove cpu->cfg.ext_i

Create a new "i" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are replaced with riscv_has_ext(env, RVI). Remove the old "i" property and 'ext_i' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 10/20] target/riscv: remove cpu->cfg.ext_e

Create a new "e" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are replaced with riscv_has_ext(env, RVE). Remove the old "e" property and 'ext_e' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 12/20] target/riscv: remove cpu->cfg.ext_s

Create a new "s" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are replaced with riscv_has_ext(env, RVS). Remove the old "s" property and 'ext_s' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data

We don't have MISA extensions in isa_edata_arr[] anymore. Remove the redundant 'multi_letter' field from isa_ext_data. Suggested-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 118 ++--- 1 file changed, 58 insertions(+), 60

[PATCH v3 13/20] target/riscv: remove cpu->cfg.ext_u

Create a new "u" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are replaced with riscv_has_ext(env, RVU). Remove the old "u" property and 'ext_u' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 00/20] remove MISA ext_N flags from cpu->cfg,

Hi, This new version has a new patch (3) that removes the 'multi_letter' attribute from isa_ext_data that became redundant after the changes made in patch 2. The change was proposed by Weiwei Li in the v2. All patches but patch 3 are acked. Changes from v2: - patch 3 (new) - remove

[PATCH v3 07/20] target/riscv: remove cpu->cfg.ext_d

Create a new "d" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are replaced with riscv_has_ext(env, RVD). Remove the old "d" property and 'ext_d' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 15/20] target/riscv: remove cpu->cfg.ext_j

Create a new "j" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are replaced with riscv_has_ext(env, RVJ). Remove the old "j" property and 'ext_j' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 14/20] target/riscv: remove cpu->cfg.ext_h

Create a new "h" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are replaced with riscv_has_ext(env, RVH). Remove the old "h" property and 'ext_h' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 17/20] target/riscv: remove riscv_cpu_sync_misa_cfg()

This function was created to move the sync between cpu->cfg.ext_N bit changes to env->misa_ext* from the validation step to an ealier step, giving us a guarantee that we could use either cpu->cfg.ext_N or riscv_has_ext(env,N) in the validation. We don't have any cpu->cfg.ext_N left that has an

[PATCH v3 18/20] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()

This CPU is enabling G via cfg.ext_g and, at the same time, setting IMAFD in set_misa() and cfg.ext_icsr. riscv_cpu_validate_set_extensions() is already doing that, so there's no need for cpu_init() setups to worry about setting G and its extensions. Signed-off-by: Daniel Henrique Barboza

[PATCH v3 06/20] target/riscv: remove cpu->cfg.ext_c

Create a new "c" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are replaced with riscv_has_ext(env, RVC). Remove the old "c" property and 'ext_c' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 05/20] target/riscv: remove cpu->cfg.ext_a

Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 08/20] target/riscv: remove cpu->cfg.ext_f

Create a new "f" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are replaced with riscv_has_ext(env, RVF). Remove the old "f" property and 'ext_f' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 04/20] target/riscv: introduce riscv_cpu_add_misa_properties()

Ever since RISCVCPUConfig got introduced users are able to set CPU extensions in the command line. User settings are reflected in the cpu->cfg object for later use. These properties are used in the target/riscv/cpu.c code, most notably in riscv_cpu_validate_set_extensions(), where most of our

[PATCH v3 01/20] target/riscv: sync env->misa_ext* with cpu->cfg in realize()

When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N properties updated. The same can't be said about env->misa_ext*, since the user might enable/disable MISA extensions in the command line, and env->misa_ext* won't caught these changes. The current solution is to sync

Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

On 29/3/23 18:48, Rob Landley wrote: On 3/29/23 11:07, Philippe Mathieu-Daudé wrote: On 29/3/23 18:09, Rob Landley wrote: On 3/28/23 12:02, Philippe Mathieu-Daudé wrote: On 20/3/23 17:58, Nathan Chancellor wrote: On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote: On

Re: [PATCH] tests/vm: use the default system python for NetBSD

Daniel P. Berrangé writes: > Currently our NetBSD VM recipe requests instal of the python37 package > and explicitly tells QEMU to use that version of python. Since the > NetBSD base ISO was updated to version 9.3 though, the default system > python version is 3.9 which is sufficiently new for

Re: [PATCH for 8.0] tests/qemu-iotests: explicitly invoke 'check' via 'python'

Daniel P. Berrangé writes: > The 'check' script will use "#!/usr/bin/env python3" by default > to locate python, but this doesn't work in distros which lack a > bare 'python3' binary like NetBSD. > > We need to explicitly invoke 'check' by referring to the 'python' > variable in meson, which

Re: [PATCH] gdbstub: Only build libgdb_user.fa / libgdb_softmmu.fa if necessary

Philippe Mathieu-Daudé writes: > It is pointless to build libgdb_user.fa in a system-only build > (or libgdb_softmmu.fa in a user-only build). Besides, in some > restricted build configurations, some APIs might be restricted / > not available. Example in a KVM-only builds where TCG is

Re: [PATCH 2/2] hw/acpi: i386: bump MADT to revision 5

On Wed, Mar 29, 2023 at 08:19:22AM -0500, Eric DeVolder wrote: > > > On 3/29/23 08:16, Eric DeVolder wrote: > > > > > > On 3/29/23 00:03, Michael S. Tsirkin wrote: > > > On Tue, Mar 28, 2023 at 11:59:26AM -0400, Eric DeVolder wrote: > > > > Currently i386 QEMU generates MADT revision 3, and

Re: [PATCH 0/2] hw/acpi: bump MADT to revision 5

On Wed, Mar 29, 2023 at 08:14:37AM -0500, Eric DeVolder wrote: > > > On 3/29/23 00:19, Michael S. Tsirkin wrote: > > Hmm I don't think we can reasonably make such a change for 8.0. > > Seems too risky. > > Also, I feel we want to have an internal (with "x-" prefix") flag to > > revert to old

RE: [PATCH] Use hexagon toolchain version 16.0.0

> -Original Message- > From: Alex Bennée > Sent: Wednesday, March 29, 2023 10:34 AM > To: Marco Liebel (QUIC) > Cc: Taylor Simpson ; qemu-devel@nongnu.org > Subject: Re: [PATCH] Use hexagon toolchain version 16.0.0 > > Marco Liebel writes: > > > Signed-off-by: Marco Liebel > > ---

Re: [PATCH] gdbstub: Only build libgdb_user.fa / libgdb_softmmu.fa if necessary

On 3/29/23 09:18, Philippe Mathieu-Daudé wrote: It is pointless to build libgdb_user.fa in a system-only build (or libgdb_softmmu.fa in a user-only build). Besides, in some restricted build configurations, some APIs might be restricted / not available. Example in a KVM-only builds where TCG is

Re: [PATCH v2 5/5] target/riscv: Add pointer mask support for instruction fetch

On 3/28/23 20:23, Weiwei Li wrote: Transform the fetch address in cpu_get_tb_cpu_state() when pointer mask for instruction is enabled. Enable PC-relative translation when J is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c| 4

Re: [PATCH] Use hexagon toolchain version 16.0.0

Marco Liebel writes: > Signed-off-by: Marco Liebel > --- > tests/docker/dockerfiles/debian-hexagon-cross.docker | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker >

Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

On 3/29/23 11:07, Philippe Mathieu-Daudé wrote: > On 29/3/23 18:09, Rob Landley wrote: >> On 3/28/23 12:02, Philippe Mathieu-Daudé wrote: >>> On 20/3/23 17:58, Nathan Chancellor wrote: On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote: > On 23/2/23 17:19, Jiaxun

Re: [PATCH v2 4/5] target/riscv: Add support for PC-relative translation

On 3/28/23 20:23, Weiwei Li wrote: static bool trans_auipc(DisasContext *ctx, arg_auipc *a) { -gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next); +assert(ctx->pc_save != -1); +if (tb_cflags(ctx->base.tb) & CF_PCREL) { +TCGv target_pc = tcg_temp_new(); dest_gpr(s,

Re: stat64 wrong on sparc64 user

Le 28/03/2023 à 14:22, Luca Bonissi a écrit : On 28/03/23 13:55, Thomas Huth wrote: On 28/03/2023 13.48, Luca Bonissi wrote: --- qemu-20230327/linux-user/syscall_defs.h    2023-03-27 15:41:42.0 +0200 +++ qemu-20230327/linux-user/syscall_defs.h.new    2023-03-27 21:43:25.615115126

[PATCH] gdbstub: Only build libgdb_user.fa / libgdb_softmmu.fa if necessary

It is pointless to build libgdb_user.fa in a system-only build (or libgdb_softmmu.fa in a user-only build). Besides, in some restricted build configurations, some APIs might be restricted / not available. Example in a KVM-only builds where TCG is disabled: $ ninja qemu-system-x86_64 [99/2187]

Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

On 3/29/23 03:55, Thomas Huth wrote: > On 28/03/2023 19.02, Philippe Mathieu-Daudé wrote: >> On 20/3/23 17:58, Nathan Chancellor wrote: >>> On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote: On 23/2/23 17:19, Jiaxun Yang wrote: > 145e2198d749 ("hw/mips/gt64xxx_pci:

Re: [PATCH v3] linux-user, bsd-user: preserve incoming order of environment variables in the target

On 29/3/23 17:00, Andreas Schwab wrote: Do not reverse the order of environment variables in the target environ array relative to the incoming environ order. Some testsuites depend on a specific order, even though it is not defined by any standard. Signed-off-by: Andreas Schwab ---

Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

On 29/3/23 18:09, Rob Landley wrote: On 3/28/23 12:02, Philippe Mathieu-Daudé wrote: On 20/3/23 17:58, Nathan Chancellor wrote: On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote: On 23/2/23 17:19, Jiaxun Yang wrote: 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using

Re: [PULL 22/30] gdbstub: only compile gdbstub twice for whole build

On 23/3/23 11:05, Philippe Mathieu-Daudé wrote: Hi Alex, Paolo, On 7/3/23 22:21, Alex Bennée wrote: Now we have removed any target specific bits from the core gdbstub code we only need to build it twice. We have to jump a few meson hoops to manually define the CONFIG_USER_ONLY symbol but it

Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

On 3/28/23 12:02, Philippe Mathieu-Daudé wrote: > On 20/3/23 17:58, Nathan Chancellor wrote: >> On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote: >>> On 23/2/23 17:19, Jiaxun Yang wrote: 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE

Re: [PATCH v2 3/5] target/riscv: Sync cpu_pc before update badaddr

On 3/28/23 20:23, Weiwei Li wrote: We should sync cpu_pc before storing it into badaddr when mis-aligned exception is triggered. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_rvi.c.inc | 1 + target/riscv/translate.c| 1 + 2 files

Re: [PATCH v2 2/5] apic: add support for x2APIC mode

On 3/29/23 21:53, Bui Quang Minh wrote: On 3/28/23 22:58, Bui Quang Minh wrote: On 3/27/23 23:49, David Woodhouse wrote: On Mon, 2023-03-27 at 23:35 +0700, Bui Quang Minh wrote: On 3/27/23 23:22, David Woodhouse wrote: On Mon, 2023-03-27 at 22:45 +0700, Bui Quang Minh wrote: Maybe I'm

Re: [RFC PATCH v2 09/44] target/loongarch: Implement vhaddw/vhsubw

On 3/28/23 20:24, gaosong wrote: I also think we could make use of (__typeof(Vd->E1(0))) instead of separately passing the output type?  It would appear to be less error-prone. I will try this on v3. Consider using local typedefs, e.g. typedef __typeof(Vd->E1(0)) TD; r~

Re: [RFC PATCH v2 05/44] target/loongarch: Implement vadd/vsub

On 3/29/23 02:59, gaosong wrote: 在 2023/3/29 上午3:59, Richard Henderson 写道: On 3/27/23 20:05, Song Gao wrote: +    func(mop, vd_ofs, vj_ofs, vk_ofs, 16, 16); Oh, reading about ASXD and 256-bit vectors makes me wonder if it would be better to plan ahead and have a function, or DisasContext

Re: [PATCH v2 02/19] target/riscv: remove MISA properties from isa_edata_arr[]

On 3/29/23 05:32, liweiwei wrote: On 2023/3/28 06:49, Daniel Henrique Barboza wrote: The code that disables extensions if there's a priv version mismatch uses cpu->cfg.ext_N properties to do its job. We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split the MISA related

[PATCH v3] linux-user, bsd-user: preserve incoming order of environment variables in the target

Do not reverse the order of environment variables in the target environ array relative to the incoming environ order. Some testsuites depend on a specific order, even though it is not defined by any standard. Signed-off-by: Andreas Schwab --- bsd-user/main.c | 10 +-

RE: [PATCH] Use hexagon toolchain version 16.0.0

> -Original Message- > From: qemu-devel-bounces+bcain=quicinc@nongnu.org bounces+bcain=quicinc@nongnu.org> On Behalf Of Marco Liebel > Sent: Wednesday, March 29, 2023 9:21 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Marco Liebel (QUIC) > > Subject: [PATCH] Use

Re: [PATCH] target/riscv: Fix addr type for get_physical_address

On 3/29/23 03:19, Weiwei Li wrote: Function get_physical_address() translates both virtual address and guest physical address, and the latter is 34-bits for Sv32x4. So we should use vaddr type for 'addr' parameter. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---

Re: [PATCH v2 2/5] apic: add support for x2APIC mode

On 3/28/23 22:58, Bui Quang Minh wrote: On 3/27/23 23:49, David Woodhouse wrote: On Mon, 2023-03-27 at 23:35 +0700, Bui Quang Minh wrote: On 3/27/23 23:22, David Woodhouse wrote: On Mon, 2023-03-27 at 22:45 +0700, Bui Quang Minh wrote: Maybe I'm misreading the patch, but to me it looks

Re: [PATCH v2] linux-user: preserve incoming order of environment variables in the target

On Mär 29 2023, Philippe Mathieu-Daudé wrote: > On 29/3/23 16:00, Daniel P. Berrangé wrote: >> On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote: >>> Do not reverse the order of environment variables in the target environ >>> array relative to the incoming environ order. Some

Re: [PATCH v2] linux-user: preserve incoming order of environment variables in the target

On Wed, Mar 29, 2023, 4:00 PM Daniel P. Berrangé wrote: > On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote: > > Do not reverse the order of environment variables in the target environ > > array relative to the incoming environ order. Some testsuites depend on > a > > specific

[PATCH] Use hexagon toolchain version 16.0.0

Signed-off-by: Marco Liebel --- tests/docker/dockerfiles/debian-hexagon-cross.docker | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker b/tests/docker/dockerfiles/debian-hexagon-cross.docker index 5308ccb8fe..b99d99f943

Re: [PATCH 4/5] hw/i2c: pmbus: block uninitialised string reads

On 22/3/23 18:55, Titus Rwantare wrote: Devices models calling pmbus_send_string can't be relied upon to send a non-zero pointer. This logs an error and doesn't segfault. Reviewed-by: Patrick Venture Signed-off-by: Titus Rwantare --- hw/i2c/pmbus_device.c | 7 +++ 1 file changed, 7

Re: [PATCH v2] linux-user: preserve incoming order of environment variables in the target

On Wed, Mar 29, 2023 at 04:04:43PM +0200, Andreas Schwab wrote: > On Mär 29 2023, Daniel P. Berrangé wrote: > > > On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote: > >> Do not reverse the order of environment variables in the target environ > >> array relative to the incoming

Re: [PATCH v2] linux-user: preserve incoming order of environment variables in the target

On Mär 29 2023, Daniel P. Berrangé wrote: > On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote: >> Do not reverse the order of environment variables in the target environ >> array relative to the incoming environ order. Some testsuites depend on a >> specific order, even though it is

[PATCH 3/4] serial-mcb: Add serial via MEN chameleon bus

Add MEN z125 UART over MEN Chameleon Bus emulation. Signed-off-by: Johannes Thumshirn --- hw/char/Kconfig | 6 +++ hw/char/meson.build | 1 + hw/char/serial-mcb.c | 115 +++ 3 files changed, 122 insertions(+) create mode 100644

[PATCH 2/4] Add MEN Chameleon Bus via PCI carrier

Add PCI based MEN Chameleon Bus carrier emulation. Signed-off-by: Johannes Thumshirn --- hw/mcb/Kconfig | 6 + hw/mcb/mcb-pci.c | 307 + hw/mcb/meson.build | 1 + 3 files changed, 314 insertions(+) create mode 100644 hw/mcb/mcb-pci.c diff

Ensure the PV ring is drained on disconnect

If the Xen PV guest VM sends a close whilst there is outstanding I/O being processed that IO needs to be completed and drained before unrealizing the rings or SEGVs will occurr when the I/O does complete and tries to update an already unmapped grant entry.

Re: [PATCH v2] linux-user: preserve incoming order of environment variables in the target

On 29/3/23 16:00, Daniel P. Berrangé wrote: On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote: Do not reverse the order of environment variables in the target environ array relative to the incoming environ order. Some testsuites depend on a specific order, even though it is not

Re: [PATCH-for-8.0 v2 3/3] softmmu: Restore use of CPU watchpoint for all accelerators

Philippe Mathieu-Daudé writes: > CPU watchpoints can be use by non-TCG accelerators. > > KVM uses them: > > $ git grep CPUWatchpoint|fgrep kvm > target/arm/kvm64.c:1558:CPUWatchpoint *wp = find_hw_watchpoint(cs, > debug_exit->far); > target/i386/kvm/kvm.c:5216:static CPUWatchpoint

[PATCH 1/4] Add MEN Chameleon Bus emulation

The MEN Chameleon Bus (MCB) is an on-chip bus system exposing IP Cores of an FPGA to a outside bus system like PCIe. Signed-off-by: Johannes Thumshirn --- MAINTAINERS | 6 ++ hw/Kconfig | 1 + hw/mcb/Kconfig | 2 + hw/mcb/mcb.c | 182

Re: [PATCH v2] linux-user: preserve incoming order of environment variables in the target

On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote: > Do not reverse the order of environment variables in the target environ > array relative to the incoming environ order. Some testsuites depend on a > specific order, even though it is not defined by any standard. > >

Re: [PATCH-for-8.0 v2 2/3] softmmu/watchpoint: Add missing 'qemu/error-report.h' include

Philippe Mathieu-Daudé writes: > cpu_watchpoint_insert() calls error_report() which is declared > in "qemu/error-report.h". When moving this code in commit 2609ec2868 > ("softmmu: Extract watchpoint API from physmem.c") we neglected to > include this header. This works so far because it is

Re: [PATCH-for-8.0 v2 1/3] softmmu: Restrict cpu_check_watchpoint / address_matches to TCG accel

Philippe Mathieu-Daudé writes: > Both cpu_check_watchpoint() and cpu_watchpoint_address_matches() > are specific to TCG system emulation. Declare them in "tcg-cpu-ops.h" > to be sure accessing them from non-TCG code is a compilation error. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by:

[PATCH v2] linux-user: preserve incoming order of environment variables in the target

Do not reverse the order of environment variables in the target environ array relative to the incoming environ order. Some testsuites depend on a specific order, even though it is not defined by any standard. Signed-off-by: Andreas Schwab --- linux-user/main.c | 6 ++ 1 file changed, 6

Re: [PATCH] tests/vm: use the default system python for NetBSD

On 3/29/23 14:46, Daniel P. Berrangé wrote: Currently our NetBSD VM recipe requests instal of the python37 package and explicitly tells QEMU to use that version of python. Since the NetBSD base ISO was updated to version 9.3 though, the default system python version is 3.9 which is sufficiently

Re: [PATCH for 8.0] tests/qemu-iotests: explicitly invoke 'check' via 'python'

On 3/29/23 14:45, Daniel P. Berrangé wrote: The 'check' script will use "#!/usr/bin/env python3" by default to locate python, but this doesn't work in distros which lack a bare 'python3' binary like NetBSD. We need to explicitly invoke 'check' by referring to the 'python' variable in meson,

[PATCH] Ensure the PV ring is drained on disconnect

Also ensure all pending AIO is complete. Signed-off-by: Mark Syms --- hw/block/dataplane/xen-block.c | 16 1 file changed, 16 insertions(+) diff --git a/hw/block/dataplane/xen-block.c b/hw/block/dataplane/xen-block.c index 734da42ea7..067f8e2f45 100644 ---

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