Biosbits avocado tests on gitlab has thus far been disabled because some
packages needed by this test was missing in the container images used by gitlab
CI. These packages have now been added with the commit:
da9000784c90d ("tests/lcitool: Add mtools and xorriso and remove genisoimage as
dependen
17.05.2023 09:35, Thomas Huth wrote:
..
I think this should also go into the next stable release (now on CC:), we're
already getting bug reports about this:
https://gitlab.com/qemu-project/qemu/-/issues/1655
Yes, I already picked that one up after noticing win32/win64 CI build failures.
T
08.02.2023 05:03, Chuck Zmudzinski wrote:
Commit 998250e97661 ("xen, gfx passthrough: register host bridge specific
to passthrough") uses the igd-passthrough-i440FX pci host device with
the xenfv machine type and igd-passthru=on, but using it for the pc
machine type, xen accelerator, and igd-pass
On 20/04/2023 22.29, Cédric Le Goater wrote:
From: Cédric Le Goater
GCC13 reports an error :
../util/async.c: In function ‘aio_bh_poll’:
include/qemu/queue.h:303:22: error: storing the address of local variable
‘slice’ in ‘*ctx.bh_slice_list.sqh_last’ [-Werror=dangling-pointer=]
303 |
On Wed, May 17, 2023 at 5:59 AM Jason Wang wrote:
>
> On Tue, May 9, 2023 at 11:44 PM Eugenio Pérez wrote:
> >
> > Evaluating it at start time instead of initialization time may make the
> > guest capable of dynamically adding or removing migration blockers.
> >
> > Also, moving to initialization
Le 16/05/2023 à 19:08, Richard Henderson a écrit :
On 5/16/23 05:48, Laurent Vivier wrote:
The following changes since commit 7c18f2d663521f1b31b821a13358ce38075eaf7d:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-04-29 23:07:17
+0100)
are available in the
Richard Henderson writes:
> On 5/15/23 22:22, Markus Armbruster wrote:
>>> https://gitlab.com/qemu-project/qemu/-/jobs/4289613692#L574
>>>
>>>File "/builds/qemu-project/qemu/scripts/qapi/parser.py", line 566, in
>>> QAPIDoc
>>> def _match_at_name_colon(string: str) -> Optional[re.Match[
QE tested this series with sanity testing on the vdpa_sim device,
everything are works fine and there is no any new regression problems.
Tested-by: Lei Yang
On Tue, May 9, 2023 at 11:44 PM Eugenio Pérez wrote:
>
> QEMU v8.0 is able to switch dynamically between vhost-vdpa passthrough
> and SV
Two type hints fail centos-stream-8-x86_64 CI. They are actually
broken. Changing them to Optional[re.Match[str]] fixes them locally
for me, but then CI fails differently. Drop them for now.
Fixes: 3e32dca3f0d1 (qapi: Rewrite parsing of doc comment section symbols and
tags)
Signed-off-by: Mark
On 5/17/23 04:46, Zhenzhong Duan wrote:
vbasedev->name is freed wrongly which leads to garbage VFIO trace log.
Fix it by allocating a dup of vbasedev->name and then free the dup.
Fixes: 2dca1b37a7 ("vfio/pci: add support for VF token")
Suggested-by: Alex Williamson
Signed-off-by: Zhenzhong Duan
On Wed, May 17, 2023 at 1:46 PM Eugenio Perez Martin
wrote:
>
> On Wed, May 17, 2023 at 5:14 AM Jason Wang wrote:
> >
> > On Tue, May 9, 2023 at 11:44 PM Eugenio Pérez wrote:
> > >
> > > This allows to reset a vhost-vdpa device from external subsystems like
> > > vhost-net, since it does not hav
On Wed, May 17, 2023 at 5:14 AM Jason Wang wrote:
>
> On Tue, May 9, 2023 at 11:44 PM Eugenio Pérez wrote:
> >
> > This allows to reset a vhost-vdpa device from external subsystems like
> > vhost-net, since it does not have any struct vhost_dev by the time we
> > need to use it.
> >
> > It is use
On Sat, May 6, 2023 at 10:07 PM Hawkins Jiawei wrote:
>
> This patch introduces the vhost_vdpa_net_cvq_add() and
> refactors the vhost_vdpa_net_load*(), so that QEMU can
> send CVQ state load commands in parallel.
>
> To be more specific, this patch introduces vhost_vdpa_net_cvq_add()
> to add SVQ
On Wed, May 17, 2023 at 02:57:12PM +1000, Alistair Francis wrote:
> On Mon, May 8, 2023 at 9:45 PM Andrea Bolognani wrote:
> >
> > On Mon, May 08, 2023 at 04:53:46PM +0530, Sunil V L wrote:
> > > On Mon, May 08, 2023 at 03:00:02AM -0700, Andrea Bolognani wrote:
> > > > I think that it's more impor
On Mon, May 08, 2023 at 04:44:22AM -0700, Andrea Bolognani wrote:
> On Mon, May 08, 2023 at 04:53:46PM +0530, Sunil V L wrote:
> > On Mon, May 08, 2023 at 03:00:02AM -0700, Andrea Bolognani wrote:
> > > I think that it's more important to align with other architectures.
> > >
> > > The number of pe
On Tue, May 16, 2023 at 10:55 AM Yin Wang wrote:
>
> Command "qemu-system-riscv64 -machine virt
> -m 2G -smp 1 -numa node,mem=1G -numa node,mem=1G"
> would trigger this problem.Backtrace with:
> #0 0x55b5b1a4 in riscv_numa_get_default_cpu_node_id at
> ../hw/riscv/numa.c:211
> #1 0x00
On Mon, May 8, 2023 at 9:45 PM Andrea Bolognani wrote:
>
> On Mon, May 08, 2023 at 04:53:46PM +0530, Sunil V L wrote:
> > On Mon, May 08, 2023 at 03:00:02AM -0700, Andrea Bolognani wrote:
> > > I think that it's more important to align with other architectures.
That's true, ideally we want to mat
On Fri, May 12, 2023 at 10:42 PM Daniel Henrique Barboza
wrote:
>
> Alistair,
>
>
> Since this is the only patch that is being contested is it possible to apply
> all
> the other ones to riscv-to-apply.next?
>
> I'm asking because I'm going to send more code that will affect cpu_init() and
> risc
On Mon, May 8, 2023 at 8:29 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 5/7/23 20:25, Alistair Francis wrote:
> > On Fri, Apr 21, 2023 at 11:29 PM Daniel Henrique Barboza
> > wrote:
> >>
> >> write_misa() must use as much common logic as possible. We want to open
> >> code just the bits that are
On Sat, May 6, 2023 at 10:07 PM Hawkins Jiawei wrote:
>
> We want to introduce a new version of vhost_vdpa_net_cvq_add() that
> does not poll immediately after forwarding custom buffers
> to the device, so that QEMU can send all the SVQ control commands
> in parallel instead of serialized.
>
> Sig
So I was working late scratching my head yesterday on why I was not getting my
ASL diff on mismatched blobs! Turns out there were two things:
(a) iasl was not installed and I completely forgot about it because my old
setup is gone and the new box is, well new and I did not get to mess around
wi
在 2023/5/9 16:48, Hawkins Jiawei 写道:
QEMU invokes vhost_svq_add() when adding a guest's element
into SVQ. In vhost_svq_add(), it uses vhost_svq_available_slots()
to check whether QEMU can add the element into SVQ. If there is
enough space, then QEMU combines some out descriptors and some
in des
On Tue, May 9, 2023 at 11:44 PM Eugenio Pérez wrote:
>
> Evaluating it at start time instead of initialization time may make the
> guest capable of dynamically adding or removing migration blockers.
>
> Also, moving to initialization reduces the number of ioctls in the
> migration, reducing failur
On Tue, May 9, 2023 at 10:29 AM Gavin Shan wrote:
>
> There are two RISCV machines where NUMA is aware: 'virt' and 'spike'.
> Both of them are required to follow cluster-NUMA-node boundary. To
> enable the validation to warn about the irregular configuration where
> multiple CPUs in one cluster ha
On Tue, May 9, 2023 at 11:44 PM Eugenio Pérez wrote:
>
> This allows to reset a vhost-vdpa device from external subsystems like
> vhost-net, since it does not have any struct vhost_dev by the time we
> need to use it.
>
> It is used in subsequent patches to negotiate features
> and probe for CVQ A
On Tue, May 2, 2023 at 12:00 AM Mayuresh Chitale
wrote:
>
> If smstateen is implemented and smtateen0.fcsr is clear and misa.F
> is off then the floating point operations must return illegal
> instruction exception or virtual instruction trap, if relevant.
Do you mind re-wording this commit messa
vbasedev->name is freed wrongly which leads to garbage VFIO trace log.
Fix it by allocating a dup of vbasedev->name and then free the dup.
Fixes: 2dca1b37a7 ("vfio/pci: add support for VF token")
Suggested-by: Alex Williamson
Signed-off-by: Zhenzhong Duan
---
v2: "toke" -> "token", Cedric
Up
On Sun, Apr 23, 2023 at 11:39 PM Yong Li wrote:
>
> The firmware may be specified with -bios
> and the plfash0 device with option -drive if=pflash.
> If both options are applied, it is intented that the pflash0 will
> store the secure variable and the firmware be the one specified
> by -bios. Expl
On Wed, May 10, 2023 at 1:02 PM Weiwei Li wrote:
>
> Zc* extensions (version 1.0) are ratified.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 16
> 1 file changed, 8 insertions(+), 8
On Sat, Apr 29, 2023 at 12:38 AM Weiwei Li wrote:
>
> Access will fails if access is partially inside the PMP entry.
> However,only set ret = false doesn't really mean pmp violation
> since pmp_hart_has_privs_default() may return true at the end of
> pmp_hart_has_privs().
>
> Signed-off-by: Weiwei
On Sat, Apr 29, 2023 at 12:38 AM Weiwei Li wrote:
>
> Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to
> update rule nums only once for each pmpcfg_csr_write. Then remove
> pmp_update_rule() since it become unused.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
R
On Sat, Apr 29, 2023 at 12:38 AM Weiwei Li wrote:
>
> Currently only the rule addr of the same index of pmpaddr is updated
> when pmpaddr CSR is modified. However, the rule addr of next PMP entry
> may also be affected if its A field is PMP_AMATCH_TOR. So we should
> also update it in this case.
>
On Sat, Apr 29, 2023 at 12:37 AM Weiwei Li wrote:
>
> RLB/MML/MMWP bits in mseccfg CSR are introduced by Smepmp extension.
> So they can only be writable and set to 1s when cfg.epmp is true.
> Then we also need't check on epmp in pmp_hart_has_privs_default().
>
> Signed-off-by: Weiwei Li
> Signed
On Sat, Apr 29, 2023 at 12:39 AM Weiwei Li wrote:
>
> MMWP and MML bits may affect the allowed privs of PMP entries and the
> default privs, both of which may change the allowed privs of exsited
> TLB entries. So we need flush TLB when they are changed.
>
> Signed-off-by: Weiwei Li
> Signed-off-b
On Sat, Apr 29, 2023 at 12:38 AM Weiwei Li wrote:
>
> The addr and size parameters in pmp_hart_has_privs_default() are unused.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/pmp.c | 9 +++--
> 1 file changed, 3 ins
On Sat, Apr 29, 2023 at 12:38 AM Weiwei Li wrote:
>
> We no longer need the pmp_index for matched PMP entry now.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 8
> target/riscv/pmp.c|
On Sat, Apr 29, 2023 at 12:38 AM Weiwei Li wrote:
>
> Return the result directly for short cut, since We needn't do the
> following check on the PMP entries if there is no PMP rules.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> t
On Sat, Apr 29, 2023 at 12:38 AM Weiwei Li wrote:
>
> pmp_get_tlb_size can be separated from get_physical_address_pmp and is only
> needed when ret == TRANSLATE_SUCCESS.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alista
On Sat, Apr 29, 2023 at 12:37 AM Weiwei Li wrote:
>
> PMP entries before the matched PMP entry (including the matched PMP entry)
> may only cover partial of the TLB page, which may make different regions in
> that page allow different RWX privs. Such as for PMP0 (0x8008~0x800F,
> R) and PM
On Wed, May 3, 2023 at 6:57 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target-con-set.h | 1 +
> tcg/riscv/tcg-target.h | 8
> tcg/riscv/tcg-target.c.inc | 35 ++
v2: Drop a few patches, which showed regressions in CI
for jobs that are not run for forks. :-/
r~
The following changes since commit f9d58e0ca53b3f470b84725a7b5e47fcf446a2ea:
Merge tag 'pull-9p-20230516' of https://github.com/cschoenebeck/qemu into
staging (2023-05-16 10:2
On Wed, May 3, 2023 at 6:59 PM Richard Henderson
wrote:
>
> Implement with and without Zicond. Without Zicond, we were letting
> the middle-end expand to a 5 insn sequence; better to use a branch
> over a single insn.
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
>
On Wed, May 3, 2023 at 6:59 PM Richard Henderson
wrote:
>
> Split out a helper function, tcg_out_setcond_int, which does not
> always produce the complete boolean result, but returns a set of
> flags to do so.
>
> Based on 21af16198425, the same improvement for loongarch64.
>
> Signed-off-by: Rich
On Mon, May 15, 2023 at 10:32:01AM +0200, Juan Quintela wrote:
> When we detect that we have broken backwards compantibility in a
> released version, we can't do anything for that version. But once we
> fix that bug on the next released version, we can "mitigate" that
> problem when migrating to n
On Wed, May 3, 2023 at 6:58 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target.h | 4 ++--
> tcg/riscv/tcg-target.c.inc | 9 +
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/r
On Mon, May 15, 2023 at 10:32:00AM +0200, Juan Quintela wrote:
> Sometimes devices have different features depending of things outside
> of qemu. For instance the kernel. Document how to handle that cases.
>
> Signed-off-by: Juan Quintela
>
> ---
>
> If you have some example to put here, I am
On Wed, May 3, 2023 at 6:59 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target.h | 10 +-
> tcg/riscv/tcg-target.c.inc | 29 +
> 2 files changed, 34 insertions(+), 5 deletio
On Wed, May 3, 2023 at 6:57 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target.h | 4 ++--
> tcg/riscv/tcg-target.c.inc | 34 ++
> 2 files changed, 36 insertions(+), 2 deletion
On Wed, May 3, 2023 at 6:58 PM Richard Henderson
wrote:
>
> The instruction is a combined zero-extend and add.
> Use it for exactly that.
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target.c.inc | 33 ++---
> 1 fi
On Wed, May 3, 2023 at 6:59 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target.c.inc | 32
> 1 file changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.
On Mon, May 15, 2023 at 10:31:59AM +0200, Juan Quintela wrote:
> State what are the requeriments to get migration working between qemu
> versions. And once there explain how one is supposed to implement a
> new feature/default value and not break migration.
>
> Reviewed-by: Vladimir Sementsov-Ogi
On Wed, May 3, 2023 at 6:58 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target-con-set.h | 1 +
> tcg/riscv/tcg-target-con-str.h | 1 +
> tcg/riscv/tcg-target.h | 12 +-
> tcg/riscv/tcg-target.c.
On Wed, May 3, 2023 at 6:59 PM Richard Henderson
wrote:
>
> Define a useful subset of the extensions. Probe for them
> via compiler pre-processor feature macros and SIGILL.
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target.h | 6 +++
>
On Wed, May 3, 2023 at 6:59 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index d6b0fbe5e8..c0a8b1006a
On 05/16/2023 01:08 PM -0700, Richard Henderson wrote:
> On 5/15/23 20:59, Zhuojia Shen wrote:
> > DC CVAP and DC CVADP instructions can be executed in EL0 on Linux,
> > either directly when SCTLR_EL1.UCI == 1 or emulated by the kernel (see
> > user_cache_maint_handler() in arch/arm64/kernel/traps.
On Tue, May 16, 2023 at 11:32:27PM +0900, ~akihirosuda wrote:
>
> From: Akihiro Suda
>
> "zlib" clusters are actually raw deflate (RFC1951) clusters without
> zlib headers.
>
> Signed-off-by: Akihiro Suda
> ---
> docs/interop/qcow2.txt | 10 +++---
> 1 file changed, 7 insertions(+), 3 d
On Fri, May 12, 2023 at 03:29:02PM +0300, Andrew Melnychenko wrote:
>
> Updated section name, so libbpf should init/gues proper
> program type without specifications during open/load.
>
> Signed-off-by: Andrew Melnychenko
> ---
> ebpf/rss.bpf.skeleton.h | 1469
On Tue, May 16, 2023 at 04:22:58PM -0500, Eric DeVolder wrote:
>
>
> On 5/16/23 07:51, Ani Sinha wrote:
> > On Tue, May 16, 2023 at 6:01 PM Igor Mammedov wrote:
> > >
> > > On Mon, 15 May 2023 16:33:10 -0400
> > > Eric DeVolder wrote:
> > >
> > > > Currently i386 QEMU generates MADT revision
On 5/16/23 07:51, Ani Sinha wrote:
On Tue, May 16, 2023 at 6:01 PM Igor Mammedov wrote:
On Mon, 15 May 2023 16:33:10 -0400
Eric DeVolder wrote:
Currently i386 QEMU generates MADT revision 3, and reports
MADT revision 1. Set .revision to 3 to match reality.
Link: https://lore.kernel.org/
On Mon, May 15, 2023 at 10:38:44AM +0100, Daniel P. Berrangé wrote:
>
> > -static bool virtio_net_load_ebpf(VirtIONet *n)
> > +static bool virtio_net_load_ebpf_fds(VirtIONet *n, Error **errp)
> > {
> > -if (!virtio_net_attach_ebpf_to_backend(n->nic, -1)) {
> > -/* backend does't sup
16.05.2023 18:21, Christian Schoenebeck wrote:
From: Jason Andryuk
xen_9pfs_free can't use gnttabdev since it is already closed and NULL-ed
out when free is called. Do the teardown in _disconnect(). This
matches the setup done in _connect().
trace-events are also added for the XenDevOps func
Right now, either stage-1 or stage-2 are supported, this simplifies
how we can deal with TLBs.
This patch makes TLB lookup work if stage-2 is enabled instead of
stage-1.
TLB lookup is done before a PTW, if a valid entry is found we won't
do the PTW.
To be able to do TLB lookup, we need the correct
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
same as CMD_TLBI_NH_VAA.
CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.
For stage-1 only commands, add a check to throw CERROR_ILL if used
when stage-1 is not supported.
Reviewed-by: Eric Auger
Signed-off-by: M
In preparation for adding stage-2 support, rename smmu_ptw_64 to
smmu_ptw_64_s1 and refactor some of the code so it can be reused in
stage-2 page table walk.
Remove AA64 check from PTW as decode_cd already ensures that AA64 is
used, otherwise it faults with C_BAD_CD.
A stage member is added to SM
In smmuv3_notify_iova, read the granule based on translation stage
and use VMID if valid value is sent.
Signed-off-by: Mostafa Saleh
Reviewed-by: Eric Auger
---
Changes in v3:
- Collected Reviewed-by tag.
---
hw/arm/smmuv3.c | 39 ++-
hw/arm/trace-events
Allow TLB to be tagged with VMID.
If stage-1 is only supported, VMID is set to -1 and ignored from STE
and CMD_TLBI_NH* cmds.
Update smmu_iotlb_insert trace event to have vmid.
Signed-off-by: Mostafa Saleh
Reviewed-by: Eric Auger
---
Changes in v3:
- Collected Reviewed-by tag.
Changes in v2:
-
In preparation for adding stage-2 support, add Stage-2 PTW code.
Only Aarch64 format is supported as stage-1.
Nesting stage-1 and stage-2 is not supported right now.
HTTU is not supported, SW is expected to maintain the Access flag.
This is described in the SMMUv3 manual(IHI 0070.E.a)
"5.2. Strea
In preparation for adding stage-2 support, add a S2 config
struct(SMMUS2Cfg), composed of the following fields and embedded in
the main SMMUTransCfg:
-tsz: Size of IPA input region (S2T0SZ)
-sl0: Start level of translation (S2SL0)
-affd: AF Fault Disable (S2AFFD)
-record_faults: Record fault ev
In preparation for adding stage-2 support.
Add IDR0 fields related to stage-2.
VMID16: 16-bit VMID supported.
S2P: Stage-2 translation supported.
They are described in 6.3.1 SMMU_IDR0.
No functional change intended.
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Signed-off-by: Mostafa
Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
Validity of field values are checked when possible.
Only AA64 tables are supported and Small Translation Tables (STT) are
not supported.
According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields
with an S2 prefix (with
As everything is in place, we can use a new system property to
advertise which stage is supported and remove bad_ste from STE
stage2 config.
The property added arm-smmuv3.stage can have 3 values:
- "1": Stage-1 only is advertised.
- "2": Stage-2 only is advertised.
If not passed or an unsupported
This patch series adds stage-2 translation support for SMMUv3. It is
controlled by a new system property “arm-smmuv3.stage”.
- When set to “1”: Stage-1 only would be advertised and supported (default
behaviour)
- When set to “2”: Stage-2 only would be advertised and supported.
Features implemented
On 4/28/23 02:55, Cornelia Huck wrote:
Extend the 'mte' property for the virt machine to cover KVM as
well. For KVM, we don't allocate tag memory, but instead enable the
capability.
If MTE has been enabled, we need to disable migration, as we do not
yet have a way to migrate the tags as well. Th
On 5/16/23 13:11, Michael Tokarev wrote:
12.05.2023 20:17, Richard Henderson wrote:
The REXW bit must be set to produce a 64-bit pointer result; the
bit is disabled in 32-bit mode, so we can do this unconditionally.
Fixes: 7d9e1ee424b0 ("tcg/i386: Adjust assert in tcg_out_addi_ptr")
Resolves: h
On 5/16/23 03:44, Alex Bennée wrote:
The commit b3aa2f2128 (target/arm: provide stubs for more external
debug registers) was added to handle HyperV's unconditional usage of
Debug Communications Channel. It turns out that Linux will similarly
break if you enable CONFIG_HVC_DCC "ARM JTAG DCC consol
12.05.2023 20:17, Richard Henderson wrote:
The REXW bit must be set to produce a 64-bit pointer result; the
bit is disabled in 32-bit mode, so we can do this unconditionally.
Fixes: 7d9e1ee424b0 ("tcg/i386: Adjust assert in tcg_out_addi_ptr")
Resolves: https://gitlab.com/qemu-project/qemu/-/issu
On 5/15/23 20:59, Zhuojia Shen wrote:
DC CVAP and DC CVADP instructions can be executed in EL0 on Linux,
either directly when SCTLR_EL1.UCI == 1 or emulated by the kernel (see
user_cache_maint_handler() in arch/arm64/kernel/traps.c). The Arm ARM
documents the semantics of the two instructions th
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index e244209890..4375a06377 100644
--- a/tcg/sparc64/tcg-target
Emphasize that the constant is signed.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 64464
Use LPQ/STPQ when 16-byte atomicity is required.
Note that these instructions require 16-byte alignment.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 2 +
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 103
Use the fpu to perform 64-bit loads and stores.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 44 +--
1 file changed, 38 insertions(+), 6 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.
Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required.
Note that these instructions do not require 16-byte alignment.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target-con-set.h | 2 +
tcg/ppc/tcg-target-con-str.h | 1 +
tcg/ppc/tcg-target.h
TCG will need this declaration, without all of the other
bits that come with cpu-all.h.
Reviewed-by: Thomas Huth
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 5 +
include/exec/user/guest-base.h | 12
tcg/tcg.c | 3 +++
3 files cha
Always pass the target address as uint64_t.
Adjust tcg_out_{ld,st}_helper_args to match.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/tcg/tcg-ldst.h | 26 +-
accel/tcg/cputlb.c | 26 +-
accel/tcg/user-exec.c | 26 +-
We already pass uint64_t to restore_state_to_opc; this changes all
of the other uses from insn_start through the encoding to decoding.
Reviewed-by: Anton Johansson
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 39 +
Expand from TCGv to TCGTemp inline in the translators,
and validate that the size matches tcg_ctx->addr_type.
These inlines will eventually be seen only by target-specific code.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 50 ++-
tcg/tcg-op-ldst.c
We only need to make copies for loads, when the destination
overlaps the address. For now, only eliminate the copy for
stores and 128-bit loads.
Rename plugin_prep_mem_callbacks to plugin_maybe_preserve_addr,
returning NULL if no copy is made.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Hen
As gen_mem_wrapped is only used in plugin_gen_empty_mem_callback,
we can avoid the curiosity of union mem_gen_fn by inlining it.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 30 ++
1 file changed, 6 insertions(+), 24 deletion
As do_gen_mem_cb is called once, merge it into gen_empty_mem_cb.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 39 +--
1 file changed, 17 insertions(+), 22 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/
Am Tue, 16 May 2023 13:38:42 -0400
schrieb John Snow :
> I haven't touched IDE or block code in quite a long while now -- I
> don't think I can help land this fix, but I won't get in anyone's way,
> either. Maybe just re-submit the patches with an improved commit
> message / cover letter that help
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index cd0254a0d7..3f3fe5b991 100644
--- a/tcg/mips/tcg-target.c.inc
There is an edge condition prior to gcc13 for which optimization
is required to generate 16-byte atomic sequences. Detect this.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
meson.build| 52 ++
accel/tcg/ldst_atomicity.c.inc
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index bb23038529..9676b745a2 100644
--- a/tcg/sparc6
All uses replaced with TCGContext.addr_type.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 8d78838796..4
Use LDXP+STXP when LSE2 is not present and 16-byte atomicity is required,
and LDP/STP otherwise. This requires allocating a second general-purpose
temporary, as Rs cannot overlap Rn in STXP.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-con-set.h | 2
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index b62a163014..b5c49895f3 100644
--- a/tcg/ppc/tcg-target.c.inc
All uses can be infered from the INDEX_op_qemu_*_a{32,64}_* opcode
being used. Add a field into TCGLabelQemuLdst to record the usage.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --gi
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index d26174dde5..07d35f92fa 100644
--- a/tcg/loongarch64/
Notice when the host has additional atomic instructions.
The new variables will also be used in generated code.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 3 +++
tcg/aarch64/tcg-target.c.inc | 12 +
Because of its use on tgen_arithi, this value must be a signed
32-bit quantity, as that is what may be encoded in the insn.
The truncation of the value to unsigned for 32-bit guests is
done via the REX bit via 'trexw'.
Removes the only uses of target_ulong from this tcg backend.
Reviewed-by: Alex
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