From: Max Fritz
This modification enables better control over the inclusion of libkeyutils
based on the configuration, enhancing the flexibility of the build system.
Signed-off-by: Max Fritz
---
meson.build | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/meson.build
I have a patch that adds a conditional dependency for 'libkeyutils' in
the meson.build file to enhance the build system's flexibility. The
patch addresses the following issue:
If the dynamic library 'libkeyutils' is found by pkg-config, but one
attempts to build with static linkage, the build
Hi, Jiaxun,
Rename loongarch_ipi to loongson_ipi? It will be shared by both MIPS
and LoongArch in your series.
Huacai
On Sun, May 21, 2023 at 6:24 PM Jiaxun Yang wrote:
>
> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
> Loongson 3A5000's IPI implementation have 4 mailboxes per
Hi,
在 2023/5/21 下午6:23, Jiaxun Yang 写道:
IOCSR based send features are tied to LoongArch's CPU implmentation,
ifdef them for LoongArch only so we can build loongarch_ipi on MIPS.
Note that Loongson-3A4000 have IOCSR as well, so we may implement
those features for MIPS in future.
Signed-off-by:
Hi there,
This series enables Loongson-3A4000 TCG for system emulation.
It Implemented Loongson CSR insertions which is required for
Linux Kernel to probe CPU features and removed CPU type restrictions
for loongson3_virt board.
This series is based on two of my previous series[1] [2]. However
After implemented CPUCFG and CSR, we are now able to boot Linux
kernel with Loongson-3A4000 CPU, so there is no point to restrict
CPU type for TCG.
Signed-off-by: Jiaxun Yang
---
hw/mips/loongson3_virt.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/mips/loongson3_virt.c
Loongson introduced CSR instructions since 3A4000, which looks
similar to IOCSR and CPUCFG instructions we seen in LoongArch.
Unfortunately we don't have much document about those instructions,
bit fields of CPUCFG instructions and IOCSR registers can be found
at 3A4000's user manual, while
On Sun, 21 May 2023, BALATON Zoltan wrote:
On Sun, 21 May 2023, Bernhard Beschow wrote:
Resolves circular depencency between IDE function and south bridge.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
---
hw/ide/via.c | 6 --
hw/isa/vt82c686.c | 5 +
2 files
On Sun, 21 May 2023, Bernhard Beschow wrote:
The modern, declarative way to set up VM state handling is to assign to
DeviceClass::vmsd attribute.
There shouldn't be any change in behavior since dc->vmsd causes
vmstate_register_with_alias_id() to be called on the instance during
the instance
Hello everyone,
This is v3 of the switchover ack series (previously called precopy
initial data).
Changes from v2 [4]:
* Rebased on latest master branch.
* Changed the capability name to "switchover-ack" and the related
code/docs accordingly. (Peter)
* Added a counter for the number of
On Sun, 21 May 2023, Bernhard Beschow wrote:
Every TYPE_PCI_IDE device performs the same not-so-trivial bit manipulation by
copy'n'paste code. Extract this into bmdma_status_writeb(), mirroring
bmdma_cmd_writeb().
Signed-off-by: Bernhard Beschow
Reviewed-by: BALATON Zoltan
Refactor vfio_save_block() to return the size of saved data on success
and -errno on error.
This will be used in next patch to implement VFIO migration pre-copy
support.
Signed-off-by: Avihai Horon
Reviewed-by: Cédric Le Goater
Reviewed-by: Juan Quintela
---
hw/vfio/migration.c | 17
Add migration switchover ack capability test. The test runs without
devices that support this capability, but is still useful to make sure
it didn't break anything.
Signed-off-by: Avihai Horon
Reviewed-by: Juan Quintela
Reviewed-by: Peter Xu
---
tests/qtest/migration-test.c | 26
Loading of a VFIO device's data can take a substantial amount of time as
the device may need to allocate resources, prepare internal data
structures, etc. This can increase migration downtime, especially for
VFIO devices with a lot of resources.
To solve this, VFIO migration uAPI defines "initial
Now that switchover ack logic has been implemented, enable the
capability.
Signed-off-by: Avihai Horon
Reviewed-by: Juan Quintela
Reviewed-by: Peter Xu
---
migration/options.c | 4
1 file changed, 4 deletions(-)
diff --git a/migration/options.c b/migration/options.c
index
Implement switchover ack logic. This prevents the source from stopping
the VM and completing the migration until an ACK is received from the
destination that it's OK to do so.
To achieve this, a new SaveVMHandlers handler switchover_ack_needed()
and a new return path message
Pre-copy support allows the VFIO device data to be transferred while the
VM is running. This helps to accommodate VFIO devices that have a large
amount of data that needs to be transferred, and it can reduce migration
downtime.
Pre-copy support is optional in VFIO migration protocol v2.
Implement
Migration downtime estimation is calculated based on bandwidth and
remaining migration data. This assumes that loading of migration data in
the destination takes a negligible amount of time and that downtime
depends only on network speed.
While this may be true for RAM, it's not necessarily true
On Sun, 21 May 2023, Bernhard Beschow wrote:
Resolves circular depencency between IDE function and south bridge.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
---
hw/ide/via.c | 6 --
hw/isa/vt82c686.c | 5 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff
On 5/21/23 04:28, Philippe Mathieu-Daudé wrote:
On 20/5/23 18:26, Richard Henderson wrote:
Add cpuinfo.h for i386 and x86_64, and the initialization
for that in util/. Populate that with a slightly altered
copy of the tcg host probing code. Other uses of cpuid.h
will be adjusted one patch at
On 5/21/23 04:21, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 20/5/23 18:26, Richard Henderson wrote:
Use cpu_ld16_mmu and cpu_st16_mmu to eliminate the special case,
and change all of the *_data_ra functions to match.
Signed-off-by: Richard Henderson
---
Cc: qemu-s3...@nongnu.org
Cc: David
On 5/21/23 04:15, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 20/5/23 18:26, Richard Henderson wrote:
With the current structure of cputlb.c, there is no difference
between the little-endian and big-endian entry points, aside
from the assert. Unify the pairs of functions.
The only use of
> On 21-May-2023, at 2:24 PM, Michael S. Tsirkin wrote:
>
> On Wed, May 17, 2023 at 05:37:51PM +0530, Ani Sinha wrote:
>> Currently the meson based QEMU build process locates the iasl binary from the
>> current PATH and other locations [1] and uses that to set CONFIG_IASL which
>> is
>> then
On Sun, 21 May 2023, Bernhard Beschow wrote:
Exporting ParallelState is a precondition for exporing TYPE_ISA_PARALLEL.
This may need a better commit message. It's not a precondition per coding
standards I think just a preference for allowing embedding the device in
other devices but
The attribute isn't used since commit 5c9736789b79ea49cd236ac326f0a414f63b1015
"i82378: Cleanup implementation".
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
Reviewed-by: Mark Cave-Ayland
---
hw/isa/i82378.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/isa/i82378.c
In order to replace string literals with the TYPE_ISA_PARALLEL macro we need to
export the whole structure as well.
Suggested-by: Mark Cave-Ayland
---
include/hw/char/parallel-isa.h | 46 ++
hw/char/parallel.c | 13 +-
2 files changed, 47
Exporting ParallelState is a precondition for exporing TYPE_ISA_PARALLEL.
Suggested-by: Mark Cave-Ayland
---
include/hw/char/parallel.h | 44 ++
hw/char/parallel.c | 42
2 files changed, 44 insertions(+), 42
Both TYPE_KVM_I8254 and TYPE_I8254 have their own but same implementation of
the "iobase" property. The storage for the property already resides in
PITCommonState, so also move the property definition there.
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
Reviewed-by: Mark
This series:
* Removes dead code from omap_uart and i82378
* Resolves redundant code in the i8254 timer devices
* Exports ParallelState and ISAParallelState in order to replac string literals
by TYPE_ISA_PARALLEL macro usage
v2:
* Export ParallelState and ISAParallelState (Mark)
Testing done:
Rather than using a string literal which is prone to typos let's use a macro
instead which is caught by the compiler if mistyped.
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
---
hw/char/parallel-isa.c | 3 ++-
hw/isa/isa-superio.c | 3 ++-
2 files changed, 4 insertions(+), 2
The function is unused since commit
bdad3654d3c55f478e538037d9eccd204e5fc8ee ('hw/arm/nseries: Remove
invalid/unnecessary n8x0_uart_setup()').
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
On 21/5/23 13:00, Jiaxun Yang wrote:
Previous implementation of MIPS cp0_timer computes a
cp0_count_ns based on input clock. However rounding
error of cp0_count_ns can affect precision of cp0_timer.
Using clock API and a divider for cp0_timer, so we can
use clock_ns_to_ticks/clock_ns_to_ticks
On 20/5/23 18:26, Richard Henderson wrote:
Add cpuinfo.h for i386 and x86_64, and the initialization
for that in util/. Populate that with a slightly altered
copy of the tcg host probing code. Other uses of cpuid.h
will be adjusted one patch at a time.
Reviewed-by: Juan Quintela
On 20/5/23 18:26, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/debug-assert.h | 17 +
include/tcg/tcg.h | 9 +
2 files changed, 18 insertions(+), 8 deletions(-)
create mode 100644 include/tcg/debug-assert.h
While here:
---
Hi Richard,
On 20/5/23 18:26, Richard Henderson wrote:
Use cpu_ld16_mmu and cpu_st16_mmu to eliminate the special case,
and change all of the *_data_ra functions to match.
Signed-off-by: Richard Henderson
---
Cc: qemu-s3...@nongnu.org
Cc: David Hildenbrand
Cc: Ilya Leoshkevich
---
Every TYPE_PCI_IDE device performs the same not-so-trivial bit manipulation by
copy'n'paste code. Extract this into bmdma_status_writeb(), mirroring
bmdma_cmd_writeb().
Signed-off-by: Bernhard Beschow
---
include/hw/ide/pci.h | 1 +
hw/ide/cmd646.c | 2 +-
hw/ide/pci.c | 5 +
Every invocation of bmdma_init() is followed by `d->bmdma[i].bus = >bus[i]`.
Resolve this redundancy by extracting it into bmdma_init().
Signed-off-by: Bernhard Beschow
Reviewed-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
---
hw/ide/cmd646.c | 1 -
Now that via_isa_set_irq() is unused it can be removed.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
---
include/hw/isa/vt82c686.h | 2 --
hw/isa/vt82c686.c | 6 --
2 files changed, 8 deletions(-)
diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h
The modern, declarative way to set up VM state handling is to assign to
DeviceClass::vmsd attribute.
There shouldn't be any change in behavior since dc->vmsd causes
vmstate_register_with_alias_id() to be called on the instance during
the instance init phase. vmstate_register() was also called
This series is split off from a more general PCI IDE refactoring aiming for a
common implementation of the PCI IDE controller specification for all
TYPE_PCI_IDE models [1].
The first three patches resolve a circular dependency between the VIA IDE
controller and its south bridge. The next two
Resolves circular depencency between IDE function and south bridge.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
---
hw/ide/via.c | 6 --
hw/isa/vt82c686.c | 5 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/ide/via.c b/hw/ide/via.c
index
Exposing the legacy IDE interrupts as GPIOs allows them to be connected in the
parent device through qdev_connect_gpio_out(), i.e. without accessing private
data of TYPE_PCI_IDE.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
---
hw/ide/pci.c | 9 +
1 file changed, 9
Hi Richard,
On 20/5/23 18:26, Richard Henderson wrote:
With the current structure of cputlb.c, there is no difference
between the little-endian and big-endian entry points, aside
from the assert. Unify the pairs of functions.
The only use of the functions with explicit endianness was in
Previous implementation of MIPS cp0_timer computes a
cp0_count_ns based on input clock. However rounding
error of cp0_count_ns can affect precision of cp0_timer.
Using clock API and a divider for cp0_timer, so we can
use clock_ns_to_ticks/clock_ns_to_ticks to avoid rounding
issue.
Also
On 20/5/23 18:26, Richard Henderson wrote:
Silly typo: sizeof(16) != 16.
Fixes: e61f1efeb730 ("meson: Detect atomic128 support with optimization")
Signed-off-by: Richard Henderson
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
On 20/5/23 18:26, Richard Henderson wrote:
The entire contents of the header is host-specific, but the
existence of such a header is not, which could prevent some
host specific ifdefs at the top of the file for the include.
Add host/include/{arch,generic} to the project arguments.
Reviewed-by:
On 20/5/23 18:26, Richard Henderson wrote:
Separates the aarch64-specific portion into its own file.
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-cas.h | 43 ++
host/include/generic/host/atomic128-cas.h | 43 ++
Test loongson3-virt machine againt debian kernel and cpio rootfs.
Signed-off-by: Jiaxun Yang
---
tests/avocado/boot_linux_console.py | 46 +
1 file changed, 46 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
IOCSR based send features are tied to LoongArch's CPU implmentation,
ifdef them for LoongArch only so we can build loongarch_ipi on MIPS.
Note that Loongson-3A4000 have IOCSR as well, so we may implement
those features for MIPS in future.
Signed-off-by: Jiaxun Yang
---
hw/intc/loongarch_ipi.c
Hi all,
This series wires up loongarch_ipi device for loongson3-virt,
which is required for SMP support.
We also add a new test for loongson3-virt for acceptance harness.
Thanks
- Jiaxun
Jiaxun Yang (4):
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
hw/intc/loongarch_ipi: Guard
Wire up loongarch_ipi device for loongson3_virt machine, so we
can have SMP support for TCG backend as well.
Signed-off-by: Jiaxun Yang
---
hw/mips/Kconfig | 1 +
hw/mips/loongson3_bootp.c | 2 --
hw/mips/loongson3_bootp.h | 3 +++
hw/mips/loongson3_virt.c | 20
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
Loongson 3A5000's IPI implementation have 4 mailboxes per
core.
However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
percpu device"), the number of IPI mailboxes was reduced to
one, which mismatches actual hardware.
It won't
On Sat, May 20, 2023 at 07:08:22PM +0200, Philippe Mathieu-Daudé wrote:
> On 20/5/23 17:15, Richard Henderson wrote:
> > On 5/20/23 06:15, BALATON Zoltan wrote:
> > > On Sat, 20 May 2023, Peter Maydell wrote:
> > > > On Fri, 19 May 2023 at 15:19, Jonathan Cameron via
> > > > wrote:
> > > > >
> >
On Wed, May 17, 2023 at 05:37:51PM +0530, Ani Sinha wrote:
> Currently the meson based QEMU build process locates the iasl binary from the
> current PATH and other locations [1] and uses that to set CONFIG_IASL which is
> then used by the test.
>
> This has two disadvantages:
> - If iasl was not
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