The following changes since commit d762bf97931b58839316b68a570eecc6143c9e3e:
Merge tag 'pull-target-arm-20231102' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-11-03
10:04:12 +0800)
are available in the Git repository at:
https://gitlab.com/gaosong/qem
We use cpu la464 for the 'max' cpu.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20231020084925.3457084-2-gaos...@loongson.cn>
---
target/loongarch/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ef1bf
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20231101030816.2353416-7-gaos...@loongson.cn>
---
linux-user/loongarch64/signal.c | 68 ++---
1 file changed, 62 insertions(+), 6 deletions(-)
diff --git a/linux-user/loongarch64/signal.c b/linux-use
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-Id: <20231101030816.2353416-2-gaos...@loongson.cn>
Signed-off-by: Song Gao
---
linux-user/loongarch64/cpu_loop.c | 13 +
target/loongarch/insn_trans/trans_vec.c.inc | 11 ---
2 files changed, 13 inse
The LoongArch kernel supports 4K page size.
Change TARGET_PAGE_BITS to 12.
Signed-off-by: Song Gao
Message-Id: <20231023024059.3858349-1-gaos...@loongson.cn>
---
target/loongarch/cpu-param.h | 2 +-
target/loongarch/tlb_helper.c | 9 -
2 files changed, 5 insertions(+), 6 deletions(-)
d
See:
https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c
The kernel setup_sigcontext() set end context size 0.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20231101030816.2353416-4-gaos...@loongson.cn>
---
linux-user/loongarch64/signal.c | 2 +-
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20231101030816.2353416-6-gaos...@loongson.cn>
---
linux-user/loongarch64/signal.c | 107 ++--
1 file changed, 87 insertions(+), 20 deletions(-)
diff --git a/linux-user/loongarch64/signal.c b/linux-us
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20231101030816.2353416-5-gaos...@loongson.cn>
---
linux-user/loongarch64/signal.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/linux-user/loongarch64/signal.c b/linux-user/loonga
Add support for the query-cpu-model-expansion QMP command to LoongArch.
We support query the cpu features.
e.g
la464 and max cpu support LSX/LASX, default enable,
la132 not support LSX/LASX.
1. start with '-cpu max,lasx=off'
(QEMU) query-cpu-model-expansion type=static model={
Some users may not need LSX/LASX, this patch allows the user
enable/disable LSX/LASX features.
e.g
'-cpu max,lsx=on,lasx=on' (default);
'-cpu max,lsx=on,lasx=off' (enabled LSX);
'-cpu max,lsx=off,lasx=on' (enabled LASX, LSX);
'-cpu max,lsx=off' (disable LSX and LASX).
Signed-off
See:
https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c
The alloc size is sizeof(struct target_fpu_context).
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20231101030816.2353416-3-gaos...@loongson.cn>
---
linux-user/loongarch64/signal.c | 2 +-
Markus Armbruster writes:
> There are a few more reports left. Before I try to address them, I'd
> like to know:
>
> 1. Do we still need to support Sphinx older than 1.7?
>
> 2. What should intersperse() do when the first argument is empty?
Patch queued, questions remain open.
[...]
Markus Armbruster writes:
> Pylint warns:
>
> tests/qapi-schema/test-qapi.py:139:13: W1514: Using open without
> explicitly specifying an encoding (unspecified-encoding)
> tests/qapi-schema/test-qapi.py:143:13: W1514: Using open without
> explicitly specifying an encoding (unspecified-e
On Thu, Nov 02, 2023 at 01:53:05PM +, Peter Maydell wrote:
> On Thu, 2 Nov 2023 at 13:49, Peter Xu wrote:
> >
> > On Thu, Nov 02, 2023 at 05:40:12PM +0800, Ethan Chen wrote:
> > > Signed-off-by: Ethan Chen
> > > ---
> > > include/exec/memattrs.h | 6 ++
> > > 1 file changed, 6 insertions
On Thu, Nov 02, 2023 at 09:49:17AM -0400, Peter Xu wrote:
> On Thu, Nov 02, 2023 at 05:40:12PM +0800, Ethan Chen wrote:
> > Signed-off-by: Ethan Chen
> > ---
> > include/exec/memattrs.h | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/include/exec/memattrs.h b/include/exec/me
On Mon, Oct 30, 2023 at 11:01:26PM +0800, Sam Li wrote:
> Hi Eric,
>
> Eric Blake 于2023年10月30日周一 22:53写道：
> >
> > On Mon, Oct 30, 2023 at 08:18:45PM +0800, Sam Li wrote:
> > > To configure the zoned format feature on the qcow2 driver, it
> > > requires settings as: the device size, zone model, zo
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
On Mon, Oct 30, 2023 at 08:18:45PM +0800, Sam Li wrote:
> To configure the zoned format feature on the qcow2 driver, it
> requires settings as: the device size, zone model, zone size,
> zone capacity, number of conventional zones, limits on zone
> resources (max append bytes, max open zones, and ma
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
On Mon, Oct 30, 2023 at 08:18:45PM +0800, Sam Li wrote:
> +typedef struct Qcow2ZoneListEntry {
> +QLIST_ENTRY(Qcow2ZoneListEntry) exp_open_zone_entry;
> +QLIST_ENTRY(Qcow2ZoneListEntry) imp_open_zone_entry;
> +QLIST_ENTRY(Qcow2ZoneListEntry) closed_zone_entry;
Where is closed_zone_entr
On Thu, Nov 02, 2023 at 06:00:22PM -0300, Daniel Henrique Barboza wrote:
> Sunil,
>
>
> While doing unrelated work (running Gitlab on my series built on top of
> current riscv-to-apply.next), I hit the following error:
>
> https://gitlab.com/danielhb/qemu/-/jobs/5448178994
>
> ==
>
> 4
On Wed, Oct 25, 2023 at 5:36 AM Markus Armbruster wrote:
>
> Pylint warns:
>
> tests/qapi-schema/test-qapi.py:139:13: W1514: Using open without
> explicitly specifying an encoding (unspecified-encoding)
> tests/qapi-schema/test-qapi.py:143:13: W1514: Using open without
> explicitly speci
Add IMSIC structure in MADT when IMSIC is configured.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 35 +++
1 file changed, 35 in
Add PLIC structures for each socket in the MADT when system is
configured with PLIC as the external interrupt controller.
Signed-off-by: Haibo Xu
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
--
Add APLIC structures for each socket in the MADT when system is configured
with APLIC as the external wired interrupt controller.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-
Add basic IO controllers and devices like PCI, VirtIO and UART in the
ACPI namespace.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 79 ++
ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit
and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of
making these values machine specific, create properties for the GPEX
host bridge with default value 0. During initialization, the firmware
can initialize
With common function to add virtio in DSDT created now, update microvm
code also to use it instead of duplicate code.
Suggested-by: Andrew Jones
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/i386/acpi-microvm.c | 15 ++-
1 file changed, 2
MMU type information is available via MMU node in RHCT. Add this node in
RHCT.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 36 +
Update the GPEX host bridge properties related to MMIO ranges with
values set for the virt machine.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt.c | 47 -
inclu
Some macros and static function related to IMSIC are defined in virt.c.
They are required in virt-acpi-build.c. So, make them public.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/risc
This series primarily enables external interrupt controllers (AIA and PLIC)
in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and
MMU related information.
Below ECRs for these changes are approved by ASWG and will be
available in next ACPI spec release.
1) MADT (AIA) -
https
When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
block size for those extensions need to be communicated via CMO node in
RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: A
Update the RINTC structure in MADT with AIA related fields.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 43 ++
1 file chang
RISC-V also needs to create the virtio in DSDT in the same way as ARM.
So, instead of duplicating the code, move this function to the device
specific file which is common across architectures.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Andrew
RISC-V also needs to use the same code to create fw_cfg in DSDT. So,
avoid code duplication by moving the code in arm and riscv to a device
specific file.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew
On Wed, Oct 25, 2023 at 6:10 AM Markus Armbruster wrote:
>
> Pylint advises:
>
> docs/sphinx/qapidoc.py:518:12: W0707: Consider explicitly re-raising
> using 'raise ExtensionError(str(err)) from err' (raise-missing-from)
>
> From its manual:
>
> Python's exception chaining shows the trace
On Thu, Nov 2, 2023 at 11:50 AM Stefan Berger wrote:
>
>
>
> On 10/31/23 00:00, Joelle van Dyne wrote:
> > This logic is similar to TPM TIS ISA device. Since TPM CRB can only
> > support TPM 2.0 backends, we check for this in realize.
>
> The problem on x86_64 is that the creation of the ACPI does
Hi, Taylor!:) Always nice to see your name pop up here. The patches seem
to have been sent as attachments for whatever reason.
/ Anton
We have two instances of the setting/clearing a MISA bit from
env->misa_ext and env->misa_ext_mask pattern. And the next patch will
end up adding one more.
Create a helper to avoid code repetition.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Rev
KVM does not have the means to support enabling the rva22u64 profile.
The main reasons are:
- we're missing support for some mandatory rva22u64 extensions in the
KVM module;
- we can't make promises about enabling a profile since it all depends
on host support in the end.
We'll revisit this
The profile support is handling multi-letter extensions only. Let's add
support for MISA bits as well.
We'll go through every known MISA bit. If the profile doesn't declare
the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext
and env->misa_ext_mask.
Now that we're setting prof
zic64b is defined in the RVA22U64 profile [1] as a named feature for
"Cache blocks must be 64 bytes in size, naturally aligned in the address
space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64
profile mandates this feature, meaning that applications using this
profile expects 64 by
Named features (zic64b the sole example at this moment) aren't expose to
users, thus we need another way to expose them.
Go through each named feature, get its boolean value, do the needed
conversions (bool to qbool, qbool to QObject) and add it to output dict.
Another adjustment is needed: named
We already track user choice for multi-letter extensions because we
needed to honor user choice when enabling/disabling extensions during
realize(). We refrained from adding the same mechanism for MISA
extensions since we didn't need it.
Profile support requires tne need to check for user choice f
Previous patches added several g_hash_table_insert() patterns. Add two
helpers, one for each user hash, to make the code cleaner.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/tcg/tcg-cpu.c | 28
1 file changed, 16 insertions(+),
RVG behaves like a profile: a single flag enables a set of bits. Right
now we're considering user choice when handling RVG and zicsr/zifencei
and ignoring user choice on MISA bits.
We'll add user warnings for profiles when the user disables its
mandatory extensions in the next patch. We'll do the
The TCG emulation implements all the extensions described in the
RVA22U64 profile, both mandatory and optional. The mandatory extensions
will be enabled via the profile flag. We'll leave the optional
extensions to be enabled by hand.
Given that this is the first profile we're implementing in TCG w
Enabling a profile and then disabling some of its mandatory extensions
is a valid use. It can be useful for debugging and testing. But the
common expected use of enabling a profile is to enable all its mandatory
extensions.
Add an user warning when mandatory extensions from an enabled profile
are
This CPU was suggested by Alistair [1] and others during the profile
design discussions. It consists of the bare 'rv64i' CPU with rva22u64
enabled by default, like an alias of '-cpu rv64i,rva22u64=true'.
Users now have an even easier way of consuming this user-mode profile by
doing '-cpu rva22u64'
Expose all profile flags for all CPUs when executing
query-cpu-model-expansion. This will allow callers to quickly determine
if a certain profile is implemented by a given CPU. This includes vendor
CPUs - the fact that they don't have profile user flags doesn't mean
that they don't implement the pr
There's no gain in allowing the 'max' CPU to support profiles, since it
already contains everything that QEMU can support. And we'll open the
door for 'unorthodox' stuff like users disabling profiles of the 'max'
CPU.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/tcg/tcg-cpu.c | 16 +++
The rva22U64 profile, described in:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles
Contains a set of CPU extensions aimed for 64-bit userspace
applications. Enabling this set to be enabled via a single user flag
makes it convenient to enable a predictable set of fe
We don't have any form of a 'bare bones' CPU. rv64, our default CPUs,
comes with a lot of defaults. This is fine for most regular uses but
it's not suitable when more control of what is actually loaded in the
CPU is required.
A bare-bones CPU would be annoying to deal with if not by profile
suppor
We'll add a new bare CPU type that won't have any default priv_ver. This
means that the CPU will default to priv_ver = 0, i.e. 1.10.0.
At the same we'll allow these CPUs to enable extensions at will, but
then, if the extension has a priv_ver newer than 1.10, we'll end up
disabling it. Users will t
QEMU already implements zicbom (Cache Block Management Operations) and
zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv:
add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for
what would be the instructions for zicbop (Cache Block Prefetch
Operations), which are
We want to add a new CPU type for bare CPUs that will inherit specific
traits of the 2 existing types:
- it will allow for extensions to be enabled/disabled, like generic
CPUs;
- it will NOT inherit defaults, like vendor CPUs.
We can make this conditions met by adding an explicit type for the
Hi,
In this version two new patches were added, both while discussing v6
with Alistair:
- new 'rva22u64' CPU. This is a CPU suggested by Alistair and others to
allow users to use a profile without having to deal with profile
enablement. This is done in patch 18;
- 'max' CPU profile restricti
Our current logic in get/setters of MISA and multi-letter extensions
works because we have only 2 CPU types, generic and vendor, and by using
"!generic" we're implying that we're talking about vendor CPUs. When adding
a third CPU type this logic will break so let's handle it beforehand.
In set_mis
Ping. Running out of days before soft-freeze. :-)
r~
On 10/28/23 12:44, Richard Henderson wrote:
Expose a pair of comparison operators that map to the "test"
comparison that is available on many architectures.
Changes for v2:
* Add TCGCond to tcg_target_const_match.
This fixes a long
Sunil,
While doing unrelated work (running Gitlab on my series built on top of
current riscv-to-apply.next), I hit the following error:
https://gitlab.com/danielhb/qemu/-/jobs/5448178994
==
4/257 ERROR:../tests/qtest/bios-tables-test.c:535:test_acpi_asl: assertion
failed: (all_tables
binstlsT1oUDf.bin
Description: test/plain
binQUp8uBOBfS.bin
Description: test/plain
binJqsrgMI63R.bin
Description: test/plain
binBoZeeZ311a.bin
Description: test/plain
(+cc qemu-devel)
On Tue, 2023-10-24 at 12:07 +0200, Heiko Carstens wrote:
> Qemu's SCLP implementation incorrectly reports that it supports CPU
> reconfiguration. If a guest issues a CPU reconfiguration request it
> is rejected as invalid command.
>
> Fix the SCLP_HAS_CPU_INFO mask, and remove th
On 10/31/23 00:00, Joelle van Dyne wrote:
This logic is similar to TPM TIS ISA device. Since TPM CRB can only
support TPM 2.0 backends, we check for this in realize.
The problem on x86_64 is that the creation of the ACPI doesn't seem to
get invoked. The device then ends up not working under
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20231028122415.14869-4-shen...@gmail.com
Signed-off-by: Peter Maydell
---
hw/misc/imx7_snvs.c | 5 +
hw/misc/trace-events | 4
2 files changed, 9 insertions(+)
diff --git a/hw/mis
In qemu-plugin.h, mark all API functions as __declspec(dllexport) when
compiling the executables, and as __declspec(dllimport) when being used
to compile plugins against.
Signed-off-by: Greg Manning
---
include/qemu/qemu-plugin.h | 50 +++---
1 file changed, 47 in
Marc-André Lureau writes:
> Hi Stephen
>
> On Tue, Sep 19, 2023 at 3:32 AM Stephen Brennan
> wrote:
>>
>> The flattened format (currently output by QEMU) is used by makedumpfile
>> only when it is outputting a vmcore to a file which is not seekable. The
>> flattened format functions essentially
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20231028122415.14869-5-shen...@gmail.com
[PMM: Add "Hz" unit indicator to frequency traces]
Signed-off-by: Peter Maydell
---
hw/misc/imx6_ccm.c | 41 ++-
Convert the docs/specs/vmw_pvscsi-spec.txt file to rST format.
This conversion includes some minor wordsmithing of the text
to fix some grammar nits.
Signed-off-by: Peter Maydell
Reviewed-by: Thomas Huth
Message-id: 20230927151205.70930-2-peter.mayd...@linaro.org
---
MAINTAINERS
Add basic IO controllers and devices like PCI, VirtIO and UART in the
ACPI namespace.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 79 ++
From: Hans-Erik Floryd
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Hans-Erik Floryd
Message-id: 20231030151528.1138131-4-hans-erik.flo...@rt-labs.com
Signed-off-by: Peter Maydell
---
include/hw/char/stm32f2xx_usart.h | 10 ++
From: Thomas Huth
gic_internal.h is already covered by the "ARM cores" section.
Let's adapt the entry with a wildcard to cover gicv3_internal.h, too.
Signed-off-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20231027060709.242388-1-th...@redhat.com
Signed-off-by: Peter Maydell
Greg Manning writes:
> allow plugins to be enabled in the configure script on windows. Also,
> add the qemu_plugin_api.lib to the installer.
>
> Signed-off-by: Greg Manning
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Greg Manning writes:
> The lockstep plugin uses unix sockets and would require a different
> communication mechanism to work on Windows.
>
> Signed-off-by: Greg Manning
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20231028122415.14869-2-shen...@gmail.com
Signed-off-by: Peter Maydell
---
hw/watchdog/wdt_imx2.c | 24 ++--
hw/watchdog/trace-events | 4
2 files changed, 22 inse
Greg Manning writes:
> Generate a qemu_plugin_api.lib delay import lib on windows, for
> windows qemu plugins to link against.
>
> Implement an example dll load fail hook to link up the API functions
> correctly when a plugin is loaded on windows.
>
> Update the build scripts for the test and exa
In a two-stage translation, the result of the BTI guarded bit should
be the guarded bit from the first stage of translation, as there is
no BTI guard information in stage two. Our code tried to do this,
but got it wrong, because we currently have two fields where the GP
bit information might live
Greg Manning writes:
> In qemu-plugin.h, mark all API functions as __declspec(dllexport) when
> compiling the executables, and as __declspec(dllimport) when being used
> to compile plugins against.
>
> Signed-off-by: Greg Manning
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Le
On Thu, Nov 02, 2023 at 03:25:25PM +0100, Markus Armbruster wrote:
> Juan Quintela writes:
>
> > Markus Armbruster wrote:
> >> Peter Xu writes:
> >>
> >>> On Wed, Oct 11, 2023 at 04:21:02PM +0200, Markus Armbruster wrote:
> >
> >>> IIRC both of them used to be the goals: either allow compat pro
Convert docs/specs/standard-vga.txt to rST format.
Signed-off-by: Peter Maydell
Message-id: 20230927151205.70930-6-peter.mayd...@linaro.org
Reviewed-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
docs/specs/index.rst| 1 +
docs/specs/standard-vga.rst | 94 ++
ommit 6c9ae1ce82b65faa3f266fd103729878cf11e07e:
Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging
(2023-11-01 06:58:11 +0900)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20231102
for you to fetc
Some macros and static function related to IMSIC are defined in virt.c.
They are required in virt-acpi-build.c. So, make them public.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/risc
The lockstep plugin uses unix sockets and would require a different
communication mechanism to work on Windows.
Signed-off-by: Greg Manning
---
contrib/plugins/Makefile | 6 ++
1 file changed, 6 insertions(+)
diff --git a/contrib/plugins/Makefile b/contrib/plugins/Makefile
index 751fa38619.
Convert docs/specs/pvpanic.txt to rST format.
Signed-off-by: Peter Maydell
Message-id: 20230927151205.70930-5-peter.mayd...@linaro.org
Reviewed-by: Philippe Mathieu-Daudé
---
docs/specs/index.rst| 1 +
docs/specs/{pvpanic.txt => pvpanic.rst} | 41 -
Currently for each button on the device we have a
StellarisGamepadButton struct which has the irq, keycode and pressed
state for it. When we convert to qdev, the qdev property and GPIO
APIs are going to require that we have separate arrays for the irqs
and keycodes. Convert from array-of-structs
Convert docs/specs/edu.txt to rST format.
Signed-off-by: Peter Maydell
Reviewed-by: Thomas Huth
Message-id: 20230927151205.70930-3-peter.mayd...@linaro.org
---
MAINTAINERS | 1 +
docs/specs/{edu.txt => edu.rst} | 84 -
docs/specs/index.rst
From: Philippe Mathieu-Daudé
Instead of passing the CPU index and resolving it,
use a QOM link to directly pass the CPU.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20231030083706.63685-1-phi...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/pxa2xx_gpio.c
From: Bernhard Beschow
Let the trace messages slightly deviate from the function names
("smb" -> "smbus") being traced in order to avoid conflights with the SMB
protocol.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Corey Minyard
Message-id: 20231028122415.148
From: Hans-Erik Floryd
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Hans-Erik Floryd
Message-id: 20231030151528.1138131-2-hans-erik.flo...@rt-labs.com
Signed-off-by: Peter Maydell
---
hw/char/stm32f2xx_usart.c | 28 +++
The AArch64 ELF hwcap2 field is 64 bits, but our get_elf_hwcap2()
works with uint32_t, so it accidentally fails to report any hwcaps
over bit 31. Use uint64_t here.
The Arm hwcap2 is only 32 bits (because the ELF format makes these
fields be the size of "long" in the ABI), but since it shares the
From: Tong Ho
Signed-off-by: Tong Ho
Message-id: 20231031184611.3029156-4-tong...@amd.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
tests/qtest/xlnx-versal-trng-test.c | 485
tests/qtest/meson.build | 2 +-
2 files changed, 486 inse
Most of the registers used by the FEAT_MOPS instructions cannot use
31 as a register field value; this is CONSTRAINED UNPREDICTABLE to
NOP or UNDEF (we UNDEF). However, it is permitted for the "source
value" register for the memset insns SET* to be 31, which (as usual
for most data-processing insn
Rename the structs in stellaris_gamepad.c to our now-standard
CamelCase convention.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-id: 20231030114802.3671871-3-peter.mayd...@linaro.org
---
hw/input/stellaris_gamepad.c | 22 +++
Now that we have converted to qdev, we can use the newer
qemu_input_handler_register() API rather than the legacy
qemu_add_kbd_event_handler().
Since we only have one user, take the opportunity to convert
from scancodes to QCodes, rather than using
qemu_input_key_value_to_scancode() (which adds an
Convert docs/specs/vmgenid.txt to rST format.
Reviewed-by: Ani Sinha
Signed-off-by: Peter Maydell
Message-id: 20230927151205.70930-9-peter.mayd...@linaro.org
---
MAINTAINERS| 2 +-
docs/specs/index.rst | 1 +
docs/specs/vmgenid.rst | 246 +++
From: Tong Ho
This adds a non-cryptographic grade implementation of the
model for the True Random Number Generator (TRNG) component
in AMD/Xilinx Versal device family.
This implements all 3 modes defined by the actual hardware
specs, all of which selectable by guest software at will
at anytime:
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