From: Helge Deller
The following changes since commit 7425b6277f12e82952cede1f531bfc689bf77fb1:
Merge tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2023-12-27 05:15:32 -0500)
are available in the Git repository at:
https://github.com/hdeller/qemu-hppa.git
From: Helge Deller
Move functionality to set IOR and ISR on fault into own
function. This will be used by follow-up patches.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
---
target/hppa/cpu.h| 1 +
target/hppa/mem_helper.c | 23 ---
2 files changed,
From: Helge Deller
Put correct values (depending on CPU arch) into IOR and ISR on fault.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
---
target/hppa/cpu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index
From: Helge Deller
Fix the address translation for PDC space on PA2.0 if PSW.W=0.
Basically, for any address in the 32-bit PDC range from 0xf000 to
0xf100 keep the lower 32-bits and just set the upper 32-bits to
0xfff0.
This mapping fixes the emulated power button in PDC space for
From: Helge Deller
The value of unwind_breg may reference register %r0, but we need to avoid
accessing gr0 directly and use the value 0 instead.
At runtime I've seen unwind_breg being zero with the Linux kernel when
rfi is used to jump to smp_callin().
Signed-off-by: Helge Deller
Reviewed-by:
From: Helge Deller
Recognize the qemu --nodefaults option, which will disable the
following default devices on hppa:
- lsi53c895a SCSI controller,
- artist graphics card,
- LASI 82596 NIC,
- tulip PCI NIC,
- second serial PCI card,
- USB OHCI controller.
Adding this option is very useful to
From: Helge Deller
NetBSD accesses some astro and elroy registers which aren't accessed
by Linux yet. Add emulation for those registers to allow NetBSD to
boot further.
Please note that this patch is not sufficient to completely boot up
NetBSD on the 64-bit C3700 machine yet.
Signed-off-by:
From: Helge Deller
The physical hardware allows DIMMs of 4 MB size and above, allowing up
to 3840 MB of memory, but is restricted by setup code to 3 GB.
Increase the limit to allow up to the maximum amount of memory.
Btw. the memory area from 0xf000. to 0x. is reserved by
the
From: Helge Deller
Put correct values (depending on CPU arch) into IOR and ISR on fault.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
---
target/hppa/op_helper.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/hppa/op_helper.c
From: Helge Deller
The various operating systems (e.g. Linux, NetBSD) have issues
mapping the power button when it's stored in page zero.
NetBSD even crashes, because it fails to map that page and then
accesses unmapped memory.
Since we now have a consistent memory mapping of PDC in 32-bit
and
On 1/12/24 21:20, Alex Bennée wrote:
Pierrick Bouvier writes:
On 1/11/24 19:57, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 11/1/24 15:23, Pierrick Bouvier wrote:
For now, it simply performs instruction, bb and mem count, and ensure
that inline vs callback versions have the same result.
Rob Bradford wrote:
I'm using table 27.1 in the published PDF which is the PDF in this
release:
https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC
It looks like it was removed in this commit (which is a set of
backports):
We would retain the previously documented
When zero-copy usage of indirect descriptors buffer table isn't
possible, library gather scattered memory chunks in a local copy.
This commit fixes the issue with pointer arithmetic for the local copy
buffer.
Signed-off-by: Temir Zharaspayev
---
subprojects/libvhost-user/libvhost-user.c | 11
When zero-copy usage of indirect descriptors buffer table isn't
possible, library gather scattered memory chunks in a local copy.
This commit fixes the issue with pointer arithmetic for the local copy
buffer.
Signed-off-by: Temir Zharaspayev
---
subprojects/libvduse/libvduse.c | 11 ++-
Hello! I have found a problem with virtqueue_read_indirect_desc function, which
was advancing pointer to struct as it was a byte pointer, so every element
comming after first chunk would be copied somewhere out of buffer.
As I understand this is cold path, but nevertheless worth fixing.
Also,
On 1/12/24 16:05, Richard Henderson wrote:
So by default qemu ships the vdso binary. How can one rebuild it ?
From skimming the build files it seems following ought to do it
make update-linux-vdso
with a prior configure cmd like below with PATH pointing to the
On 1/13/24 10:37, Vineet Gupta wrote:
On 1/12/24 13:35, Richard Henderson wrote:
On 1/12/24 08:49, Vineet Gupta wrote:
Hi Richard, Alistair
On 10/30/23 14:17, Richard Henderson wrote:
diff --git a/linux-user/riscv/Makefile.vdso b/linux-user/riscv/Makefile.vdso
new file mode 100644
index
On 1/12/24 15:37, Vineet Gupta wrote:
> Now if only I could rebuild vdso/qemu with the revert of following and
> the reg size change.
> 2021-07-06 468c1bb5cac9 linux-user/riscv: Add vdso
And is there way to debug qemu internals in this regard, like a
developer toggle on steroids or
On 1/12/24 13:35, Richard Henderson wrote:
> On 1/12/24 08:49, Vineet Gupta wrote:
>> Hi Richard, Alistair
>>
>> On 10/30/23 14:17, Richard Henderson wrote:
>>> diff --git a/linux-user/riscv/Makefile.vdso b/linux-user/riscv/Makefile.vdso
>>> new file mode 100644
>>> index 00..2c257dbfda
On 1/13/24 10:15, Helge Deller wrote:
On 1/13/24 00:11, Richard Henderson wrote:
On 1/13/24 09:44, Helge Deller wrote:
I think it would be better to pass this as a parameter to create_fw_cfg, or
to drop the translated FW_CFG_IO_BASE parameter and merely pass in translate
itself.
Like this?
On 1/13/24 00:11, Richard Henderson wrote:
On 1/13/24 09:44, Helge Deller wrote:
I think it would be better to pass this as a parameter to create_fw_cfg, or
to drop the translated FW_CFG_IO_BASE parameter and merely pass in translate
itself.
Like this?
The various operating systems (e.g.
On 1/13/24 09:44, Helge Deller wrote:
I think it would be better to pass this as a parameter to create_fw_cfg, or
to drop the translated FW_CFG_IO_BASE parameter and merely pass in translate
itself.
Like this?
The various operating systems (e.g. Linux, NetBSD) have issues
mapping the power
On Fri, 12 Jan 2024 13:35:39 PST (-0800), Richard Henderson wrote:
> On 1/12/24 08:49, Vineet Gupta wrote:
>> Hi Richard, Alistair
>>
>> On 10/30/23 14:17, Richard Henderson wrote:
>>> diff --git a/linux-user/riscv/Makefile.vdso b/linux-user/riscv/Makefile.vdso
>>> new file mode 100644
>>> index
Simplify the exec migration code by using list utility functions.
As a side effect, this also fixes a minor memory leak. On function return,
"g_auto(GStrv) argv" frees argv and each element, which is wrong, because
the function does not own the individual elements. To compensate, the code
uses
On 1/13/24 08:38, Daniel Henrique Barboza wrote:
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 26 +
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
Signed-off-by: Steve Sistare
Reviewed-by: Marc-André Lureau
---
include/qapi/util.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/qapi/util.h b/include/qapi/util.h
index 81a2b13..e1b8b1d 100644
--- a/include/qapi/util.h
+++ b/include/qapi/util.h
@@ -56,4 +56,17 @@
Signed-off-by: Steve Sistare
Reviewed-by: Marc-André Lureau
---
tests/unit/meson.build| 1 +
tests/unit/test-strList.c | 80 +++
2 files changed, 81 insertions(+)
create mode 100644 tests/unit/test-strList.c
diff --git a/tests/unit/meson.build
Generalize hmp_split_at_comma() to take any delimiter string, rename
as strList_from_string(), and move it to util/strList.c.
No functional change.
Signed-off-by: Steve Sistare
---
include/monitor/hmp.h | 1 -
include/qemu/strList.h | 24
monitor/hmp-cmds.c | 19
Signed-off-by: Steve Sistare
Reviewed-by: Marc-André Lureau
---
include/qemu/strList.h | 6 ++
util/strList.c | 14 ++
2 files changed, 20 insertions(+)
diff --git a/include/qemu/strList.h b/include/qemu/strList.h
index 010237f..4b86aa6 100644
---
Add some handy string list functions for general use, and use them in
live migration functions. These will also be needed for cpr exec mode.
Changes in V4:
* added exec migration patch
Steve Sistare (5):
util: strList_from_string
qapi: QAPI_LIST_LENGTH
util: strv_from_strList
util:
On 1/13/24 08:38, Daniel Henrique Barboza wrote:
MAXSZ() returns the value in bytes. Now that we have access to vlenb
we don't need to compensate with a '-3' in the scale to use 'vlen'.
MAXSZ() now works as follows:
LMUL lmul=scale MAXSZ (vlenb >> -scale)
1 0 vlenb
2
> I think it would be better to pass this as a parameter to create_fw_cfg, or
> to drop the translated FW_CFG_IO_BASE parameter and merely pass in translate
> itself.
Like this?
The various operating systems (e.g. Linux, NetBSD) have issues
mapping the power button when it's stored in page
On 1/13/24 08:38, Daniel Henrique Barboza wrote:
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 11df226a00..628ef67d5f 100644
--- a/target/riscv/cpu.h
+++
On 1/13/24 08:38, Daniel Henrique Barboza wrote:
Use the new 'vlenb' CPU config to validate fractional LMUL. The original
comparison is done with 'vlen' and 'sew', both in bits. Use sew/8, or
sew in bytes, to do a direct comparison with vlenb.
Signed-off-by: Daniel Henrique Barboza
---
declare, but don't initialize the type of "type" to be QAPISchemaType -
and allow the value to be initialized during check(). This creates a
form of delayed initialization for QAPISchemaType objects where the
static typing only represents the fully-realized object, which occurs
after check() has
Dict[str, object] is a stricter type, but with the way that code is
currently arranged, it is infeasible to enforce this strictness.
In particular, although expr.py's entire raison d'être is normalization
and type-checking of QAPI Expressions, that type information is not
"remembered" in any
QAPISchemaInfo instances are sometimes defined as an Optional
field/argument because built-in definitions don't *have* a source
definition. As a consequence, there are a few places where we need to
assert that it's present because the root entity definition can only
enforce that it is "Optional".
With strict typing enabled, these runtime statements aren't necessary
anymore; we can prove them statically.
Signed-off-by: John Snow
---
scripts/qapi/schema.py | 27 ---
1 file changed, 27 deletions(-)
diff --git a/scripts/qapi/schema.py b/scripts/qapi/schema.py
index
Hi! This branch has some comical name like python-qapi-cleanup-pt6-v2
but, simply, it finishes what I started and statically types all of the
QAPI generator code.
Patches 1-16 fix minor nits or typing issues,
Patch 17 adds type hints with no runtime changes,
Patch 18 turns on type checking with
This field should always be present and defined after check() is
called. Declare the property but allow its initialization to be delayed
until check() so that it can be typed without the use of `Optional`.
This helps simplify typing by avoiding the need to interrogate the value
for None at
There are two related changes here:
(1) We need to perform type narrowing for resolving the type of
tag_member during check(), and
(2) tag_member is a delayed initialization field, but we can hide it
behind a property that raises an Exception if it's called too
early. This simplifies
lookup_type() is capable of returning None, but some callers aren't
prepared for that and assume it will always succeed.
Use the must-not-fail variant resolve_type() instead, which guarantees
that the return type will not be None.
Signed-off-by: John Snow
---
scripts/qapi/introspect.py | 4
allow resolve_type to be used for both built-in and user-specified
type definitions. In the event that the type cannot be resolved, assert
that 'info' and 'what' were both provided in order to create a usable
QAPISemError.
In practice, 'info' will only be None for built-in definitions, which
This patch can be rolled in with the previous one once the series is
ready for merge, but for work-in-progress' sake, it's separate here.
Signed-off-by: John Snow
---
scripts/qapi/mypy.ini | 5 -
1 file changed, 5 deletions(-)
diff --git a/scripts/qapi/mypy.ini b/scripts/qapi/mypy.ini
Adjust the expression at the callsite to eliminate weak type
introspection that believes this value can resolve to QAPISourceInfo; it
cannot.
Signed-off-by: John Snow
---
scripts/qapi/schema.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/qapi/schema.py
We already take care to perform some type narrowing for arg_type and
ret_type, but not in a way where mypy can utilize the result once we add
type hints, e.g.:
qapi/schema.py:833: error: Incompatible types in assignment (expression
has type "QAPISchemaType", variable has type
This patch only adds type hints, which aren't utilized at runtime and
don't change the behavior of this module in any way.
In a scant few locations, type hints are removed where no longer
necessary due to inference power from typing all of the rest of
creation; and any type hints that no longer
This function is a bit hard to type as-is; mypy needs some assertions to
assist with the type narrowing.
Signed-off-by: John Snow
---
scripts/qapi/schema.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/scripts/qapi/schema.py b/scripts/qapi/schema.py
index
differentiate between "actively in the process of checking" and
"checking has completed". This allows us to clean up the types of some
internal fields such as QAPISchemaObjectType's members field which
currently uses "None" as a test for determining if check has been run
already or not.
This
QAPISchemaVariant's "variants" field is typed as
List[QAPISchemaVariant], where the typing for QAPISchemaVariant allows
its type field to be any QAPISchemaType.
However, QAPISchemaVariant expects that all of its variants contain the
narrower QAPISchemaObjectType. This relationship is enforced at
Include entities don't have names, but we generally expect "entities" to
have names. Reclassify all entities with names as *definitions*, leaving
the nameless include entities as QAPISchemaEntity instances.
This is primarily to help simplify typing around expectations of what
callers expect for
Suggested-by: Markus Armbruster
Signed-off-by: John Snow
---
scripts/qapi/pylintrc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/scripts/qapi/pylintrc b/scripts/qapi/pylintrc
index 90546df5345..78b63af4df6 100644
--- a/scripts/qapi/pylintrc
+++
With this patch, pylint is happy with the file, so enable it in the
configuration.
Signed-off-by: John Snow
Reviewed-by: Markus Armbruster
---
scripts/qapi/pylintrc | 5 -
scripts/qapi/schema.py | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git
These methods should always return a str, it's only the default abstract
implementation that doesn't. They can be marked "abstract", which
requires subclasses to override the method with the proper return type.
Signed-off-by: John Snow
---
scripts/qapi/schema.py | 9 ++---
1 file changed, 6
On 1/13/24 09:23, Helge Deller wrote:
Please adjust the code comment that immediately precedes this, not just
within the commit message.
Like this: ?
Yes, thanks.
Reviewed-by: Richard Henderson
+/*
+ * PDC address space:
+ * Figures H-10 and H-11 of the parisc2.0
On 1/13/24 01:27, Pierrick Bouvier wrote:
On 1/12/24 02:04, Richard Henderson wrote:
On 1/12/24 01:23, Pierrick Bouvier wrote:
Instead of working on a fixed memory location, allow to index it based
on cpu_index and a given offset (ptr + cpu_index * offset).
Current semantic is not modified as
> Please adjust the code comment that immediately precedes this, not just
> within the commit message.
Like this: ?
Fix the address translation for PDC space on PA2.0 if PSW.W=0.
Basically, for any address in the 32-bit PDC range from 0xf000 to
0xf100 keep the lower 32-bits and just set
On 1/12/24 21:29, del...@kernel.org wrote:
From: Helge Deller
Put correct values (depending on CPU arch) into IOR and ISR on fault.
Signed-off-by: Helge Deller
---
target/hppa/op_helper.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/12/24 21:29, del...@kernel.org wrote:
From: Helge Deller
Move functionality to set IOR and ISR on fault into own
function. This will be used by follow-up patches.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h| 1 +
target/hppa/mem_helper.c | 23 ---
2
On 1/12/24 21:29, del...@kernel.org wrote:
From: Helge Deller
Put correct values (depending on CPU arch) into IOR and ISR on fault.
Signed-off-by: Helge Deller
---
target/hppa/cpu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/12/24 21:29, del...@kernel.org wrote:
+static hwaddr soft_power_reg;
#define enable_lasi_lan() 0
@@ -45,7 +45,6 @@ static DeviceState *lasi_dev;
static void hppa_powerdown_req(Notifier *n, void *opaque)
{
-hwaddr soft_power_reg = HPA_POWER_BUTTON;
uint32_t
Reported-by: Vineet Gupta
Signed-off-by: Richard Henderson
---
linux-user/riscv/vdso-32.so | Bin 2900 -> 2900 bytes
linux-user/riscv/vdso-64.so | Bin 3856 -> 3856 bytes
linux-user/riscv/vdso.S | 2 +-
3 files changed, 1 insertion(+), 1 deletion(-)
diff --git
On 1/12/24 21:29, del...@kernel.org wrote:
From: Helge Deller
Fix the address translation for PDC space on PA2.0 if PSW.W=0.
Basically, for any address in the 32-bit PDC range from 0xf000 to
0xf100 keep the lower 32-bits and just set the upper 32-bits to
0xfff0.
This mapping fixes
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 26 +
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 804cfd6c7f..3782d0fa2f 100644
MAXSZ() returns the value in bytes. Now that we have access to vlenb
we don't need to compensate with a '-3' in the scale to use 'vlen'.
MAXSZ() now works as follows:
LMUL lmul=scale MAXSZ (vlenb >> -scale)
1 0 vlenb
2 1 vlenb << 1
4 2 vlenb << 2
8
On Fri, 12 Jan 2024 07:04:59 -0800
Steve Sistare wrote:
> Allow cpr-reboot for vfio if the guest is in the suspended runstate. The
> guest drivers' suspend methods flush outstanding requests and re-initialize
> the devices, and thus there is no device state to save and restore. The
> user is
Use ctx->cfg_ptr->vlenb instead of ctx->cfg_ptr->vlen / 8.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc
Use the new 'vlenb' CPU config to validate fractional LMUL. The original
comparison is done with 'vlen' and 'sew', both in bits. Use sew/8, or
sew in bytes, to do a direct comparison with vlenb.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 9 ++---
1 file
Use s->cfg_ptr->vlenb instead of s->cfg_ptr->vlen / 8.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvvk.c.inc | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc
Use 'cpu->cfg.vlenb' instead of 'cpu->cfg.vlen >> 3'.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index
There is no need to keep both 'vlen' and 'vlenb'. All existing code
that requires 'vlen' is retrieving it via 'vlenb << 3'.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 8 +++-
target/riscv/cpu_cfg.h | 1 -
target/riscv/tcg/tcg-cpu.c | 4 +++-
3 files changed,
There's no need to calculate 'vlmax'. We're garanteeing that 'vl_eq_vlmax'
is true, and we can retrieve 'vl' via 'cpu_vl'.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 29 -
1 file changed, 19 insertions(+), 10 deletions(-)
diff
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 11df226a00..628ef67d5f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -692,7 +692,8 @@ static inline
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/gdbstub.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 58b3ace0fe..5ab0abda19 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -130,7
Our usage of 'vlenb' is overwhelming superior than the use of 'vlen'.
We're using 'vlenb' most of the time, having to do 'vlen >> 3' or
'vlen / 8' in every instance.
In hindsight we would be better if the 'vlenb' property was introduced
instead of 'vlen'. That's not what happened, and now we
As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
reading CSR_VLENB.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 674ea075a4..5c8d22452b 100644
Use s->cfg_ptr->vlenb instead of "s->cfg_ptr->vlen / 8" and
"s->cfg_ptr->vlen >> 3".
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 140
1 file changed, 70 insertions(+), 70 deletions(-)
diff --git
Hi,
When working in the KVM Vector support, adding support for the 'vlenb'
register, I noticed that we have a *LOT* of code that uses 'vlenb', in a
far greater amount than 'vlen', and we resort to do 'vlen >> 3' every
time we need 'vlenb'. The conclusion is that we're storing the wrong
state - we
On 1/12/24 08:49, Vineet Gupta wrote:
Hi Richard, Alistair
On 10/30/23 14:17, Richard Henderson wrote:
diff --git a/linux-user/riscv/Makefile.vdso b/linux-user/riscv/Makefile.vdso
new file mode 100644
index 00..2c257dbfda
--- /dev/null
+++ b/linux-user/riscv/Makefile.vdso
@@ -0,0 +1,15
Philippe Mathieu-Daudé writes:
> Move the 'has_el2' and 'has_el3' properties to the abstract
> QOM parent.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/cpu/cortex_mpcore.h | 5 +
> hw/arm/exynos4210.c| 10 --
> hw/arm/vexpress.c | 6 ++
On Fri, 12 Jan 2024 12:57:22 PST (-0800), r...@rivosinc.com wrote:
Commit f4e1168198 (linux-user: Split out host_sig{segv,bus}_handler)
introduced a bug, when returning from host_sigbus_handler the PC is
So we should probably have a
Fixes: f4e1168198 ("linux-user: Split out
Commit f4e1168198 (linux-user: Split out host_sig{segv,bus}_handler)
introduced a bug, when returning from host_sigbus_handler the PC is
never set. Thus cpu_loop_exit_restore is called with a zero PC and
we immediate get a SIGSEGV.
Signed-off-by: Robbin Ehn
---
linux-user/signal.c | 5 +++--
1
On Fri, Jan 12, 2024 at 01:15:28PM +, Mark Cave-Ayland wrote:
> The setting of DMA_STAT_DONE at the end of a DMA transfer can be configured to
> generate an interrupt, however the Linux driver manually checks for
> DMA_STAT_DONE
> being set and if it is, considers that a DMA transfer has
On Fri, Jan 12, 2024 at 01:15:29PM +, Mark Cave-Ayland wrote:
> Even though the BLAST command isn't fully implemented in QEMU, the
> DMA_STAT_BCMBLT
> bit should be set after the command has been issued to indicate that the
> command
> has completed.
>
> This fixes an issue with the DC390
On Fri, Jan 12, 2024 at 01:15:27PM +, Mark Cave-Ayland wrote:
> The am53c974/dc390 PCI interrupt has two separate sources: the first is from
> the
> internal ESP device, and the second is from the PCI DMA transfer logic.
>
> Update the ESP interrupt handler so that it sets DMA_STAT_SCSIINT
On Fri, Jan 12, 2024 at 01:15:26PM +, Mark Cave-Ayland wrote:
> The current code in esp_pci_dma_memory_rw() sets the DMA address to the value
> of the DMA_SPA (Starting Physical Address) register which is incorrect: this
> means that for each callback from the SCSI layer the DMA address is set
On 1/12/24 21:29, del...@kernel.org wrote:
From: Helge Deller
Recognize the qemu --nodefaults option, which will disable the
following default devices on hppa:
- lsi53c895a SCSI controller,
- artist graphics card,
- LASI 82596 NIC,
- tulip PCI NIC,
- second serial PCI card,
- USB OHCI
Cédric Le Goater writes:
> On 1/10/24 14:19, Fabiano Rosas wrote:
>> Markus Armbruster writes:
>>
>>> Peter Xu writes:
>>>
On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Fabiano,
>
> On 9/1/24 21:21, Fabiano Rosas wrote:
>> Cédric Le Goater
On Thu, Dec 28, 2023 at 11:45:18AM -0600, x...@trimaso.com.mx wrote:
> I noticed something weird when using "-cpu host" with Windows vms.
> First, I always use it along with ",hv_passthrough" as well.
>
> First, performance: since some years ago, since prior to qemu 6.2 until
> latest 8.2, win10
On Wed, 10 Jan 2024 at 14:38, Bohdan Kostiv wrote:
>
> Hello,
>
> I have faced an issue in using serial ports when I need to skip a couple of
> ports in the CLI.
>
> For example the ARM machine netduinoplus2 supports up to 7 UARTS.
> Following case works (the first UART is used to send data in
On Tue, 9 Jan 2024 at 19:44, Inès Varhol wrote:
>
> This patch adds a new device STM32L4x5 SYSCFG device and is part
> of a series implementing the STM32L4x5 with a few peripherals.
>
Applied to target-arm.next, thanks.
-- PMM
On Tue, 9 Jan 2024 at 16:07, Inès Varhol wrote:
>
> This patch adds a new device STM32L4x5 EXTI device and is part
> of a series implementing the STM32L4x5 with a few peripherals.
>
Applied to target-arm.next, thanks.
-- PMM
On Thu, 11 Jan 2024 at 05:11, Gavin Shan wrote:
>
> It's found that some of the CPU type names in the array of valid
> CPU types are invalid because their corresponding classes aren't
> registered, as reported by Peter Maydell.
>
> [gshan@gshan build]$ ./qemu-system-arm -machine virt -cpu
On Tue, 9 Jan 2024 at 18:45, Samuel Tardieu wrote:
>
> Signed-off-by: Samuel Tardieu
> Fixes: ff68dacbc786 ("armv7m: Split systick out from NVIC")
> ---
> hw/timer/trace-events | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied to target-arm.next, thanks.
-- PMM
On Fri, Jan 12, 2024 at 05:47:17PM +0100, Thomas Huth wrote:
> The npcm7xx_watchdog_timer-test can take more than 60 seconds
> when running in the gitlab-CI, see for example:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/5890481174#L4756
>
> Bumping to 2 minutes will give more headroom.
>
>
On Fri, 12 Jan 2024 at 13:59, Alex Bennée wrote:
>
> The following changes since commit 3fab43d2f638b98765b0f8ef033ec93e3ea6b809:
>
> Merge tag 'firmware/edk2-20231213-pull-request' of
> https://gitlab.com/kraxel/qemu into staging (2024-01-11 15:19:42 +)
>
> are available in the Git
On Thu, 11 Jan 2024 at 17:00, Thomas Huth wrote:
>
> Hi Peter!
>
> The following changes since commit 34eac35f893664eb8545b98142e23d9954722766:
>
> Merge tag 'pull-riscv-to-apply-20240110' of
> https://github.com/alistair23/qemu into staging (2024-01-10 11:41:56 +)
>
> are available in
Pierrick Bouvier writes:
> On 1/11/24 19:57, Philippe Mathieu-Daudé wrote:
>> Hi Pierrick,
>> On 11/1/24 15:23, Pierrick Bouvier wrote:
>>> For now, it simply performs instruction, bb and mem count, and ensure
>>> that inline vs callback versions have the same result. Later, we'll
>>> extend it
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
tests/qtest/meson.build | 3 +-
tests/qtest/stm32l4x5_gpio-test.c | 319 ++
2 files changed, 321 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
diff --git
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/Kconfig | 3 +-
hw/arm/stm32l4x5_soc.c | 62 +++---
include/hw/arm/stm32l4x5_soc.h | 9 +
3 files changed, 60 insertions(+), 14 deletions(-)
diff --git a/hw/arm/Kconfig
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