Re: [PATCH v3 2/2] cxl/core: add poison creation event handler

Shiyang Ruan wrote: [..] > >> My expectation is MF_ACTION_REQUIRED is not appropriate for CXL event > >> reported errors since action is only required for direct consumption > >> events and those need not be reported through the device event queue. > > Got it. > > I'm not very sure about 'Host wri

[PATCH 4/4] disas/riscv: Support zcmop disassemble

Although in QEMU disassemble, we usually lift compressed instruction to an normal format when display the instruction name. For C.MOP.n, it is more reasonable to directly display its compressed name, because its behavior can be redefined by later extension. Signed-off-by: LIU Zhiwei --- disas/ri

[PATCH 3/4] target/riscv: Add zcmop extension

Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI xn, 0. Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions are defined to not write any re

[PATCH rfcv2 13/17] intel_iommu: add support for PASID-based device IOTLB invalidation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 hw/i386/intel_iommu.c | 50 ++ 2 files changed, 61 insertions(+) diff --git a/hw/i386/intel_iommu_internal.

[PATCH 2/4] disas/riscv: Support zimop disassemble

Signed-off-by: LIU Zhiwei --- disas/riscv.c | 100 ++ 1 file changed, 100 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index e236c8b5b7..4cd769f165 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -906,6 +906,46 @@ typedef enum {

[PATCH 1/4] target/riscv: Add zimop extension

Zimop extension defines an encoding space for 40 MOPs.The Zimop extension defines 32 MOP instructions named MOP.R.n, where n is an integer between 0 and 31, inclusive. The Zimop extension additionally defines 8 MOP instructions named MOP.RR.n, where n is an integer between 0 and 7. These 40 MOPs i

[PATCH rfcv2 10/17] intel_iommu: Process PASID-based iotlb invalidation

PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3

[PATCH 0/4] target/riscv: Implement May-Be-Operations(zimop) extension

The may be operation means that it has an initial behavior which can be redefined by later extensions to perform some other action. The May-Be-Operations includes two extension: zimop and zcmop. Zimop has 40 instructions, whose initial behavior is writing zero to the destination register. Zcmop,

[PATCH rfcv2 11/17] intel_iommu: Extract device IOTLB invalidation logic

From: Clément Mathieu--Drif This piece of code can be shared by both IOTLB invalidation and PASID-based IOTLB invalidation No functional changes intended. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 57 ++

[PATCH rfcv2 05/17] intel_iommu: Rename slpte to pte

From: Yi Liu Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation, rename slpte to pte to make it generic. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 ++- include/hw/i386/intel_iommu.h | 2 +- hw

[PATCH rfcv2 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode

According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 in scalable modern mode. In other cases, it is still default to 39

[PATCH rfcv2 16/17] intel_iommu: Modify x-scalable-mode to be string option

From: Yi Liu Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities related to scalable mode translation, thus there are multiple combinations. While this vIOMMU implementation wants to simplify it for user by providing typical combinations. User could config it by "x-scalabl

[PATCH rfcv2 01/17] intel_iommu: Update version to 3.0 and add the latest fault reasons

From: Yu Zhang The scalable mode was introduced in VTD spec 3.0, now that the scalable mode is already supported, bump version to 3.0. In spec 3.0 some more detailed fault reasons are defined for scalable mode. So introduce them into emulation code, see spec section 7.1.2 for details. Guest ker

[PATCH rfcv2 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation

Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. With scalable modern mdoe introduced, guest could send PADID-selective PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. Signed-off-by: Zhen

[PATCH rfcv2 00/17] intel_iommu: Enable stage-1 translation for emulated device

Hi, Per Jason Wang's suggestion, iommufd nesting series[1] is split into "Enable stage-1 translation for emulated device" series and "Enable stage-1 translation for passthrough device" series. This series enables stage-1 translation support for emulated device in intel iommu which we called "mode

[PATCH rfcv2 17/17] tests/qtest: Add intel-iommu test

Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness in scalable modern mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan --- MAINTAINERS| 1 + tests/qtest/intel-iommu-test.c

[PATCH rfcv2 08/17] intel_iommu: set accessed and dirty bits during first stage translation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 25 + 2 files changed, 28 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/in

[PATCH rfcv2 14/17] intel_iommu: piotlb invalidation should notify unmap

This is used by some emulated devices which caches address translation result. When piotlb invalidation issued in guest, those caches should be refreshed. Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 35 ++- 1 file changed, 34 i

[PATCH rfcv2 06/17] intel_iommu: Implement stage-1 translation

From: Yi Liu This adds stage-1 page table walking to support stage-1 only transltion in scalable modern mode. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 17 + hw/i386/intel_iommu.c | 128 +++

[PATCH rfcv2 12/17] intel_iommu: add an internal API to find an address space with PASID

From: Clément Mathieu--Drif This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 39 --- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/h

[PATCH rfcv2 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through (PGTT=100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IOTLB entries caching first-stage (PGTT=001b)

[PATCH rfcv2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

Add an new element scalable_mode in IntelIOMMUState to mark scalable modern mode, this element will be exposed as an intel_iommu property finally. For now, it's only a placehholder and used for cap/ecap initialization, compatibility check and block host device passthrough until nesting is supporte

[PATCH rfcv2 07/17] intel_iommu: check if the input address is canonical

From: Clément Mathieu--Drif First stage translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 21 + 2 files changed

[PATCH rfcv2 02/17] intel_iommu: Make pasid entry type check accurate

When guest configures Nested Translation(011b) or First-stage Translation only (001b), type check passed unaccurately. Fails the type check in those cases as their simulation isn't supported yet. Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation") Suggested-by: Yi Liu Signed-off-by: Zhen

Re: [PATCH v2 10/20] vfio/pci: Make vfio_populate_device() return a bool

On 5/22/24 06:40, Zhenzhong Duan wrote: Since vfio_populate_device() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. By this chance, pass errp directly to vfio_populate_device() to avoid calling error_propagate(). Signed-off-by: Zhenzho

Re: [PATCH v2 09/20] vfio/pci: Make vfio_pci_relocate_msix() and vfio_msix_early_setup() return a bool

On 5/22/24 06:40, Zhenzhong Duan wrote: Since vfio_pci_relocate_msix() and vfio_msix_early_setup() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. By this chance, pass errp directly to vfio_msix_early_setup() to avoid calling error_propa

Re: [PATCH v2 03/20] vfio/helpers: Use g_autofree in vfio_set_irq_signaling()

On 5/22/24 06:39, Zhenzhong Duan wrote: Local pointer irq_set is freed before return from vfio_set_irq_signaling(). Use 'g_autofree' to avoid the g_free() calls. Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater Thanks, C. --- hw/vfio/helpers.c | 3 +-- 1 file changed, 1

Re: [PULL 10/38] tests/qtest/migration: Add a test for the analyze-migration script

On 21/05/2024 14.46, Fabiano Rosas wrote: Alex Bennée writes: Juan Quintela writes: From: Fabiano Rosas Add a smoke test that migrates to a file and gives it to the script. It should catch the most annoying errors such as changes in the ram flags. After code has been merged it becomes wa

[PATCH] virtio-pci: Fix the use of an uninitialized irqfd.

The crash was reported in MAC OS and NixOS, here is the link for this bug https://gitlab.com/qemu-project/qemu/-/issues/2334 https://gitlab.com/qemu-project/qemu/-/issues/2321 The root cause is that the function virtio_pci_set_guest_notifiers() only initializes the irqfd when the use_guest_notifie

[PATCH v2 18/20] vfio/igd: Use g_autofree in vfio_probe_igd_bar4_quirk()

Pointer opregion, host and lpc are allocated and freed in vfio_probe_igd_bar4_quirk(). Use g_autofree to automatically free them. Signed-off-by: Zhenzhong Duan --- hw/vfio/igd.c | 27 --- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/hw/vfio/igd.c b/hw/v

[PATCH v2 16/20] vfio/pci-quirks: Make vfio_add_*_cap() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Include below functions: vfio_add_virt_caps() vfio_add_nv_gpudirect_cap() vfio_add_vmd_shadow_cap() Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw

[PATCH v2 14/20] vfio/pci: Use g_autofree for vfio_region_info pointer

Pointer opregion is freed after vfio_pci_igd_opregion_init(). Use 'g_autofree' to avoid the g_free() calls. Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index c33

RE: [PATCH 02/16] vfio/display: Make vfio_display_*() return bool

>-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH 02/16] vfio/display: Make vfio_display_*() return bool > >On 5/15/24 10:20, Zhenzhong Duan wrote: >> This is to follow the coding standand in qapi/error.h to return bool >> for bool-valued functions. >> >> Suggested-by: Céd

[PATCH v2 09/20] vfio/pci: Make vfio_pci_relocate_msix() and vfio_msix_early_setup() return a bool

Since vfio_pci_relocate_msix() and vfio_msix_early_setup() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. By this chance, pass errp directly to vfio_msix_early_setup() to avoid calling error_propagate(). Signed-off-by: Zhenzhong Duan --

[PATCH v2 07/20] vfio/ccw: Make vfio_ccw_get_region() return a bool

Since vfio_populate_device() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/ccw.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git

[PATCH v2 00/20] VFIO: misc cleanups part2

Hi This is the last round of cleanup series to change functions in hw/vfio/ to return bool when the error is passed through errp parameter. The first round is at https://lists.gnu.org/archive/html/qemu-devel/2024-05/msg01147.html I see Cédric is also working on some migration stuff cleanup, so

[PATCH v2 13/20] vfio/pci: Make capability related functions return bool

The functions operating on capability don't have a consistent return style. Below functions are in bool-valued functions style: vfio_msi_setup() vfio_msix_setup() vfio_add_std_cap() vfio_add_capabilities() Below two are integer-valued functions: vfio_add_vendor_specific_cap() vfio_setup_pcie_cap(

[PATCH v2 01/20] vfio/display: Fix error path in call site of ramfb_setup()

vfio_display_dmabuf_init() and vfio_display_region_init() calls ramfb_setup() without checking its return value. So we may run into a situation that vfio_display_probe() succeed but errp is set. This is risky and may lead to assert failure in error_setv(). Cc: Gerd Hoffmann Fixes: b290659fc3d ("

[PATCH v2 05/20] vfio/helpers: Make vfio_device_get_name() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- include/hw/vfio/vfio-common.h | 2 +- hw/vfio/ap.c | 2 +- hw/vfio/ccw.c

[PATCH v2 06/20] vfio/platform: Make vfio_populate_device() and vfio_base_device_init() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/platform.c | 40 +--- 1 file changed, 17 insertions(+), 23

[PATCH v2 02/20] vfio/display: Make vfio_display_*() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.h | 2 +- hw/vfio/display.c | 20 ++-- hw/vfio/pci.c | 3 +-- 3 f

[PATCH v2 04/20] vfio/helpers: Make vfio_set_irq_signaling() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- include/hw/vfio/vfio-common.h | 4 ++-- hw/vfio/ap.c | 8 +++ hw/vfio/ccw.c

[PATCH v2 20/20] vfio/ccw: Fix the missed unrealize() call in error path

When get name failed, we should call unrealize() so that vfio_ccw_realize() is self contained. Fixes: 909a6254eda ("vfio/ccw: Make vfio cdev pre-openable by passing a file handle") Signed-off-by: Zhenzhong Duan --- hw/vfio/ccw.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --gi

[PATCH v2 19/20] vfio/ccw: Drop local @err in vfio_ccw_realize()

Use @errp to fetch error information directly and drop the local variable @err. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/ccw.c | 21 ++--- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c index 2600e62e

[PATCH v2 11/20] vfio/pci: Make vfio_intx_enable() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.c | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/

[PATCH v2 12/20] vfio/pci: Make vfio_populate_vga() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.h | 2 +- hw/vfio/igd.c | 2 +- hw/vfio/pci.c | 11 +-- 3 files changed, 7 insert

[PATCH v2 17/20] vfio: Use g_autofree in all call site of vfio_get_region_info()

There are some exceptions when pointer to vfio_region_info is reused. In that case, the pointed memory is freed manually. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/helpers.c | 7 ++- hw/vfio/igd.c | 5 ++--- hw/vfio/pci.c | 13 +++-- 3 files

[PATCH v2 15/20] vfio/pci-quirks: Make vfio_pci_igd_opregion_init() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.h| 6 +++--- hw/vfio/igd.c| 3 +-- hw/vfio/pci-quirks.c | 8 hw/vf

[PATCH v2 08/20] vfio/pci: Make vfio_intx_enable_kvm() return a bool

Since vfio_intx_enable_kvm() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater --- hw/vfio/pci.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git

[PATCH v2 10/20] vfio/pci: Make vfio_populate_device() return a bool

Since vfio_populate_device() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. By this chance, pass errp directly to vfio_populate_device() to avoid calling error_propagate(). Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.c | 21 +

[PATCH v2 03/20] vfio/helpers: Use g_autofree in vfio_set_irq_signaling()

Local pointer irq_set is freed before return from vfio_set_irq_signaling(). Use 'g_autofree' to avoid the g_free() calls. Signed-off-by: Zhenzhong Duan --- hw/vfio/helpers.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/vfio/helpers.c b/hw/vfio/helpers.c index 47b4096

[PATCH 0/2] target/ppc: Fix PMU instruction counting

The crux of the problem being that dynamic exits from a TB would not count instructions previously executed in the TB. I don't know how important it is for PMU to count instructions exactly, however for instruction replay this can lead to different counts for the same execution (e.g., because TBs c

[PATCH 1/2] target/ppc: Fix PMC5 instruction counting

PMC5 does not count instructions correctly when single stepping the target with gdb, or when taking exceptions. The single-stepping inaccuracy is a problem for reverse debugging (because the PMC5 value can go out of sync between executions of the same trace). AFAIKS the current instruction count s

[PATCH 2/2] target/ppc: Tidy pmu_count_insns implementation

Merge the user-only and full implementations together, and only call translator_io_start() and only create and set the label when necessary. Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 55 +- 1 file changed, 28 insertions(+), 27 deletions(-

[PATCH RISU v2 3/8] Introduce host_context_t

Most hosts pass ucontext_t as the third parameter of signal handlers. In one existing usage, loongarch64 is using the kernel's struct ucontext instead of libc's ucontext_t. This is probably a simple mistake that could be fixed, but the structure member names differ, so the change would not be com

[PATCH RISU v2 5/8] risugen: Be explicit about print destinations

Printing directly to STDOUT and STDERR will allow the print destination to be selected elsewhere. Signed-off-by: Richard Henderson --- risugen_common.pm | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/risugen_common.pm b/risugen_common.pm index 71ee996..520

[PATCH RISU v2 8/8] sparc64: Add VIS1 instructions

Signed-off-by: Richard Henderson --- sparc64.risu | 91 1 file changed, 91 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index b45ea86..10a8510 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -28,3 +28,94 @@ XOR_r SPARC 10 r

[PATCH RISU v2 6/8] risugen: Add sparc64 support

Signed-off-by: Richard Henderson --- risugen| 10 +- risugen_common.pm | 50 +- risugen_sparc64.pm | 385 + 3 files changed, 443 insertions(+), 2 deletions(-) create mode 100644 risugen_sparc64.pm diff --git a/risugen b/risugen inde

[PATCH RISU v2 2/8] Build elf test cases instead of raw binaries

For test_arch64.s and test_arm.s, use '.inst' so that the risu control insns are marked as instructions for disassembly. For test_i386.S, split the data to be loaded into the data section; fix an error aligning the data: 16 not 2**16. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard He

[PATCH RISU v2 0/8] ELF and Sparc64 support

Let risu accept elf test files, adjusted from v1. Adjust risugen to invoke the assembler and linker, with a cross-compiler prefix if needed. Add some sparc64 testing which utilizes this. r~ Richard Henderson (8): risu: Allow use of ELF test files Build elf test cases instead of raw binaries

[PATCH RISU v2 4/8] risu: Add initial sparc64 support

Best effort for both Linux and Solaris as a host, since the gcc compile farm has more working Sparc Solaris hosts than Sparc Linux hosts. What's missing is a value for %gsr from Solaris. This could complicate comparison of VIS instructions. Signed-off-by: Richard Henderson --- Makefile

[PATCH RISU v2 1/8] risu: Allow use of ELF test files

By using elf files, we make it easier to disassemble the test file, to match comparison failures to code. Signed-off-by: Richard Henderson --- risu.c | 57 - 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/risu.c b/risu.c ind

[PATCH RISU v2 7/8] sparc64: Add a few logical insns

Just a token to verify the script is working. Signed-off-by: Richard Henderson --- sparc64.risu | 30 ++ 1 file changed, 30 insertions(+) create mode 100644 sparc64.risu diff --git a/sparc64.risu b/sparc64.risu new file mode 100644 index 000..b45ea86 --- /dev/nu

[PATCH v3] target/ppc: Add PPR32 SPR

PPR32 provides access to the upper half of PPR. Signed-off-by: Nicholas Piggin --- v3: - Don't clobber lower half of PPR. - Add spr_load_dump_spr (spr_store_dump_spr was already there). target/ppc/cpu.h| 1 + target/ppc/spr_common.h | 2 ++ target/ppc/cpu_init.c | 12 t

Re: [PATCH v3 2/6] hw/loongarch: Refine fadt memory table for numa memory

在 2024/5/15 下午5:39, Bibo Mao 写道: One LoongArch virt machine platform, there is limitation for memory map information. The minimum memory size is 256M and minimum memory size for numa node0 is 256M also. With qemu numa qtest, it is possible that memory size of numa node0 is 128M. Limitations for

Re: [PATCH v2 06/12] target/ppc: Add PPR32 SPR

On Wed May 22, 2024 at 3:40 AM AEST, Richard Henderson wrote: > On 5/20/24 18:30, Nicholas Piggin wrote: > > +void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn) > > +{ > > +TCGv t0 = tcg_temp_new(); > > + > > +tcg_gen_shli_tl(t0, cpu_gpr[gprn], 32); > > +gen_store_spr(SPR_PPR,

Re: [PATCH v3 1/6] hw/loongarch: Refine acpi srat table for numa memory

在 2024/5/15 下午5:39, Bibo Mao 写道: One LoongArch virt machine platform, there is limitation for memory map information. The minimum memory size is 256M and minimum memory size for numa node0 is 256M also. With qemu numa qtest, it is possible that memory size of numa node0 is 128M. Limitations for

Re: [PATCH v2 03/12] target/ppc: Implement attn instruction on BookS 64-bit processors

On Wed May 22, 2024 at 3:34 AM AEST, Richard Henderson wrote: > On 5/20/24 18:30, Nicholas Piggin wrote: > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > > index c358927211..2532408be0 100644 > > --- a/target/ppc/cpu.h > > +++ b/target/ppc/cpu.h > > @@ -3025,6 +3031,12 @@ static inline int ch

Re: [PATCH v2 03/12] target/ppc: Implement attn instruction on BookS 64-bit processors

Ah sorry, it's on top of some of Chinmay's decodetree series which is causing a couple of minor rejects. Thanks, Nick On Wed May 22, 2024 at 1:41 AM AEST, Miles Glenn wrote: > Looks like this patch is failing to apply to the current master head? > > Thanks, > > Glenn > > On Tue, 2024-05-21 at 11:

Re: [PATCH V9 6/8] physmem: Add helper function to destroy CPU AddressSpace

On Mon May 20, 2024 at 8:55 PM AEST, Salil Mehta wrote: > > From: Nicholas Piggin > > Sent: Monday, May 20, 2024 9:19 AM > > > > On Mon May 20, 2024 at 7:06 AM AEST, Salil Mehta wrote: > > > Virtual CPU Hot-unplug leads to unrealization of a CPU object. This > > > also involves destruction

Re: [PATCH V10 1/8] accel/kvm: Extract common KVM vCPU {creation,parking} code

On Tue May 21, 2024 at 9:32 AM AEST, Salil Mehta wrote: > KVM vCPU creation is done once during the vCPU realization when Qemu vCPU > thread > is spawned. This is common to all the architectures as of now. > > Hot-unplug of vCPU results in destruction of the vCPU object in QOM but the > correspond

Re: [PATCH v12 10/13] virtio-gpu: Move fence_poll timer to VirtIOGPUGL

On 5/20/24 06:51, Akihiko Odaki wrote: > On 2024/05/20 6:27, Dmitry Osipenko wrote: >> Move fence_poll timer to VirtIOGPUGL for consistency with cmdq_resume_bh >> that are used only by GL device. >> >> Signed-off-by: Dmitry Osipenko > > Thanks for refacotoring. > > Please move this before "[PATC

Re: [PATCH v12 00/13] Support blob memory and venus on qemu

On 5/21/24 17:57, Alex Bennée wrote: > Alex Bennée writes: > >> Dmitry Osipenko writes: >> >>> Hello, >>> >>> This series enables Vulkan Venus context support on virtio-gpu. >>> >>> All virglrender and almost all Linux kernel prerequisite changes >>> needed by Venus are already in upstream. For

Re: [PATCH v7 09/12] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents

On Mon, May 20, 2024 at 05:50:12PM +0100, Jonathan Cameron wrote: > On Wed, 1 May 2024 15:29:31 -0700 > fan wrote: > > > From 873f59ec06c38645768ada452d9b18920a34723e Mon Sep 17 00:00:00 2001 > > From: Fan Ni > > Date: Tue, 20 Feb 2024 09:48:31 -0800 > > Subject: [PATCH] hw/cxl/events: Add qmp i

Re: [PATCH v7 09/12] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents

>From 9d6d774ec973d22c0f662b32385345a88b14cc55 Mon Sep 17 00:00:00 2001 From: Fan Ni Date: Tue, 20 Feb 2024 09:48:31 -0800 Subject: [PATCH 11/14] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents To simulate FM functionalities for initiating Dynamic Capacity Add (Opcode

Re: [PATCH v3 4/4] target/hexagon: idef-parser simplify predicate init

On 5/21/2024 3:16 PM, Anton Johansson via wrote: Only predicate instruction arguments need to be initialized by idef-parser. This commit removes registers from the init_list and simplifies gen_inst_init_args() slightly. Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- Reviewe

Re: [PATCH v3 3/4] target/hexagon: idef-parser fix leak of init_list

On 5/21/2024 3:16 PM, Anton Johansson via wrote: gen_inst_init_args() is called for instructions using a predicate as an rvalue. Upon first call, the list of arguments which might need initialization init_list is freed to indicate that they have been processed. For instructions without an rvalu

Re: [PATCH v3 1/4] target/hexagon: idef-parser remove unused defines

On 5/21/2024 3:16 PM, Anton Johansson via wrote: Before switching to GArray/g_string_printf we used fixed size arrays for output buffers and instructions arguments among other things. Macros defining the sizes of these buffers were left behind, remove them. Signed-off-by: Anton Johansson Rev

Re: [PATCH v3 2/4] target/hexagon: idef-parser remove undefined functions

On 5/21/2024 3:16 PM, Anton Johansson via wrote: Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- Reviewed-by: Brian Cain target/hexagon/idef-parser/parser-helpers.h | 13 - 1 file changed, 13 deletions(-) diff --git a/target/hexagon/idef-parser/parser-help

Re: [PATCH] hw/core/machine: move compatibility flags for VirtIO-net USO to machine 8.1

On Fri, May 17, 2024 at 09:53:36AM +0200, Fiona Ebner wrote: > Migration from an 8.2 or 9.0 binary to an 8.1 binary with machine > version 8.1 can fail with: > > > kvm: Features 0x1c0010130afffa7 unsupported. Allowed features: 0x10179bfffe7 > > kvm: Failed to load virtio-net:virtio > > kvm: error

Re: [PATCH-for-9.1 v2 2/3] migration: Remove RDMA protocol handling

On Fri, May 17, 2024 at 03:01:59PM +0200, Yu Zhang wrote: > Hello Michael and Peter, Hi, > > Exactly, not so compelling, as I did it first only on servers widely > used for production in our data center. The network adapters are > > Ethernet controller: Broadcom Inc. and subsidiaries NetXtreme

[PATCH] accel/tcg: Init tb size and icount before plugin_gen_tb_end

When passing disassembly data to plugin callbacks, translator_st_len relies on db->tb->size having been set. Fixes: 4c833c60e047 ("disas: Use translator_st to get disassembly data") Reported-by: Bernhard Beschow Signed-off-by: Richard Henderson --- accel/tcg/translator.c | 8 1 file ch

[PATCH v3 4/4] target/hexagon: idef-parser simplify predicate init

Only predicate instruction arguments need to be initialized by idef-parser. This commit removes registers from the init_list and simplifies gen_inst_init_args() slightly. Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/idef-parser/idef-parser.y| 2 -- target/h

[PATCH v3 1/4] target/hexagon: idef-parser remove unused defines

Before switching to GArray/g_string_printf we used fixed size arrays for output buffers and instructions arguments among other things. Macros defining the sizes of these buffers were left behind, remove them. Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/idef-pa

[PATCH v3 3/4] target/hexagon: idef-parser fix leak of init_list

gen_inst_init_args() is called for instructions using a predicate as an rvalue. Upon first call, the list of arguments which might need initialization init_list is freed to indicate that they have been processed. For instructions without an rvalue predicate, gen_inst_init_args() isn't called and in

[PATCH v3 0/4] target/hexagon: Minor idef-parser cleanup

Was running idef-parser with valgrind and noticed we were leaking the init_list GArray, which is used to hold instruction arguments that may need initialization. This patchset fixes the leak, removes unused macros and undefined functions, and simplifies gen_inst_init_args() to only handle predicat

[PATCH v3 2/4] target/hexagon: idef-parser remove undefined functions

Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/idef-parser/parser-helpers.h | 13 - 1 file changed, 13 deletions(-) diff --git a/target/hexagon/idef-parser/parser-helpers.h b/target/hexagon/idef-parser/parser-helpers.h index 7c58087169..2087d534a9 100

[PATCH] Hyperv: Correct kvm_hv_handle_exit return value

From: donsheng This bug fix addresses the incorrect return value of kvm_hv_handle_exit for KVM_EXIT_HYPERV_SYNIC, which should be EXCP_INTERRUPT. Handling of KVM_EXIT_HYPERV_SYNIC in QEMU needs to be synchronous. This means that async_synic_update should run in the current QEMU vCPU thread befor

Re: [PATCH 57/57] target/arm: Convert SQDMULH, SQRDMULH to decodetree

On 5/21/24 09:16, Peter Maydell wrote: +void HELPER(neon_sqrdmulh_idx_s)(void *vd, void *vn, void *vm, + void *vq, uint32_t desc) +{ +intptr_t i, j, opr_sz = simd_oprsz(desc); +int idx = simd_data(desc); +int32_t *d = vd, *n = vn, *m = (int32_t *)vm + H

Re: [PATCH 32/57] target/arm: Inline scalar SUQADD and USQADD

On 5/21/24 09:46, Peter Maydell wrote: On Mon, 6 May 2024 at 02:08, Richard Henderson wrote: This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander. Signed-off-by: Richard Henderson +/* + * Set @res to the correctly satura

RE: [PATCH V10 7/8] gdbstub: Add helper function to unregister GDB register space

> From: Alex Bennée > Sent: Tuesday, May 21, 2024 4:23 PM > To: Salil Mehta > > Salil Mehta writes: > > > Hi Alex, > > > >> From: Alex Bennée > >> Sent: Tuesday, May 21, 2024 1:45 PM > >> To: Salil Mehta > >> > >> Salil Mehta writes: > >> > >> > Add common function to he

Re: [PATCH v2 06/12] target/ppc: Add PPR32 SPR

On 5/20/24 18:30, Nicholas Piggin wrote: +void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn) +{ +TCGv t0 = tcg_temp_new(); + +tcg_gen_shli_tl(t0, cpu_gpr[gprn], 32); +gen_store_spr(SPR_PPR, t0); +spr_store_dump_spr(SPR_PPR); +} The documentation isn't clear on whether t

Re: [PATCH v2 03/12] target/ppc: Implement attn instruction on BookS 64-bit processors

On 5/20/24 18:30, Nicholas Piggin wrote: diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c358927211..2532408be0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -3025,6 +3031,12 @@ static inline int check_pow_nocheck(CPUPPCState *env) return 1; } +/* attn enable check

Re: [PATCH v2 02/12] target/ppc: improve checkstop logging

On 5/20/24 18:30, Nicholas Piggin wrote: Change the logging not to print to stderr as well, because a checkstop is a guest error (or perhaps a simulated machine error) rather than a QEMU error, so send it to the log. Update the checkstop message, and log CPU registers too. Signed-off-by: Nichol

Re: [PATCH v2 12/12] target/ppc: add SMT support to msgsnd broadcast

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > msgsnd has a broadcast mode that sends hypervisor doorbells to all > threads belonging to the same core as the target. A "subcore" mode > sends to all or one thread depending on 1LPAR mode. > > S

Re: [PATCH v2 07/12] target/ppc: add helper to write per-LPAR SPRs

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR > means > per-thread or per-core, depending on 1LPAR mode. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/spr_common.h |

Re: [PATCH 32/57] target/arm: Inline scalar SUQADD and USQADD

On Mon, 6 May 2024 at 02:08, Richard Henderson wrote: > > This eliminates the last uses of these neon helpers. > Incorporate the MO_64 expanders as an option to the vector expander. > > Signed-off-by: Richard Henderson > +/* > + * Set @res to the correctly saturated result. > + * Set @qc non-ze

Re: [PATCH v2 10/12] target/ppc: Implement LDBAR, TTR SPRs

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > LDBAR, TTR are a Power-specific SPRs. These simple implementations > are enough for IBM proprietary firmware for now. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/cpu.h | 2 ++ >

Re: [PATCH v2 11/12] target/ppc: Implement SPRC/SPRD SPRs

Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers > that > can be accessed via these indirect SPRs. > > SCRATCH registers only provide storage, but they are used by firmware > fo

[PATCH] target/i386: Add x-amd-ccx-size property

According to AMD64 Architecture Programmer's Manual volume 3, information about the cache topology is exposed by 0x801D CPUID leaf, and 0x801E CPUID leaf is exposing information about the topology of the entire processor. For example, CPUID on the real EPYC Milan 7713 shows: * 0x801D_E

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