Hi Alexandre,
I have sent the patch set about Zabha before last week.
https://lore.kernel.org/all/fed99165-58da-458c-b68f-a9717fc15...@linux.alibaba.com/T/
Welcome to review it and give comments.
Thanks,
Zhiwei
On 2024/5/28 13:45, Alexandre Ghiti wrote:
From: Gianluca Guida
Add Zabha imple
On 5/27/24 18:06, Philippe Mathieu-Daudé wrote:
Hi Jamin,
On 27/5/24 10:02, Jamin Lin wrote:
AST2700 support the maximum dram size is 8GiB
and has a "DMA DRAM Side Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram
addres
Hi Nick,
On 5/26/24 17:56, Nicholas Piggin wrote:
SPRC/SPRD were recently added to all BookS CPUs supported, but
they are only tested on POWER9 and POWER10, so restrict them to
those CPUs.
Hope you mean to restrict to P9/10 for both spapr and pnv or just pnv ?
SPR indirect scratch registe
On 21/05/2024 14.53, Alex Bennée wrote:
As Centos Stream 8 goes out of support we need to update. To do this
powertools is replaced by crb and we don't over specify the python3 we
want.
Signed-off-by: Alex Bennée
---
tests/vm/centos.aarch64 | 10 +-
1 file changed, 5 insertions(+), 5
On 21/05/2024 14.53, Alex Bennée wrote:
From the website:
"After May 31, 2024, CentOS Stream 8 will be archived and no further
updates will be provided."
We have updated a few bits but there are still references that need
fixing.
Signed-off-by: Alex Bennée
---
docs/devel/testing.rst | 8 ++
On 5/24/2024 1:39 AM, Daniel Henrique Barboza wrote:
...
+/* 5.4 Features control register (32bits) */
+#define RISCV_IOMMU_REG_FCTL0x0008
Looks like doesn't support RISCV_IOMMU_FCTL_BE?
If so, need to implement it as read-only? along with other 2 bits.
IIUC,
diff --git a/hw/riscv
I just noticed that there is a typo in the subject:
s/warnigns/warnings/
On 28/05/2024 02.42, Nicholas Piggin wrote:
Reviewed-by: Thomas Huth
Signed-off-by: Nicholas Piggin
---
tests/qtest/migration-test.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/qtest
On 28/05/2024 02.42, Nicholas Piggin wrote:
The spapr QEMU machine defaults is useful outside libqos, so create a
new header for ppc specific qtests and move it there.
Signed-off-by: Nicholas Piggin
---
tests/qtest/libqos/libqos-spapr.h | 7 ---
tests/qtest/ppc-util.h| 19 ++
On 5/28/24 03:34, Jamin Lin wrote:
Hi Cedric,
On 5/27/24 10:02, Jamin Lin wrote:
AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM
Side
Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram address, new
fe
On 28/05/2024 02.42, Nicholas Piggin wrote:
As Fabiano points out, this test isn't flaky it just can't run under
gitlab CI since runners have a very small shm size.
Suggested-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
tests/qtest/migration-test.c | 18 +-
1 file ch
On 5/28/24 03:26, Jamin Lin wrote:
Hi Philippe, Cedric
On 27/5/24 13:18, Cédric Le Goater wrote:
On 5/27/24 12:24, Philippe Mathieu-Daudé wrote:
Hi Jamin,
On 27/5/24 10:02, Jamin Lin wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up t
Hi Stefan,
On Mon, May 27, 2024 at 03:59:44PM -0400, Stefan Hajnoczi wrote:
> Date: Mon, 27 May 2024 15:59:44 -0400
> From: Stefan Hajnoczi
> Subject: Re: [RFC 0/6] scripts: Rewrite simpletrace printer in Rust
>
> On Mon, May 27, 2024 at 04:14:15PM +0800, Zhao Liu wrote:
> > Hi maintainers and l
On 5/26/24 17:56, Nicholas Piggin wrote:
The timebase state machine is per per-core state and can be driven
by any thread in the core. It is currently implemented as a hack
where the state is in a CPU structure and only thread 0's state is
accessed by the chiptod, which limits programming the
From: Glenn Miles
The LPC HC irq status register bits are set when an LPC IRQSER input is
asserted. These irq status bits drive the PSI irq to the CPU interrupt
controller. The LPC HC irq status bits are cleared by software writing
to the register with 1's for the bits to clear.
Existing registe
The POWER8 LPC ISA device irqs all get combined and reported to the line
connected the PSI LPCHC irq. POWER9 changed this so only internal LPC
host controller irqs use that line, and the device irqs get routed to
4 new lines connected to PSI SERIRQ0-3.
POWER9 also introduced a new feature that aut
On 5/26/24 17:56, Nicholas Piggin wrote:
This helps move core state from CPU to core structures.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_core.h | 1 +
hw/ppc/pnv_core.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/pp
Here is v2 of the POWER9 PSI serirq patch with changes suggested by
Cedric and some other things. But also in front of that we have a fix
from Glenn for a lost interrupt problem.
I rebased Glenn's patch and also changed some comments and changelog
a bit so any bugs or silly comments are probably m
From: Minwoo Im
This patch adds support for MCQ defined in UFSHCI 4.0. This patch
utilized the legacy I/O codes as much as possible to support MCQ.
MCQ operation & runtime register is placed at 0x1000 offset of UFSHCI
register statically with no spare space among four registers (48B):
From: Minwoo Im
This patch is a prep patch for the following MCQ support patch for
hw/ufs. This patch updated minimal mandatory fields to support MCQ
based on UFSHCI 4.0.
Signed-off-by: Minwoo Im
Reviewed-by: Jeuk Kim
Message-Id: <20240528023106.856777-2-minwoo...@samsung.com>
Signed-off-by:
From: Jeuk Kim
The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into
staging (2024-05-27 06:40:42 -0700)
are available in the Git repository at:
https://gitlab.com/jeuk20.kim/qemu.git tags/pull
On Mon, May 27, 2024 at 05:15:05PM GMT, Cédric Le Goater wrote:
> On 5/27/24 09:10, Aditya Gupta wrote:
> > Power11 core is same as Power10, use the existing functionalities to
> > introduce a Power11 chip and machine, with Power10 chip as parent of
> > Power11 chip, thus going through similar clas
Hi Mads,
On Mon, May 27, 2024 at 12:49:06PM +0200, Mads Ynddal wrote:
> Date: Mon, 27 May 2024 12:49:06 +0200
> From: Mads Ynddal
> Subject: Re: [RFC 0/6] scripts: Rewrite simpletrace printer in Rust
> X-Mailer: Apple Mail (2.3774.600.62)
>
> Hi,
>
> Interesting work. I don't have any particula
From: Gianluca Guida
Add Zabha implementation.
Signed-off-by: Gianluca Guida
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 2 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 22 +++
target/riscv/insn_tr
There is no need to use /dev/shm for file-backed memory devices, and
it is too small to be usable in gitlab CI. Switch to using a regular
file in /tmp/ which will usually have more space available.
Signed-off-by: Nicholas Piggin
---
Am I missing something? AFAIKS there is not even any point using
Hi Zhao,
On 2024/5/28 上午10:31, Zhao Liu wrote:
Hi Chuang,
On Mon, May 27, 2024 at 11:13:33AM +0800, Chuang Xu wrote:
Date: Mon, 27 May 2024 11:13:33 +0800
From: Chuang Xu
Subject: [PATCH] x86: cpu: fixup number of addressable IDs for processor
cores in the physical package
According to the
On Tue May 28, 2024 at 8:23 AM AEST, BALATON Zoltan wrote:
> On Wed, 3 Apr 2024, Nicholas Piggin wrote:
> > On Tue Apr 2, 2024 at 9:32 PM AEST, BALATON Zoltan wrote:
> >> On Thu, 21 Mar 2024, BALATON Zoltan wrote:
> >>> On 27/2/24 17:47, BALATON Zoltan wrote:
> Hello,
>
> Commit 18a5
On Mon, May 27, 2024 at 7:27 PM Halil Pasic wrote:
>
> On Thu, 16 May 2024 10:39:42 +0200
> Stefano Garzarella wrote:
>
> [..]
> > >---
> > >
> > >This is a minimal fix, that follows the current patterns in the
> > >codebase, and not necessarily the best one.
> >
> > Yeah, I did something similar
On Mon, May 27, 2024 at 2:50 PM Michael S. Tsirkin wrote:
>
> On Mon, May 27, 2024 at 06:44:58AM +, Duan, Zhenzhong wrote:
> > Hi Jason,
> >
> > >-Original Message-
> > >From: Duan, Zhenzhong
> > >Subject: RE: [PATCH] intel_iommu: Use the latest fault reasons defined by
> > >spec
> > >
On 5/28/2024 11:31 AM, Minwoo Im wrote:
UFSHCI 4.0 spec introduced MCQ(Multi-Circular Queue) to support multiple
command queues for UFS controller. To test ufs-mcq path of kernel, MCQ
emulated device would be a good choice to go with.
The first patch added newly introduced fields in UFSHCI 4.
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v5 19/19] intel_iommu: Check compatibility with host
>IOMMU capabilities
>
>On 5/8/24 11:03, Zhenzhong Duan wrote:
>> If check fails, host device (either VFIO or VDPA device) is not
>> compatible with current vIOMMU config
From: Daniel Henrique Barboza
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.
Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting '
From: Alexei Filippov
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation
but
failed pmp check.
In this case w
From: Jason Chien
In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.
Signed-off-
From: Jason Chien
Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.
Signed-off-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20240328022343.6871-2-jason.ch...@sif
On 2024-05-27 23:41, Andrew Jones wrote:
> On Mon, May 27, 2024 at 02:19:13AM GMT, Chao Du wrote:
> > This patch implements insert/remove software breakpoint process:
> >
> > Add an input parameter for kvm_arch_insert_sw_breakpoint() and
> > kvm_arch_remove_sw_breakpoint() to pass the length info
From: Yangyu Chen
This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.
Signed-off-by: Yangyu Chen
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to
riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei
Revie
From: Clément Léger
The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number t
From: Daniel Henrique Barboza
SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.
The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.
As far as K
From: Rob Bradford
This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.
Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.
Signed-off-by: Rob Bradford
Reviewed-by: Andrew Jones
R
From: Yong-Xuan Wang
In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number a
From: Alistair Francis
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.
Reported-by: Eric DeVolder
Signed-off-by: Alistair Francis
Fixes: ea10325917 ("RISC-V Disassemble
From: Max Chou
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of
* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)
Signed-off-
From: Huang Tao
In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
From: Alistair Francis
When running the instruction
```
cbo.flush 0(x0)
```
QEMU would segfault.
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.
In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer m
From: Daniel Henrique Barboza
raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.
There's no mention in the spec about guest page fault being a higher
priority that PMP f
From: Yu-Ming Chang
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and wi
From: Max Chou
If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Cc: qemu-stable
Messag
From: Huang Tao
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.
However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling o
From: Max Chou
The opfv_narrow_check needs to check the single width float operator by
require_rvf.
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Cc: qemu-stable
Message-ID: <20240322092600.1198921-4-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn_t
From: Cheng Yang
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.
Signed-off-by: Cheng Yang
Reviewed-by: Alistair Francis
Message-ID:
Signed-off-by: Alistair Francis
---
hw/riscv/boot.c | 4 ++--
1 file changed, 2 i
From: Jason Chien
Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
Reviewed-
From: Daniel Henrique Barboza
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if
From: Christoph Müllner
The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
An important property of this patch is, that the th.sxstatus MAEE fiel
From: Max Chou
The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
in
From: Daniel Henrique Barboza
We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":
"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stor
From: Daniel Henrique Barboza
Privileged spec section 4.1.9 mentions:
"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)
If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fau
From: Andrew Jones
The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.
Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (
From: Andrew Jones
Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of th
From: "yang.zhang"
Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.
Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: yang.zhang
Cc: qemu-stable
Message-ID: <20240409014445.278-1-gao
The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into
staging (2024-05-27 06:40:42 -0700)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-2
This patch adds support for MCQ defined in UFSHCI 4.0. This patch
utilized the legacy I/O codes as much as possible to support MCQ.
MCQ operation & runtime register is placed at 0x1000 offset of UFSHCI
register statically with no spare space among four registers (48B):
UfsMcqSqReg, UfsMc
This patch is a prep patch for the following MCQ support patch for
hw/ufs. This patch updated minimal mandatory fields to support MCQ
based on UFSHCI 4.0.
Signed-off-by: Minwoo Im
---
include/block/ufs.h | 108 +++-
1 file changed, 106 insertions(+), 2 de
UFSHCI 4.0 spec introduced MCQ(Multi-Circular Queue) to support multiple
command queues for UFS controller. To test ufs-mcq path of kernel, MCQ
emulated device would be a good choice to go with.
The first patch added newly introduced fields in UFSHCI 4.0 to support
MCQ. The other one made the ac
Hi Chuang,
On Mon, May 27, 2024 at 11:13:33AM +0800, Chuang Xu wrote:
> Date: Mon, 27 May 2024 11:13:33 +0800
> From: Chuang Xu
> Subject: [PATCH] x86: cpu: fixup number of addressable IDs for processor
> cores in the physical package
According to the usual practice of QEMU commits, people tend
On 24-05-28 10:00:35, Jeuk Kim wrote:
> Thanks for your contribution!
>
> There are only two minor comments.
Thanks for your review.
>
> Please check it and send patch v2.
>
>
> Thank you!
>
> On 5/21/2024 8:05 PM, Minwoo Im wrote:
> > @@ -1288,12 +1717,21 @@ static void ufs_exit(PCIDevice *
Hi Philippe,
> Hi Jamin,
>
> On 27/5/24 10:02, Jamin Lin wrote:
> > AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM
> Side
> > Address High Part(0x7C)"
> > register to support 64 bits dma dram address.
> > Add helper routines functions to compute the dma dram address, new
> > fe
Hi Cedric,
> On 5/27/24 10:02, Jamin Lin wrote:
> > AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM
> Side
> > Address High Part(0x7C)"
> > register to support 64 bits dma dram address.
> > Add helper routines functions to compute the dma dram address, new
> > features and update
>
> The Aspeed SMC device model use to have a 'sdram_base' property. It was
> removed by commit d177892d4a48 ("aspeed/smc: Remove unused
> "sdram-base" property") because previous changes simplified the DMA
> transaction model to use an offset in RAM and not the physical address.
>
> The AST2700
Hi Philippe, Cedric
> On 27/5/24 13:18, Cédric Le Goater wrote:
> > On 5/27/24 12:24, Philippe Mathieu-Daudé wrote:
> >> Hi Jamin,
> >>
> >> On 27/5/24 10:02, Jamin Lin wrote:
> >>> The SDRAM memory controller(DRAMC) controls the access to external
> >>> DDR4 and DDR5 SDRAM and power up to DDR4 an
On 2024/5/27 下午6:39, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 27/5/24 10:34, Bibo Mao wrote:
Loongson Binary Translation (LBT) is used to accelerate binary
translation. LBT feature is added in kvm mode, not supported in TCG
mode since it is not emulated. And only LBT feature is added here,
Hi Philippe,
Thanks for reviewing my patch.
I reply inline.
On 2024/5/27 下午6:37, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 27/5/24 10:35, Bibo Mao wrote:
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
efla
Thanks for your contribution!
There are only two minor comments.
Please check it and send patch v2.
Thank you!
On 5/21/2024 8:05 PM, Minwoo Im wrote:
@@ -1288,12 +1717,21 @@ static void ufs_exit(PCIDevice *pci_dev)
ufs_clear_req(&u->req_list[i]);
}
g_free(u->req_list);
Similar to other archs, build a custom bios memory updater. Running the
test with OF code is a cool trick, but SLOF takes a long time to boot.
This reduces test time by around 3x (150s to 50s).
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
tests/migration/migration-test.h | 1
ppc64 with TCG seems to no longer be failing this test, perhaps since
commit 03bfc2188f061 ("physmem: Fix migration dirty bitmap coherency
with TCG memory access") which is not ppc specific but was seen to hit
ppc64 quite easily.
Let's enable it again.
The s390x problem has been identified so men
Reviewed-by: Thomas Huth
Signed-off-by: Nicholas Piggin
---
tests/qtest/migration-test.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index 8247ed98f2..7d64696f7a 100644
--- a/tests/qtest/migration-test.c
+++ b
The spapr QEMU machine defaults is useful outside libqos, so create a
new header for ppc specific qtests and move it there.
Signed-off-by: Nicholas Piggin
---
tests/qtest/libqos/libqos-spapr.h | 7 ---
tests/qtest/ppc-util.h| 19 +++
tests/qtest/boot-serial-test.
As Fabiano points out, this test isn't flaky it just can't run under
gitlab CI since runners have a very small shm size.
Suggested-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
tests/qtest/migration-test.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --g
This test is already starting to bitrot, so first remove it from ifdef
and fix compile issues. ppc64 transfers about 2MB, so bump the size
threshold too.
It was said to be broken on aarch64 but it may have been the limited shm
size under gitlab CI. The test is now excluded from running on CI so it
Since v1:
- Added "TCG" in subject since it is enabling for TCG
- Enable test_mode_reboot with checking GITLAB_CI env that Fabiano
suggested.
- Move test_ignore_shared patch out of the s390 fix series to here
and use GITLAB_CI for it too.
- Move ppc64 pseries machine options out of libqos-spapr
Peter Xu writes:
> On Thu, May 23, 2024 at 05:19:22PM -0300, Fabiano Rosas wrote:
>> We have two new migration tests that check cross version
>> compatibility. One uses the vmstate-static-checker.py script to
>> compare the vmstate structures from two different QEMU versions. The
>> other runs a
On Thu, Apr 11, 2024 at 9:34 PM Clément Léger wrote:
>
> When icount is enabled, rather than returning the virtual CPU time, we
> should return the instruction count itself. Add an instructions bool
> parameter to get_ticks() to correctly return icount_get_raw() when
> icount_enabled() == 1 and in
Peter Xu writes:
> On Thu, May 23, 2024 at 05:19:21PM -0300, Fabiano Rosas wrote:
>> The current migration-tests are almost entirely focused on catching
>> bugs on the migration code itself, not on the device migration
>> infrastructure (vmstate). That means we miss catching some low hanging
>> f
On Tue, 28 May 2024, BALATON Zoltan wrote:
On Wed, 3 Apr 2024, Nicholas Piggin wrote:
On Tue Apr 2, 2024 at 9:32 PM AEST, BALATON Zoltan wrote:
On Thu, 21 Mar 2024, BALATON Zoltan wrote:
On 27/2/24 17:47, BALATON Zoltan wrote:
Hello,
Commit 18a536f1f8 (accel/tcg: Always require can_do_io) br
Peter Xu writes:
> On Thu, May 23, 2024 at 05:19:20PM -0300, Fabiano Rosas wrote:
>> We have the vmstate-static-checker script that takes the output of:
>> '$QEMU -M $machine -dump-vmstate' for two different QEMU versions and
>> compares them to check for compatibility breakages. This is just too
On Wed, 3 Apr 2024, Nicholas Piggin wrote:
On Tue Apr 2, 2024 at 9:32 PM AEST, BALATON Zoltan wrote:
On Thu, 21 Mar 2024, BALATON Zoltan wrote:
On 27/2/24 17:47, BALATON Zoltan wrote:
Hello,
Commit 18a536f1f8 (accel/tcg: Always require can_do_io) broke booting
MorphOS on sam460ex (this was be
Fixes a bug in the immediate shifts, because the exact
encoding depends on the element size.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 58 ++--
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.i
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index b1d652355d..cc54bc4a53 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b
Signed-off-by: Richard Henderson
---
host/include/loongarch64/host/cpuinfo.h | 1 +
util/cpuinfo-loongarch.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/host/include/loongarch64/host/cpuinfo.h
b/host/include/loongarch64/host/cpuinfo.h
index fab664a10b..d7bf27501d 100644
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 5f4915c6ac..e633d268d0 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/l
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 9a8f67cf3e..c7d0c7839b 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 119 ---
1 file changed, 63 insertions(+), 56 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 652aa261a3..5f4915c6ac 100644
--- a/tcg/loongarch6
We can implement this with fld_d, fst_d for load and store,
and then use the normal v128 operations in registers.
This will improve support for guests which use v64.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 8 ++--
2 fil
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 36 ++--
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 47011488dd..652aa261a3 100644
--- a/tcg/loongarch6
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 11 ---
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 990bad1d51..58bd7d258e 100644
--- a/tc
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index c7d0c7839b..47011488dd 100644
--- a/tcg/loongarch64/t
Some guests only have, or additionally have, 64-bit vectors.
For example arm, mips, sparc. So it's best to enable this
whenever we can. As with tcg/i386, use 64-bit loads and stores
but 128-bit vector registers.
If LASX is available (all current loongarch64 cpus?), we have
256-bit vectors as wel
Use TCG_VEC_TMP0 directly.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index e633d268d0..54f7bc9d14 100644
--- a/tcg/loongarc
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 22 ++
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 980ea10211..b1d652355d 100644
--- a/tcg/loongarch64/tcg-targe
Each element size has a different encoding, so code cannot
be shared in the same way as with tcg_out_dup_vec.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/tcg/loongarch64/
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 1e721b8b20..9a8f67cf3e 100644
--- a/tcg/loongarch64/tcg-target.c.i
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