Re: [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

Hi Daniel, Andrew: Thank you for giving me the feedback. I found a new command set to cc the related maintainer's email. It also includes these emails for the cover letter. git send-email --dry-run --to='qemu-devel@nongnu.org,qemu-ri...@nongnu.org' --cc="$(scripts/get_maintainer.pl XXXPATCH/* |sed

RE: [PATCH v2 3/5] intel_iommu: Add a framework to do compatibility check with host IOMMU cap/ecap

Hi Michael, >-Original Message- >From: Michael S. Tsirkin >Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do >compatibility check with host IOMMU cap/ecap > >On Fri, Apr 26, 2024 at 03:10:14AM +, Duan, Zhenzhong wrote: >> >> >> >-Original Message- >> >From: Cédric

RE: [SPAM] Re: [PATCH v4 09/16] aspeed/smc: Add AST2700 support

Hi Cedric, Philippe > From: Cédric Le Goater > Sent: Tuesday, May 28, 2024 3:03 PM > To: Philippe Mathieu-Daudé ; Jamin Lin > ; Peter Maydell ; > Andrew Jeffery ; Joel Stanley > ; Alistair Francis ; Cleber Rosa > ; Wainer dos Santos Moschetta ; > Beraldo Leal ; open list:ASPEED BMCs > ; open list

Re: [PATCH] i386: removes microvm from default build since microvm doesn't support Xen accel.

On 6/2/24 12:38, Will Gyda wrote: i386: removes microvm from default build since microvm doesn't support Xen accel. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2294 This is already done in (what will be) QEMU 9.1; configs/devices/i386-softmmu.mak has: # Boards are selected by d

[PATCH v6 18/19] intel_iommu: Implement [set|unset]_iommu_device() callbacks

From: Yi Liu Implement [set|unset]_iommu_device() callbacks in Intel vIOMMU. In set call, a new structure VTDHostIOMMUDevice which holds a reference to HostIOMMUDevice is stored in hash table indexed by PCI BDF. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw

[PATCH v6 05/19] backends/host_iommu_device: Introduce HostIOMMUDeviceCaps

HostIOMMUDeviceCaps's elements map to the host IOMMU's capabilities. Different platform IOMMU can support different elements. Currently only two elements, type and aw_bits, type hints the host platform IOMMU type, i.e., INTEL vtd, ARM smmu, etc; aw_bits hints host IOMMU address width. Introduce .

[PATCH v6 01/19] backends: Introduce HostIOMMUDevice abstract

Introduce HostIOMMUDevice as an abstraction of host IOMMU device. Introduce .realize() to initialize HostIOMMUDevice further after instance init. Introduce a macro CONFIG_HOST_IOMMU_DEVICE to define the usage for VFIO, and VDPA in the future. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzh

[PATCH v6 07/19] vfio/container: Implement HostIOMMUDeviceClass::realize() handler

Utilize range_get_last_bit() to get host IOMMU address width and package it in HostIOMMUDeviceCaps for query with .get_cap(). Signed-off-by: Zhenzhong Duan --- hw/vfio/container.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/hw/vfio/container.c b/hw/vfio/contai

[PATCH v6 19/19] intel_iommu: Check compatibility with host IOMMU capabilities

If check fails, host device (either VFIO or VDPA device) is not compatible with current vIOMMU config and should not be passed to guest. Only aw_bits is checked for now, we don't care other capabilities before scalable modern mode is introduced. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Dua

[PATCH v6 17/19] intel_iommu: Extract out vtd_cap_init() to initialize cap/ecap

Extract cap/ecap initialization in vtd_cap_init() to make code cleaner. No functional change intended. Reviewed-by: Eric Auger Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 93 --- 1 file changed, 51 insertions(+), 42 deletions(-) diff --git

[PATCH v6 13/19] vfio: Create host IOMMU device instance

Create host IOMMU device instance in vfio_attach_device() and call .realize() to initialize it further. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-common.h | 1 + hw/vfio/common.c | 16 +++- 2 files changed, 16 insertions(+),

[PATCH v6 14/19] hw/pci: Introduce helper function pci_device_get_iommu_bus_devfn()

Extract out pci_device_get_iommu_bus_devfn() from pci_device_iommu_address_space() to facilitate implementation of pci_device_[set|unset]_iommu_device() in following patch. No functional change intended. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Nicolin Chen Signed-off-by: Zhe

[PATCH v6 10/19] vfio/container: Implement HostIOMMUDeviceClass::get_cap() handler

Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/container.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/vfio/container.c b/hw/vfio/container.c index 48800fe92f..a46c275a88 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -1154,11

[PATCH v6 03/19] backends/iommufd: Introduce abstract TYPE_HOST_IOMMU_DEVICE_IOMMUFD device

TYPE_HOST_IOMMU_DEVICE_IOMMUFD represents a host IOMMU device under iommufd backend. It will have its own .get_cap() implementation. Opportunistically, add missed header to include/sysemu/iommufd.h. Suggested-by: Cédric Le Goater Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- includ

[PATCH v6 04/19] vfio/iommufd: Introduce TYPE_HOST_IOMMU_DEVICE_IOMMUFD_VFIO device

TYPE_HOST_IOMMU_DEVICE_IOMMUFD_VFIO represents a host IOMMU device under VFIO iommufd backend. It will be created during VFIO device attaching and passed to vIOMMU. It will have its own .realize() implementation. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/

[PATCH v6 16/19] vfio/pci: Pass HostIOMMUDevice to vIOMMU

With HostIOMMUDevice passed, vIOMMU can check compatibility with host IOMMU, call into IOMMUFD specific methods, etc. Originally-by: Yi Liu Signed-off-by: Nicolin Chen Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.c | 19 ++- 1 file changed, 14 insertions

[PATCH v6 15/19] hw/pci: Introduce pci_device_[set|unset]_iommu_device()

From: Yi Liu pci_device_[set|unset]_iommu_device() call pci_device_get_iommu_bus_devfn() to get iommu_bus->iommu_ops and call [set|unset]_iommu_device callback to set/unset HostIOMMUDevice for a given PCI device. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Nicolin Chen Signed-o

[PATCH v6 08/19] backends/iommufd: Introduce helper function iommufd_backend_get_device_info()

Introduce a helper function iommufd_backend_get_device_info() to get host IOMMU related information through iommufd uAPI. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- include/sysemu/iommufd.h | 3 +++ backends/iommufd.c | 22 ++ 2 fil

[PATCH v6 06/19] range: Introduce range_get_last_bit()

This helper get the highest 1 bit position of the upper bound. If the range is empty or upper bound is zero, -1 is returned. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/qemu/range.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/qemu/range

[PATCH v6 11/19] backends/iommufd: Implement HostIOMMUDeviceClass::get_cap() handler

Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- backends/iommufd.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index c7e969d6f7..f2f7a762a0 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -230,6

[PATCH v6 09/19] vfio/iommufd: Implement HostIOMMUDeviceClass::realize() handler

It calls iommufd_backend_get_device_info() to get host IOMMU related information and translate it into HostIOMMUDeviceCaps for query with .get_cap(). Introduce macro VTD_MGAW_FROM_CAP to get MGAW which equals to (aw_bits - 1). Signed-off-by: Zhenzhong Duan --- include/hw/i386/intel_iommu.h | 1

[PATCH v6 00/19] Add a host IOMMU device abstraction to check with vIOMMU

Hi, This series introduce a HostIOMMUDevice abstraction and sub-classes. Also HostIOMMUDeviceCaps structure in HostIOMMUDevice and a new interface between vIOMMU and HostIOMMUDevice. HostIOMMUDeviceClass::realize() is introduced to initialize HostIOMMUDeviceCaps and other fields of HostIOMMUDevic

[PATCH v6 12/19] vfio: Introduce VFIOIOMMUClass::hiod_typename attribute

Initialize attribute VFIOIOMMUClass::hiod_typename based on VFIO backend type. This attribute will facilitate HostIOMMUDevice creation in vfio_attach_device(). Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-container-base.h | 3 +++ hw/vfio/container.c

[PATCH v6 02/19] vfio/container: Introduce TYPE_HOST_IOMMU_DEVICE_LEGACY_VFIO device

TYPE_HOST_IOMMU_DEVICE_LEGACY_VFIO represents a host IOMMU device under VFIO legacy container backend. It will have its own realize implementation. Suggested-by: Eric Auger Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-common.h | 3 +++ hw/vfio/containe

[PATCH 1/6] target/riscv: Introduce extension implied rules definition

From: Frank Chang RISCVCPUImpliedExtsRule is created to store the implied rules. 'is_misa' flag is used to distinguish whether the rule is derived from the MISA or other extensions. 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores the offset of the extension defined in RISCVCP

[PATCH 5/6] target/riscv: Add Zc extension implied rule

From: Frank Chang Zc extension has special implied rules that need to be handled separately. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian --- target/riscv/tcg/tcg-cpu.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu

[PATCH 0/6] Introduce extension implied rules

From: Frank Chang Currently, the implied extensions are enabled and checked in riscv_cpu_validate_set_extensions(). However, the order of enabling the implied extensions must follow a strict sequence, which is error-prone. This patchset introduce extension implied rule helpers to enable the impl

[PATCH 3/6] target/riscv: Add MISA implied rules

From: Frank Chang Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian --- target/riscv/cpu.c | 50 +- 1 file changed, 49 insertions(+), 1 deletion(-) diff -

[PATCH 4/6] target/riscv: Add standard extension implied rules

From: Frank Chang Add standard extension implied rules to enable the implied extensions of the standard extension recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian --- target/riscv/cpu.c | 340 + 1 file changed, 340 insertions(+)

[PATCH 2/6] target/riscv: Introduce extension implied rule helpers

From: Frank Chang Introduce helpers to enable the extensions based on the implied rules. The implied extensions are enabled recursively, so we don't have to expand all of them manually. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvks

[PATCH 6/6] target/riscv: Remove extension auto-update check statements

From: Frank Chang Remove the old-fashioned extension auto-update check statements as they are replaced by the extension implied rules. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian --- target/riscv/tcg/tcg-cpu.c | 115 - 1 file changed, 115 delet

[PATCH ats_vtd v5 02/22] intel_iommu: make types match

From: Clément Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2

[PATCH ats_vtd v5 17/22] atc: generic ATC that can be used by PCIe devices that support SVM

From: Clément Mathieu--Drif As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif

Re: [PATCH v2 4/4] tests/qtest/migration-test: Add a postcopy memfile test

On Fri May 31, 2024 at 11:34 PM AEST, Peter Xu wrote: > On Thu, May 30, 2024 at 07:54:07PM +1000, Nicholas Piggin wrote: > > Postcopy requires userfaultfd support, which requires tmpfs if a memory > > file is used. > > > > This adds back support for /dev/shm memory files, but adds preallocation >

[PATCH ats_vtd v5 09/22] pci: cache the bus mastering status in the device

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 24 ++-- include/hw/pci/pci_device.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c8a8aab306..51feede3cf 100644 --

[PATCH ats_vtd v5 00/22] ATS support for VT-d

From: Clément Mathieu--Drif This series belongs to a list of series that add SVM support for VT-d. As a starting point, we use the series called 'intel_iommu: Enable stage-1 translation' (rfc2) by Zhenzhong Duan and Yi Liu. Here we focus on the implementation of ATS support in the IOMMU and on

[PATCH ats_vtd v5 14/22] intel_iommu: implement the get_memory_region_pasid iommu operation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6a68df0154..d607562de2 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu

[PATCH ats_vtd v5 13/22] intel_iommu: implement the get_address_space_pasid iommu operation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 13 ++--- include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index fb6c7d1e33..6a68df015

RE: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

Hi Alistair, I think we need the following patch to fix this issue: From 6175c9aee103e40b5a5da587f659563de93b3d85 Mon Sep 17 00:00:00 2001 From: Alvin Chang Date: Thu, 18 Apr 2024 14:52:36 +0800 Subject: [PATCH] target/riscv: Fix GDB can not read the read-only CSR From commit 563581cb60, use ri

[PATCH ats_vtd v5 08/22] intel_iommu: declare supported PASID size

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 7b0c22fc07..fb6c7d1e33 100644 --- a

[PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS

From: Clément Mathieu--Drif Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier

[PATCH ats_vtd v5 15/22] memory: Allow to store the PASID in IOMMUTLBEntry

From: Clément Mathieu--Drif This will be useful for devices that support ATS Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 359bca2ae2..56ef48780f 100644 --- a/include/exec/m

[PATCH ats_vtd v5 18/22] atc: add unit tests

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 + 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests/

[PATCH ats_vtd v5 07/22] pcie: helper functions to check if PASID and ATS are enabled

From: Clément Mathieu--Drif ats_enabled and pasid_enabled check whether the capabilities are present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 18 ++ include

[PATCH ats_vtd v5 16/22] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index d607562de2..0f3bd5978e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2

[PATCH ats_vtd v5 06/22] pcie: add helper to declare PASID capability for a pcie device

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 24 +++ include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h| 3 +++ include/standard-headers/linux/pci_regs.h | 1

[PATCH ats_vtd v5 22/22] intel_iommu: add support for ATS

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 75 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

[PATCH ats_vtd v5 12/22] pci: add a pci-level initialization function for iommu notifiers

From: Clément Mathieu--Drif We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-o

[PATCH ats_vtd v5 05/22] memory: add permissions in IOMMUAccessFlags

From: Clément Mathieu--Drif This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (define

[PATCH ats_vtd v5 03/22] intel_iommu: return page walk level even when the translation fails

From: Clément Mathieu--Drif We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-of

[PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Reviewed-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 772b1cea88..7b0c22fc07 100644 --- a/hw/i386/intel_iommu.c +++ b/hw

[PATCH ats_vtd v5 21/22] intel_iommu: set the address mask even when a translation fails

From: Clément Mathieu--Drif Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/

[PATCH ats_vtd v5 11/22] memory: store user data pointer in the IOMMU notifiers

From: Clément Mathieu--Drif This will help developers of svm devices to track a state Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 0067b2266a..359bca2ae2 100644 --- a/inclu

[PATCH ats_vtd v5 10/22] pci: add IOMMU operations to get address spaces and memory regions with PASID

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 19 +++ include/hw/pci/pci.h | 34 ++ 2 files changed, 53 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 51feede3cf..3fe47d4002 100644 --- a

[PATCH ats_vtd v5 19/22] memory: add an API for ATS support

From: Clément Mathieu--Drif IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 26 +

[PATCH ats_vtd v5 01/22] intel_iommu: fix FRCD construction macro.

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel

[PATCH 3/4] hw/dma: Add a trace log for a description loading failure

Due to a description loading failure, adding a trace log makes observing the DMA behavior easy. Signed-off-by: Fea.Wang --- hw/dma/trace-events| 3 +++ hw/dma/xilinx_axidma.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/hw/dma/trace-events b/hw/dma/trace-events index 3c47df54e4..9

[PATCH 4/4] hw/net: Fix the transmission return size

Fix the transmission return size because not all bytes could be transmitted successfully. So, return a successful length instead of a constant value. Signed-off-by: Fea.Wang --- hw/net/xilinx_axienet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/xilinx_axienet.c b/

[PATCH 1/4] hw/dma: Enhance error handling in loading description

Loading a description from memory may cause a bus-error. In this case, the DMA should stop working, set the error flag, and return the error value. Signed-off-by: Fea.Wang --- hw/dma/xilinx_axidma.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/dma/xili

[PATCH 2/4] hw/dma: Break the loop when loading descriptions fails

When calling the loading a description function, it should be noticed that the function may return a failure value. Breaking the loop is one of the possible ways to handle it. Signed-off-by: Fea.Wang --- hw/dma/xilinx_axidma.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff -

[PATCH 0/4] hw/dma: Add error handling for loading descriptions failing

The original code assumes that memory transmission is always successful, but in some cases, it gets bus-error. Add error handling for DMA reading description failures. Do some reasonable settings, and return the corrected transmission size. Finally, return the error status. base-commit: 1806da76c

Re: [PATCH v13 03/13] virtio-gpu: Handle virtio_gpu_virgl_init() failure

On 2024/06/03 14:26, Dmitry Osipenko wrote: On 6/2/24 08:34, Akihiko Odaki wrote: +typedef enum { +    RS_START,   /* starting state */ +    RS_INIT_FAILED, /* failed initialisation */ Is the distinction between RS_START and RS_INIT_FAILED really necessary? The state stays in RS_INIT_FAI

Re: [PATCH v13 11/13] virtio-gpu: Handle resource blob commands

On 2024/06/03 14:32, Dmitry Osipenko wrote: On 6/2/24 08:45, Akihiko Odaki wrote: ... +    case HOSTMEM_MR_FINISH_UNMAPPING: +    ret = virgl_renderer_resource_unmap(res->base.resource_id); +    if (ret) { +    qemu_log_mask(LOG_GUEST_ERROR, +  "%s: failed

Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

On Wed, Apr 3, 2024 at 5:10 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

RE: [PATCH v4 11/16] aspeed/intc: Add AST2700 support

Hi Cedric, > From: Cédric Le Goater > Subject: Re: [PATCH v4 11/16] aspeed/intc: Add AST2700 support > > On 5/27/24 10:02, Jamin Lin wrote: > > AST2700 interrupt controller(INTC) provides hardware interrupt > > interfaces to interrupt of processors PSP, SSP and TSP. In INTC, each > > interrupt o

Re: [PATCH v13 11/13] virtio-gpu: Handle resource blob commands

On 6/2/24 08:45, Akihiko Odaki wrote: ... >> +    case HOSTMEM_MR_FINISH_UNMAPPING: >> +    ret = virgl_renderer_resource_unmap(res->base.resource_id); >> +    if (ret) { >> +    qemu_log_mask(LOG_GUEST_ERROR, >> +  "%s: failed to unmap virgl resource: %s\n",

Re: [PATCH intel_iommu 0/7] FLTS for VT-d

On 02/06/2024 16:10, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Mon, Apr 22, 2024 at 03:52:52PM +, CLEMENT MATHIEU--DRIF wrote: >> This series is the firs

Re: [PATCH v13 03/13] virtio-gpu: Handle virtio_gpu_virgl_init() failure

On 6/2/24 08:34, Akihiko Odaki wrote: >> +typedef enum { >> +    RS_START,   /* starting state */ >> +    RS_INIT_FAILED, /* failed initialisation */ > > Is the distinction between RS_START and RS_INIT_FAILED really necessary? The state stays in RS_INIT_FAILED once was failed until virtio-gpu

[QEMU][PATCH v3 1/1] hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue

Returning an uint32_t casted to a gint from g_cmp_ids causes the tx queue to become wrongly sorted when executing g_slist_sort. Fix this by always returning -1 or 1 from g_cmp_ids based on the ID comparison instead. Also, if two message IDs are the same, sort them by using their index and transmit

Re: [RFC PATCH 08/10] ppc/pnv: Invert the design for big-core machine modelling

On Thu May 30, 2024 at 5:46 PM AEST, Cédric Le Goater wrote: > > >>> @@ -157,6 +157,14 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, > >>> void *fdt) > >>> > >>>pnv_cc->processor_id(chip, pc->hwid, 0, &pir, &tir); > >>> > >>> +/* Only one DT node per (big) core */ > >>>

Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations

On 5/31/24 12:44, Max Chou wrote: The vector unit-stride load/store instructions (e.g. vle8.v/vse8.v) perform continuous load/store. We can replace the corresponding helper functions by TCG ops to copy more data at a time with following assumptions: * Perform virtual address resolution once for

Re: [PATCH] Use "void *" as parameter for functions that are used for aio_set_event_notifier()

On Wed, May 29, 2024 at 07:49:48PM +0200, Thomas Huth wrote: > aio_set_event_notifier() and aio_set_event_notifier_poll() in > util/aio-posix.c and util/aio-win32.c are casting function pointers of > functions that take an "EventNotifier *" pointer as parameter to function > pointers that take a "v

Re: [PATCH V12 0/8] Add architecture agnostic code to support vCPU Hotplug

On Thu, May 30, 2024 at 12:42:33AM +0100, Salil Mehta wrote: > Virtual CPU hotplug support is being added across various architectures[1][3]. > This series adds various code bits common across all architectures: > > 1. vCPU creation and Parking code refactor [Patch 1] > 2. Update ACPI GED framewor

Re: [PATCH v3] vhost-user-gpu: fix import of DMABUF

On Wed, May 15, 2024 at 02:52:37PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > When using vhost-user-gpu with GL, qemu -display gtk doesn't show output > and prints: qemu: eglCreateImageKHR failed > > Since commit 9ac06df8b ("virtio-gpu-udmabuf: correct naming of > Qe

Re: [PATCH v6 0/3] Support RISC-V IOPMP

Hi Dainel, Sorry for the delayed response. I've been busy over the past two months. I plan to submit the next version of the patch within two weeks. Thanks, Ethan Chen On Mon, May 27, 2024 at 09:09:49AM -0300, Daniel Henrique Barboza wrote: > Hi Ethan, > > > Did you send v7 already and I someh

Re: [PATCH] accel/tcg: nochain should disable goto_ptr

On 2024/6/1 21:36, Richard Henderson wrote: On 6/1/24 00:57, niugen wrote: on 2024/6/1 01:32, Richard Henderson wrote: On 5/31/24 03:17, NiuGenen wrote: Signed-off-by: NiuGenen ---   accel/tcg/cpu-exec.c | 2 +-   1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c

Re: [PATCH] virtio-blk: remove SCSI passthrough functionality

On Wed, May 08, 2024 at 01:32:03PM +0200, Paolo Bonzini wrote: > The legacy SCSI passthrough functionality has never been enabled for > VIRTIO 1.0 and was deprecated more than four years ago. > > Get rid of it---almost, because QEMU is advertising it unconditionally > for legacy virtio-blk devices

Re: [PATCH] virtio-pci: Fix the use of an uninitialized irqfd.

On Wed, May 29, 2024 at 9:54 PM Fiona Ebner wrote: > > Hi, > > Am 22.05.24 um 07:10 schrieb Cindy Lu: > > The crash was reported in MAC OS and NixOS, here is the link for this bug > > https://gitlab.com/qemu-project/qemu/-/issues/2334 > > https://gitlab.com/qemu-project/qemu/-/issues/2321 > > > >

Re: [PATCH] hw/cxl: Fix read from bogus memory

On Fri, May 31, 2024 at 11:22:05AM -0500, Ira Weiny wrote: > Peter and coverity report: > > We've passed '&data' to address_space_write(), which means "read > from the address on the stack where the function argument 'data' > lives", so instead of writing 64 bytes of data to the

Re: [PATCH 0/2] qapi: Remove deprecated events

On Thu, May 30, 2024 at 09:15:46AM +0200, Philippe Mathieu-Daudé wrote: > Remove MEM_UNPLUG_ERROR and 'vcpu' field in TRACE events, > all deprecated since long enough. > > Philippe Mathieu-Daudé (2): > hw/acpi: Remove the deprecated QAPI MEM_UNPLUG_ERROR event > trace: Remove deprecated 'vcpu'

Re: [PATCH V2 0/3] improve -overcommit cpu-pm=on|off

On Thu, May 30, 2024 at 04:49:33PM +0200, Igor Mammedov wrote: > On Thu, 30 May 2024 21:54:47 +0800 > Zhao Liu wrote: > > > Hi Zide, > > > > On Wed, May 29, 2024 at 10:31:21AM -0700, Chen, Zide wrote: > > > Date: Wed, 29 May 2024 10:31:21 -0700 > > > From: "Chen, Zide" > > > Subject: Re: [PATCH

Re: [PATCH v10 2/2] virtio-pci: implement No_Soft_Reset bit

On Wed, May 15, 2024 at 03:35:26PM +0800, Jiqian Chen wrote: > In current code, when guest does S3, virtio-gpu are reset due to the > bit No_Soft_Reset is not set. After resetting, the display resources > of virtio-gpu are destroyed, then the display can't come back and only > show blank after resu

Re: [PULL 25/72] Adds migration support for Branch History Rolling Buffer (BHRB) internal state.

On Sat Jun 1, 2024 at 6:06 AM AEST, Fabiano Rosas wrote: > Nicholas Piggin writes: > > > From: Glenn Miles > > > > Reviewed-by: Nicholas Piggin > > Signed-off-by: Glenn Miles > > Signed-off-by: Nicholas Piggin > > --- > > target/ppc/machine.c | 21 + > > 1 file changed, 21

Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

On 5/11/24 7:10 AM, Alexey Baturo wrote: From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/ris

Re: [PATCH intel_iommu 0/7] FLTS for VT-d

On Mon, Apr 22, 2024 at 03:52:52PM +, CLEMENT MATHIEU--DRIF wrote: > This series is the first of a list that add support for SVM in the Intel > IOMMU. > > Here, we implement support for first-stage translation in VT-d. > The PASID-based IOTLB invalidation is also added in this series as it is

Re: [PATCH v4] hw/audio/virtio-snd: Always use little endian audio format

On Mon, Apr 22, 2024 at 11:18:30PM +0200, Philippe Mathieu-Daudé wrote: > The VIRTIO Sound Device conforms with the Virtio spec v1.2, > thus only use little endianness. > > Remove the suspicious target_words_bigendian() noticed during > code review. > > Cc: qemu-sta...@nongnu.org > Fixes: eb9ad37

Re: [PATCH-for-9.0?] docs: i386: pc: Update maximum CPU numbers for PC Q35

On Fri, Apr 12, 2024 at 11:57:35AM +0200, Philippe Mathieu-Daudé wrote: > Hi Zhao, > > On 12/4/24 10:53, Zhao Liu wrote: > > From: Zhao Liu > > > > Commit e4e98c7eebfa ("pc: q35: Bump max_cpus to 4096 vcpus") increases > > the supported CPUs for PC Q35 machine. > > > > Update maximum CPU number

Re: [PATCH-for-9.0?] docs: i386: pc: Update maximum CPU numbers for PC Q35

On Fri, Apr 12, 2024 at 04:53:58PM +0800, Zhao Liu wrote: > From: Zhao Liu > > Commit e4e98c7eebfa ("pc: q35: Bump max_cpus to 4096 vcpus") increases > the supported CPUs for PC Q35 machine. > > Update maximum CPU numbers for PC Q35 in the document. > > Signed-off-by: Zhao Liu Acked-by: Mich

Re: [PATCH 4/5] x86/loader: expose unpatched kernel

On Thu, Apr 11, 2024 at 11:48:28AM +0200, Gerd Hoffmann wrote: > Add a new "etc/boot/kernel" fw_cfg file, containing the kernel without > the setup header patches. Intended use is booting in UEFI with secure > boot enabled, where the setup header patching breaks secure boot > verification. > > Ne

Re: [PATCH] vhost-user-test: no set non-blocking for cal fd less than 0.

On Thu, Apr 11, 2024 at 03:35:55PM +0800, Yuxue Liu yuxue@jaguarmicro.com wrote: > From: Yuxue Liu > > In the scenario where vhost-user sets eventfd to -1, > qemu_chr_fe_get_msgfds retrieves fd as -1. When vhost_user_read > receives, it does not perform blocking operations on the descriptor

Re: [PATCH v2 3/5] intel_iommu: Add a framework to do compatibility check with host IOMMU cap/ecap

On Fri, Apr 26, 2024 at 03:10:14AM +, Duan, Zhenzhong wrote: > > > >-Original Message- > >From: Cédric Le Goater > >Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do > >compatibility check with host IOMMU cap/ecap > > > >On 4/25/24 10:46, Duan, Zhenzhong wrote: > >> Hi C

Re: [PATCH] i386: removes microvm from default build since microvm doesn't support Xen accel.

02.06.2024 13:38, Will Gyda wrote: i386: removes microvm from default build since microvm doesn't support Xen accel. Hm. Maybe we should remove xen from default build instead? Thanks, /mjt

[PATCH] i386: removes microvm from default build since microvm doesn't support Xen accel.

i386: removes microvm from default build since microvm doesn't support Xen accel. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2294 Signed-off-by: Will Gyda --- configs/devices/i386-softmmu/default.mak | 1 - hw/i386/Kconfig | 2 ++ 2 files changed, 2 inser

Re: [PATCH] target/i386: fix SSE and SSE2 featue check

On Sun, Jun 02, 2024 at 06:09:04PM +0800, lixinyu...@ict.ac.cn wrote: > Date: Sun, 2 Jun 2024 18:09:04 +0800 > From: lixinyu...@ict.ac.cn > Subject: [PATCH] target/i386: fix SSE and SSE2 featue check > X-Mailer: git-send-email 2.34.1 > > From: Xinyu Li > > Featues check of CPUID_SSE and CPUID_S

[PATCH] target/i386: fix SSE and SSE2 featue check

From: Xinyu Li Featues check of CPUID_SSE and CPUID_SSE2 shoule use cpuid_features, rather than cpuid_ext_features Signed-off-by: Xinyu Li --- target/i386/tcg/decode-new.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386

[PATCH] target/i386: fix memory opsize for Mov to/from Seg

From: Xinyu Li This commit fixes an issue with MOV instructions (0x8C and 0x8E) involving segment registers by explicitly setting the memory operand size to 16 bits. It introduces a new flag X86_SPECIAL_MovSeg to handle this specification correctly. Signed-off-by: Xinyu Li --- target/i386/tcg/

Re: [PATCH 2/6] meson: assume x86-64-v2 baseline ISA

On Fri, May 31, 2024 at 11:14:53AM +0200, Paolo Bonzini wrote: > Date: Fri, 31 May 2024 11:14:53 +0200 > From: Paolo Bonzini > Subject: [PATCH 2/6] meson: assume x86-64-v2 baseline ISA > X-Mailer: git-send-email 2.45.1 > > x86-64-v2 processors were released in 2008, assume that we have one. > Unf

Re: [PATCH 6/6] host/i386: assume presence of POPCNT

On Fri, May 31, 2024 at 11:14:57AM +0200, Paolo Bonzini wrote: > Date: Fri, 31 May 2024 11:14:57 +0200 > From: Paolo Bonzini > Subject: [PATCH 6/6] host/i386: assume presence of POPCNT > X-Mailer: git-send-email 2.45.1 > > QEMU now requires an x86-64-v2 host, which has the POPCNT instruction. > U

Re: [PATCH 5/6] host/i386: assume presence of SSSE3

On Fri, May 31, 2024 at 11:14:56AM +0200, Paolo Bonzini wrote: > Date: Fri, 31 May 2024 11:14:56 +0200 > From: Paolo Bonzini > Subject: [PATCH 5/6] host/i386: assume presence of SSSE3 > X-Mailer: git-send-email 2.45.1 > > QEMU now requires an x86-64-v2 host, which has SSSE3 instructions > (notabl

Re: [PATCH 4/6] host/i386: assume presence of SSE2

On Fri, May 31, 2024 at 11:14:55AM +0200, Paolo Bonzini wrote: > Date: Fri, 31 May 2024 11:14:55 +0200 > From: Paolo Bonzini > Subject: [PATCH 4/6] host/i386: assume presence of SSE2 > X-Mailer: git-send-email 2.45.1 > > QEMU now requires an x86-64-v2 host, which has SSE2. > Use it freely in buff

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