[PATCH v2] virtio-iommu: add error check before assert

A fuzzer case discovered by Zheyu Ma causes an assert failure. Add a check before the assert, and respond with an error before moving on to the next queue element. To reproduce the failure: cat << EOF | \ qemu-system-x86_64 \ -display none -machine accel=qtest -m 512M -machine q35 -nodefaults \

Re: [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU

On Wed, Jun 12, 2024 at 04:14:02PM +0800, Jim Shu wrote: > [EXTERNAL MAIL] > > It is the preparation patch for upcoming RISC-V wgChecker device. > > Since RISC-V wgChecker could permit access in RO/WO permission, the > IOMMUMemoryRegion could return different section for read & write > access.

Re: [PULL 00/25] target/i386, SCSI changes for 2024-06-11

On 6/11/24 07:24, Paolo Bonzini wrote: The following changes since commit 80e8f0602168f451a93e71cbb1d59e93d745e62e: Merge tag 'bsd-user-misc-2024q2-pull-request' of gitlab.com:bsdimp/qemu into staging (2024-06-09 11:21:55 -0700) are available in the Git repository at:

Re: [PATCH v1] virtio-iommu: add error check before assert

On Wed, 12 Jun 2024 11:56, Alex Bennée wrote: Manos Pitsidianakis writes: On Tue, 11 Jun 2024 at 18:01, Philippe Mathieu-Daudé wrote: On 11/6/24 14:23, Manos Pitsidianakis wrote: > A fuzzer case discovered by Zheyu Ma causes an assert failure. > > Add a check before the assert, and

Re: [PATCH v1] virtio-iommu: add error check before assert

On Wed, 12 Jun 2024 12:46, Alex Bennée wrote: Manos Pitsidianakis writes: A fuzzer case discovered by Zheyu Ma causes an assert failure. Add a check before the assert, and respond with an error before moving on to the next queue element. To reproduce the failure: cat << EOF | \

Re: Qemu License question

Manos Pitsidianakis writes: > On Thu, 13 Jun 2024 06:26, Peng Fan wrote: >>Hi All, >> >>The following files are marked as GPL-3.0-or-later. Will these >>Conflict with Qemu LICENSE? >> >>Should we update the files to GPL-2.0? >> >>./tests/tcg/aarch64/semicall.h:7: * SPDX-License-Identifier:

[PATCH] Update event idx if guest has made extra buffers during double check

Fixes: 06b12970174 ("virtio-net: fix network stall under load") If guest has made some buffers available during double check, but the total buffer size available is lower than @bufsize, notify the guest with the latest available idx(event idx) seen by the host. --- hw/net/virtio-net.c | 1 + 1

Re: [RFC PATCH v2 0/5] Implement ARM PL011 in Rust

Good morning Daniel, On Wed, 12 Jun 2024 11:37, "Daniel P. Berrangé" wrote: On Tue, Jun 11, 2024 at 01:33:29PM +0300, Manos Pitsidianakis wrote: .gitignore | 2 + .gitlab-ci.d/buildtest.yml | 64 ++-- MAINTAINERS| 13 + configure

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

Good morning Paolo, On Thu, 13 Jun 2024 00:27, Paolo Bonzini wrote: Il mer 12 giu 2024, 22:58 Manos Pitsidianakis < manos.pitsidiana...@linaro.org> ha scritto: In any case, it is out of scope for this RFC. Introducing wrappers would be a gradual process. Sure, how would you feel about

Re: Qemu License question

On Thu, 13 Jun 2024 06:26, Peng Fan wrote: Hi All, The following files are marked as GPL-3.0-or-later. Will these Conflict with Qemu LICENSE? Should we update the files to GPL-2.0? ./tests/tcg/aarch64/semicall.h:7: * SPDX-License-Identifier: GPL-3.0-or-later

Qemu License question

Hi All, The following files are marked as GPL-3.0-or-later. Will these Conflict with Qemu LICENSE? Should we update the files to GPL-2.0? ./tests/tcg/aarch64/semicall.h:7: * SPDX-License-Identifier: GPL-3.0-or-later ./tests/tcg/x86_64/system/boot.S:13: * SPDX-License-Identifier:

RE: [PATCH] Hexagon: lldb read/write predicate registers p0/p1/p2/p3

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Wednesday, June 12, 2024 12:30 PM > To: ltaylorsimp...@gmail.com > Cc: qemu-devel@nongnu.org; bc...@quicinc.com; tedw...@quicinc.com; > alex.ben...@linaro.org; quic_mathb...@quicinc.com; > sidn...@quicinc.com;

Re: [RFC PATCH] memory: Introduce memory region fetch operation

On Wed, Jun 12, 2024 at 01:43:41PM +0100, Peter Maydell wrote: > > On Wed, 12 Jun 2024 at 10:02, Ethan Chen via wrote: > > > > Allow the memory region to have different behaviors for read and fetch > > operations. > > > > For example RISCV IOPMP will raise interrupt when cpu try to fetch a > >

[PATCH v3 1/3] hw/dma: Enhance error handling in loading description

Loading a description from memory may cause a bus-error. In this case, the DMA should stop working, set the error flag, and return the failure value. When calling the loading a description function, it should be noticed that the function may return a failure value. Breaking the loop in this case

[PATCH v3 2/3] hw/dma: Add a trace log for a description loading failure

Due to a description loading failure, adding a trace log makes observing the DMA behavior easy. Signed-off-by: Fea.Wang Reviewed-by: Edgar E. Iglesias Reviewed-by: Frank Chang --- hw/dma/trace-events| 3 +++ hw/dma/xilinx_axidma.c | 3 +++ 2 files changed, 6 insertions(+) diff --git

[PATCH v3 0/3] hw/dma: Add error handling for loading descriptions failing

The original code assumes that memory transmission is always successful, but in some cases, it gets bus-error. Add error handling for DMA reading description failures. Do some reasonable settings, and return the corrected transmission size. Finally, return the error status. * Fix the trace

[PATCH v3 3/3] hw/net: Fix the transmission return size

Fix the transmission return size because not all bytes could be transmitted successfully. So, return a successful length instead of a constant value. Signed-off-by: Fea.Wang Reviewed-by: Edgar E. Iglesias Reviewed-by: Frank Chang --- hw/net/xilinx_axienet.c | 2 +- 1 file changed, 1

Re: [PATCH v2 2/3] hw/dma: Add a trace log for a description loading failure

Sure, I will fix it in the next patch series. Thank you Sincerely, Fea On Mon, Jun 10, 2024 at 7:49 PM Philippe Mathieu-Daudé wrote: > Hi Fea, > > On 4/6/24 09:15, Fea.Wang wrote: > > Due to a description loading failure, adding a trace log makes observing > > the DMA behavior easy. > > > >

RE: [PATCH v8 4/7] migration/multifd: add qpl compression method

> -Original Message- > From: Fabiano Rosas > Sent: Wednesday, June 12, 2024 10:31 PM > To: Liu, Yuan1 ; pet...@redhat.com; > pbonz...@redhat.com; marcandre.lur...@redhat.com; berra...@redhat.com; > th...@redhat.com; phi...@linaro.org > Cc: qemu-devel@nongnu.org; Liu, Yuan1 ; Zou, Nanhai >

RE: [PATCH v8 4/7] migration/multifd: add qpl compression method

> -Original Message- > From: Fabiano Rosas > Sent: Wednesday, June 12, 2024 10:27 PM > To: Liu, Yuan1 ; pet...@redhat.com; > pbonz...@redhat.com; marcandre.lur...@redhat.com; berra...@redhat.com; > th...@redhat.com; phi...@linaro.org > Cc: qemu-devel@nongnu.org; Liu, Yuan1 ; Zou, Nanhai >

Re: [RFC PATCH v2 0/2] ui/gtk: Introduce new param - Connectors

On 6/11/2024 11:42 PM, Marc-André Lureau wrote: Hi On Tue, Jun 11, 2024 at 10:28 PM Kim, Dongwon > wrote: Hi Marc-André, On 6/5/2024 12:26 AM, Marc-André Lureau wrote: > Hi > > On Tue, Jun 4, 2024 at 9:59 PM Kim, Dongwon

Re: [PULL 0/6] Tracing patches

On 6/10/24 10:13, Stefan Hajnoczi wrote: The following changes since commit 80e8f0602168f451a93e71cbb1d59e93d745e62e: Merge tag 'bsd-user-misc-2024q2-pull-request' of gitlab.com:bsdimp/qemu into staging (2024-06-09 11:21:55 -0700) are available in the Git repository at:

Re: [PATCH 21/32] hw/sd: Add mmc switch function support

On 3/7/23 15:24, Cédric Le Goater wrote: From: Sai Pavan Boddu switch operation in mmc cards, updated the ext_csd register to request changes in card operations. Here we implement similar sequence but requests are mostly dummy and make no change. Implement SWITCH_ERROR if the write operation

Re: [PATCH 20/32] hw/sd: Add CMD21 tuning sequence

On 13/6/24 00:15, Philippe Mathieu-Daudé wrote: On 3/7/23 15:24, Cédric Le Goater wrote: From: Sai Pavan Boddu MMC cards support different tuning sequence for entering HS200 mode. Signed-off-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias [ clg: - ported on QEMU 7.0 ] Signed-off-by:

Re: [PATCH 26/32] hw/sd: Fix SET_BLOCK_COUNT command argument

On 3/7/23 15:25, Cédric Le Goater wrote: The number of blocks is defined in the lower bits [15:0]. TODO: This needs to be more precise on the spec version. Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/sd/sd.c

Re: [PATCH 20/32] hw/sd: Add CMD21 tuning sequence

On 3/7/23 15:24, Cédric Le Goater wrote: From: Sai Pavan Boddu MMC cards support different tuning sequence for entering HS200 mode. Signed-off-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias [ clg: - ported on QEMU 7.0 ] Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 40

[PULL 1/5] xen: mapcache: Make MCACHE_BUCKET_SHIFT runtime configurable

From: "Edgar E. Iglesias" Make MCACHE_BUCKET_SHIFT runtime configurable per cache instance. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini Reviewed-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 54 ++- 1 file changed, 33

Re: [PATCH 0/2] Bug fixes for plugins

Pierrick Bouvier writes: > Those two commits are meant to be applied on top of current series > <20240612153508.1532940-1-alex.ben...@linaro.org> > > The first fixes issue with windows plugins, while the second is a bug that > concerns memory callbacks, and due to a previous refactoring. Queued

[PULL 2/5] xen: mapcache: Unmap first entries in buckets

From: "Edgar E. Iglesias" When invalidating memory ranges, if we happen to hit the first entry in a bucket we were never unmapping it. This was harmless for foreign mappings but now that we're looking to reuse the mapcache for transient grant mappings, we must unmap entries when invalidated.

[PULL 5/5] hw/arm: xen: Enable use of grant mappings

From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini Reviewed-by: Manos Pitsidianakis Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/xen_arm.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/arm/xen_arm.c b/hw/arm/xen_arm.c index

[PULL 4/5] xen: mapcache: Add support for grant mappings

From: "Edgar E. Iglesias" Add a second mapcache for grant mappings. The mapcache for grants needs to work with XC_PAGE_SIZE granularity since we can't map larger ranges than what has been granted to us. Like with foreign mappings (xen_memory), machines using grants are expected to initialize

[PULL 3/5] xen: mapcache: Pass the ram_addr offset to xen_map_cache()

From: "Edgar E. Iglesias" Pass the ram_addr offset to xen_map_cache. This is in preparation for adding grant mappings that need to compute the address within the RAMBlock. No functional changes. Signed-off-by: Edgar E. Iglesias Reviewed-by: David Hildenbrand Reviewed-by: Stefano Stabellini

[PULL 0/5] virtio-grants-v8-tag

The following changes since commit 80e8f0602168f451a93e71cbb1d59e93d745e62e: Merge tag 'virtio-grants-v8-tag' into staging (2024-06-09 11:21:55 -0700) are available in the Git repository at: https://gitlab.com/sstabellini/qemu.git for you to fetch changes up to

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

Il mer 12 giu 2024, 22:58 Manos Pitsidianakis < manos.pitsidiana...@linaro.org> ha scritto: > In any case, it is out of scope for this RFC. Introducing wrappers would > be a gradual process. > Sure, how would you feel about such bindings being developed on list, and maintained in a (somewhat)

Re: [PATCH 9/9] contrib/plugins: add ips plugin example for cost modeling

* Alex Bennée (alex.ben...@linaro.org) wrote: > From: Pierrick Bouvier > > This plugin uses the new time control interface to make decisions > about the state of time during the emulation. The algorithm is > currently very simple. The user specifies an ips rate which applies > per core. If the

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

On Wed, 12 Jun 2024 19:06, "Daniel P. Berrangé" wrote: On Wed, Jun 12, 2024 at 05:14:56PM +0300, Manos Pitsidianakis wrote: On Wed, 12 Jun 2024 15:29, Paolo Bonzini wrote: > I think this is extremely useful to show where we could go in the task > of creating more idiomatic bindings. > > On

Re: [PATCH] accel/tcg/plugin: Fix inject_mem_cb rw masking

On 6/5/24 15:39, Pierrick Bouvier wrote: Thanks for catching this Richard. I did the same mistake in plugins/core.c as well, could you fix it as well as part of this patch? For complement, rw are enums, R is 0b01, W is 0b10, and RW is 0b11, thus it work as expected with &. Thanks, Pierrick

Re: [PATCH 8/9] plugins: add time control API

On 6/12/24 12:37, Alex Bennée wrote: Pierrick Bouvier writes: Hi Alex, I noticed the new symbols lack QEMU_PLUGIN_API qualifier in include/qemu/qemu-plugin.h: - qemu_plugin_update_ns - qemu_plugin_request_time_control So it would be impossible to use those symbols on windows. I kept a

[PATCH 0/2] Bug fixes for plugins

Those two commits are meant to be applied on top of current series <20240612153508.1532940-1-alex.ben...@linaro.org> The first fixes issue with windows plugins, while the second is a bug that concerns memory callbacks, and due to a previous refactoring. Pierrick Bouvier (2): plugins: missing

[PATCH 2/2] plugins: fix inject_mem_cb rw masking

These are not booleans, but masks. Issue found by Richard Henderson. Fixes: f86fd4d8721 ("plugins: distinct types for callbacks") Signed-off-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- accel/tcg/plugin-gen.c | 4 ++-- plugins/core.c | 4 ++-- 2 files changed, 4

[PATCH 1/2] plugins: missing QEMU_PLUGIN_API for time control

Signed-off-by: Pierrick Bouvier --- include/qemu/qemu-plugin.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h index 80b1637cede..310ee10f301 100644 --- a/include/qemu/qemu-plugin.h +++ b/include/qemu/qemu-plugin.h @@ -670,6 +670,7 @@

Re: [PATCH] hw/usb/hcd-ohci: Fix ohci_service_td: accept valid TDs

On Wed, Jun 12, 2024 at 2:36 PM Alex Bennée wrote: > Cord Amfmgm writes: > > > On Wed, Jun 12, 2024 at 9:21 AM Alex Bennée > wrote: > > > > David Hubbard writes: > > > > > From: Cord Amfmgm > > > > > > This changes the way the ohci emulation handles a Transfer Descriptor > with > > >

Re: [PATCH 8/9] plugins: add time control API

Pierrick Bouvier writes: > Hi Alex, > > I noticed the new symbols lack QEMU_PLUGIN_API qualifier in > include/qemu/qemu-plugin.h: > - qemu_plugin_update_ns > - qemu_plugin_request_time_control > > So it would be impossible to use those symbols on windows. > > I kept a reminder to send a new

Re: [PATCH] hw/usb/hcd-ohci: Fix ohci_service_td: accept valid TDs

Cord Amfmgm writes: > On Wed, Jun 12, 2024 at 9:21 AM Alex Bennée wrote: > > David Hubbard writes: > > > From: Cord Amfmgm > > > > This changes the way the ohci emulation handles a Transfer Descriptor with > > "Current Buffer Pointer" set to "Buffer End" + 1. > > > > The OHCI spec

Re: [PATCH v4 5/5] iotests: add backup-discard-source

On 11.06.24 20:49, Kevin Wolf wrote: Am 13.03.2024 um 16:28 hat Vladimir Sementsov-Ogievskiy geschrieben: Add test for a new backup option: discard-source. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Fiona Ebner Tested-by: Fiona Ebner This test fails for me, and it already

[PATCH 0/4] i386/cpu: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model

This series adds the support for following features in qemu. 1. RAS feature bits (SUCCOR, McaOverflowRecov) 2. perfmon-v2 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits 4. Add support for EPYC-Turin Babu Moger (3): i386/cpu: Add RAS feature bits on EPYC CPU models i386/cpu: Enable

[PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa

Following feature bits are added on EPYC-Genoa-v2 model. perfmon-v2: Allows guests to make use of the PerfMonV2 features. SUCCOR: Software uncorrectable error containment and recovery capability. The processor supports software containment of uncorrectable errors through

[PATCH 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models

Add the support for following RAS features bits on AMD guests. SUCCOR: Software uncorrectable error containment and recovery capability. The processor supports software containment of uncorrectable errors through context synchronizing data poisoning and deferred error

[PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit

From: Sandipan Das CPUID leaf 0x8022, i.e. ExtPerfMonAndDbg, advertises new performance monitoring features for AMD processors. Bit 0 of EAX indicates support for Performance Monitoring Version 2 (PerfMonV2) features. If found to be set during PMU initialization, the EBX bits can be used to

[PATCH 4/4] i386/cpu: Add support for EPYC-Turin model

Adds the support for AMD EPYC zen 5 processors(EPYC-Turin). Adds the following new feature bits on top of the feature bits from the previous generation EPYC models. movdiri: Move Doubleword as Direct Store Instruction movdir64b : Move 64 Bytes as Direct Store Instruction

Re: [PATCH 2/4] migration: Rename thread debug names

Peter Xu writes: > The postcopy thread names on dest QEMU are slightly confusing, partly I'll > need to blame myself on 36f62f11e4 ("migration: Postcopy preemption > preparation on channel creation"). E.g., "fault-fast" reads like a fast > version of "fault-default", but it's actually the fast

Re: [PATCH] ui/gtk: Wait until the current guest frame is rendered before switching to RUN_STATE_SAVE_VM

On 6/11/2024 10:44 PM, Marc-André Lureau wrote: Hi On Wed, Jun 12, 2024 at 5:29 AM Kim, Dongwon > wrote: Hi, From: Marc-André Lureau mailto:marcandre.lur...@gmail.com>> Sent: Wednesday, June 5, 2024 12:56 AM To: Kim, Dongwon

Re: [PATCH v2 18/18] migration/ram: Add direct-io support to precopy file migration

Peter Xu writes: > On Wed, Jun 12, 2024 at 07:15:19PM +0100, Daniel P. Berrangé wrote: >> IIUC, with the "fixed-ram" feature, the on-disk format of a saved VM >> should end up the same whether we're using traditional migration, or >> multifd migration. Use of multifd is simply an optimization

Sample 'qapi-schema-diff' output for v9.0.0 vs origin/master

Hiya, here's some draft output of a script I'm working on to summarize QMP wire format differences between QEMU versions. This script works in terms of the QMP *wire format*, not the QAPI *specification*. As a consequence, *almost* all type names are stripped from this output and all nested

Re: [PATCH] Hexagon: lldb read/write predicate registers p0/p1/p2/p3

On Wed, 12 Jun 2024 10:42:39 -0600 Taylor Simpson wrote: > > diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c > index 502c6987f0..e67e627fc9 100644 > --- a/target/hexagon/gdbstub.c > +++ b/target/hexagon/gdbstub.c > @@ -56,6 +64,15 @@ int hexagon_gdb_write_register(CPUState *cs,

Re: [PATCH v2 18/18] migration/ram: Add direct-io support to precopy file migration

On Wed, Jun 12, 2024 at 07:15:19PM +0100, Daniel P. Berrangé wrote: > IIUC, with the "fixed-ram" feature, the on-disk format of a saved VM > should end up the same whether we're using traditional migration, or > multifd migration. Use of multifd is simply an optimization that lets > us write RAM

Re: [PATCH v2 18/18] migration/ram: Add direct-io support to precopy file migration

On Wed, Jun 12, 2024 at 03:08:02PM -0300, Fabiano Rosas wrote: > Fabiano Rosas writes: > > > Peter Xu writes: > > > >> On Mon, Jun 10, 2024 at 02:45:53PM -0300, Fabiano Rosas wrote: > I looked into this and it's cumbersome: > > - We'd need to check migrate_direct_io() several times, once to

Re: [PATCH v2 18/18] migration/ram: Add direct-io support to precopy file migration

Fabiano Rosas writes: > Peter Xu writes: > >> On Mon, Jun 10, 2024 at 02:45:53PM -0300, Fabiano Rosas wrote: >>> >> AIUI, the issue here that users are already allowed to specify in >>> >> libvirt the equivalent to direct-io and multifd independent of each >>> >> other (bypass-cache, parallel).

Re: [PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs

On 2024-06-12 1:50 pm, Philippe Mathieu-Daudé wrote: On 12/6/24 14:48, Peter Maydell wrote: On Wed, 12 Jun 2024 at 13:33, Philippe Mathieu-Daudé wrote: Hi Zhenyu, On 12/6/24 04:05, Zhenyu Zhang wrote: diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3c93c0c0a6..3cefac6d43 100644 ---

Re: [PATCH] hw/usb/hcd-ohci: Fix ohci_service_td: accept valid TDs

On Wed, Jun 12, 2024 at 9:21 AM Alex Bennée wrote: > David Hubbard writes: > > > From: Cord Amfmgm > > > > This changes the way the ohci emulation handles a Transfer Descriptor > with > > "Current Buffer Pointer" set to "Buffer End" + 1. > > > > The OHCI spec 4.3.1.2 Table 4-2 allows td.cbp to

Re: [PATCH 0/5] Reinstate ability to use Qemu on pre-SSE4.1 x86 hosts

On Wed, Jun 12, 2024 at 7:00 PM Daniel P. Berrangé wrote: > > I guess that, because these helpers are called by TCG, you wouldn't > > pay the price of the indirect call. However, adding all this > > infrastructure for 13-15 year old CPUs is not very enthralling. > > Rather than re-introducing a

Re: [PATCH 0/5] Reinstate ability to use Qemu on pre-SSE4.1 x86 hosts

On Wed, Jun 12, 2024 at 04:09:29PM +0100, Daniel P. Berrangé wrote: > On Wed, Jun 12, 2024 at 01:21:26PM +0100, Daniel P. Berrangé wrote: > > On Wed, Jun 12, 2024 at 01:51:31PM +0200, Paolo Bonzini wrote: > > > On Wed, Jun 12, 2024 at 1:38 PM Daniel P. Berrangé > > > wrote: > > > > This isn't

[PATCH] cpu: fix memleak of 'halt_cond' and 'thread'

Since a4c2735f35 (cpu: move Qemu[Thread|Cond] setup into common code, 2024-05-30) these fields are now allocated at cpu_common_initfn(). So let's make sure we also free them at cpu_common_finalize(). Furthermore, the code also frees these on round robin, but we missed 'halt_cond'. Signed-off-by:

Re: [PATCH 0/5] Reinstate ability to use Qemu on pre-SSE4.1 x86 hosts

On Wed, Jun 12, 2024 at 01:51:31PM +0200, Paolo Bonzini wrote: > On Wed, Jun 12, 2024 at 1:38 PM Daniel P. Berrangé > wrote: > > If we want to use POPCNT in the TCG code, can we not do a runtime check > > and selectively build pieces of code with > > __attribute__((target("popcnt"))), > > as

[PATCH] Hexagon: lldb read/write predicate registers p0/p1/p2/p3

hexagon-core.xml only exposes register p3_0 which is an alias that aggregates the predicate registers. It is more convenient for users to interact directly with the predicate registers. Tested with lldb downloaded from this location

Re: [PATCH 0/5] Reinstate ability to use Qemu on pre-SSE4.1 x86 hosts

On Wed, Jun 12, 2024 at 06:40:09PM +0300, Alexander Monakov wrote: > > On Wed, 12 Jun 2024, Daniel P. Berrangé wrote: > > > I learnt that FESCo approved a surprisingly loose rule saying > > > > "Libraries packaged in Fedora may require ISA extensions, > >however any packaged application

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

On Wed, Jun 12, 2024 at 05:14:56PM +0300, Manos Pitsidianakis wrote: > On Wed, 12 Jun 2024 15:29, Paolo Bonzini wrote: > > I think this is extremely useful to show where we could go in the task > > of creating more idiomatic bindings. > > > > On Tue, Jun 11, 2024 at 12:34 PM Manos Pitsidianakis

Re: [PATCH 3/9] plugins: Ensure register handles are not NULL

On 6/12/24 08:35, Alex Bennée wrote: From: Akihiko Odaki Ensure register handles are not NULL so that a plugin can assume NULL is invalid as a register handle. Signed-off-by: Akihiko Odaki Message-Id: <20240229-null-v1-1-e716501d9...@daynix.com> Signed-off-by: Alex Bennée ---

Re: [PATCH 2/9] gdbstub: move enums into separate header

On 6/12/24 08:35, Alex Bennée wrote: This is an experiment to further reduce the amount we throw into the exec headers. It might not be as useful as I initially thought because just under half of the users also need gdbserver_start(). Signed-off-by: Alex Bennée --- include/exec/gdbstub.h

Re: [PATCH 1/9] include/exec: add missing include guard comment

On 6/12/24 08:35, Alex Bennée wrote: Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index eb14b91139..008a92198a 100644 --- a/include/exec/gdbstub.h +++

Re: [PATCH 8/9] plugins: add time control API

Hi Alex, I noticed the new symbols lack QEMU_PLUGIN_API qualifier in include/qemu/qemu-plugin.h: - qemu_plugin_update_ns - qemu_plugin_request_time_control So it would be impossible to use those symbols on windows. I kept a reminder to send a new patch after you pulled this, but if we go to

Re: [PATCH v3 2/4] usb/hub: mark as deprecated

Daniel P. Berrangé writes: > On Thu, Jun 06, 2024 at 04:30:08PM +0200, Gerd Hoffmann wrote: >> The hub supports only USB 1.1. When running out of usb ports it is in >> almost all cases the much better choice to add another usb host adapter >> (or increase the number of root ports when using

Re: [PATCH v2 8/9] target/arm: Add aarch64_tcg_ops

On 6/12/24 07:36, Alex Bennée wrote: What happens when the CPU is running mixed mode code and jumping between 64 and 32 bit? Wouldn't it be easier to have a helper that routes to the correct unwinder, c.f. gen_intermediate_code GDB can't switch modes, so there is *never* any mode switching.

Re: [PATCH v3] accel/tcg: Fix typo causing tb->page_addr[1] to not be recorded

Anton Johansson via writes: > For TBs crossing page boundaries, the 2nd page will never be > recorded/removed, as the index of the 2nd page is computed from the > address of the 1st page. This is due to a typo, fix it. > > Cc: qemu-sta...@nongnu.org > Fixes: deba78709a ("accel/tcg: Always lock

Re: [PATCH 0/5] Reinstate ability to use Qemu on pre-SSE4.1 x86 hosts

On Wed, 12 Jun 2024, Daniel P. Berrangé wrote: > I learnt that FESCo approved a surprisingly loose rule saying > > "Libraries packaged in Fedora may require ISA extensions, >however any packaged application must not crash on any >officially supported architecture, either by providing

[PATCH 2/9] gdbstub: move enums into separate header

This is an experiment to further reduce the amount we throw into the exec headers. It might not be as useful as I initially thought because just under half of the users also need gdbserver_start(). Signed-off-by: Alex Bennée --- include/exec/gdbstub.h| 9 - include/gdbstub/enums.h

[PATCH 0/9] maintainer updates (gdbstub, plugins, time control)

Hi, This is the current state of my maintainer trees. The gdbstub patches are just minor clean-ups. The main feature this brings in is the ability for plugins to control time. This has been discussed before but represents the first time plugins can "control" the execution of the core. The idea

[PATCH 8/9] plugins: add time control API

Expose the ability to control time through the plugin API. Only one plugin can control time so it has to request control when loaded. There are probably more corner cases to catch here. From: Alex Bennée Signed-off-by: Pierrick Bouvier [AJB: tweaked user-mode handling] Signed-off-by: Alex

[PATCH 5/9] qtest: use cpu interface in qtest_clock_warp

This generalises the qtest_clock_warp code to use the AccelOps handlers for updating its own sense of time. This will make the next patch which moves the warp code closer to pure code motion. From: Alex Bennée Acked-by: Thomas Huth Signed-off-by: Pierrick Bouvier Signed-off-by: Alex Bennée

[PATCH 7/9] qtest: move qtest_{get, set}_virtual_clock to accel/qtest/qtest.c

From: Pierrick Bouvier Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240530220610.1245424-5-pierrick.bouv...@linaro.org> --- include/sysemu/qtest.h | 3 --- accel/qtest/qtest.c| 12 system/qtest.c | 12 3 files

[PATCH 1/9] include/exec: add missing include guard comment

Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index eb14b91139..008a92198a 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -144,4 +144,4 @@ void

[PATCH 9/9] contrib/plugins: add ips plugin example for cost modeling

From: Pierrick Bouvier This plugin uses the new time control interface to make decisions about the state of time during the emulation. The algorithm is currently very simple. The user specifies an ips rate which applies per core. If the core runs ahead of its allocated execution time the plugin

[PATCH 4/9] sysemu: add set_virtual_time to accel ops

We are about to remove direct calls to individual accelerators for this information and will need a central point for plugins to hook into time changes. From: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Pierrick Bouvier Signed-off-by: Alex Bennée Message-Id:

[PATCH 3/9] plugins: Ensure register handles are not NULL

From: Akihiko Odaki Ensure register handles are not NULL so that a plugin can assume NULL is invalid as a register handle. Signed-off-by: Akihiko Odaki Message-Id: <20240229-null-v1-1-e716501d9...@daynix.com> Signed-off-by: Alex Bennée --- plugins/api.c | 4 ++-- 1 file changed, 2

[PATCH 6/9] sysemu: generalise qtest_warp_clock as qemu_clock_advance_virtual_time

Move the key functionality of moving time forward into the clock sub-system itself. This will allow us to plumb in time control into plugins. From: Alex Bennée Signed-off-by: Pierrick Bouvier Signed-off-by: Alex Bennée Message-Id: <20240530220610.1245424-4-pierrick.bouv...@linaro.org> ---

Re: [RFC PATCH] migration/savevm: do not schedule snapshot_save_job_bh in qemu_aio_context

On Wed, 12 Jun 2024 at 05:21, Fiona Ebner wrote: > > Am 11.06.24 um 16:04 schrieb Stefan Hajnoczi: > > On Tue, Jun 11, 2024 at 02:08:49PM +0200, Fiona Ebner wrote: > >> Am 06.06.24 um 20:36 schrieb Stefan Hajnoczi: > >>> On Wed, Jun 05, 2024 at 02:08:48PM +0200, Fiona Ebner wrote: > The fact

Re: [PATCH 0/5] Reinstate ability to use Qemu on pre-SSE4.1 x86 hosts

On Wed, Jun 12, 2024 at 5:09 PM Daniel P. Berrangé wrote: > This might suggest we could put a runtime feature check in main(), > print a warning and then exit(1), however, QEMU has alot of code > that is triggered from ELF constructors. If we're building the > entire of QEMU codebase with extra

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

On Wed, Jun 12, 2024 at 4:42 PM Manos Pitsidianakis wrote: > There was consensus in the community call that we won't be writing Rust > APIs for internal C QEMU interfaces; or at least, that's not the goal I disagree with that. We need _some_ kind of bindings, otherwise we have too much unsafe

Re: [PATCH 0/5] Reinstate ability to use Qemu on pre-SSE4.1 x86 hosts

On Wed, Jun 12, 2024 at 01:21:26PM +0100, Daniel P. Berrangé wrote: > On Wed, Jun 12, 2024 at 01:51:31PM +0200, Paolo Bonzini wrote: > > On Wed, Jun 12, 2024 at 1:38 PM Daniel P. Berrangé > > wrote: > > > This isn't anything to do with the distro installer. The use case is that > > > the distro

Re: [PATCH 3/4] migration: Use MigrationStatus instead of int

On Wed, Jun 12, 2024 at 10:42:27AM -0400, Peter Xu wrote: > @@ -1544,7 +1545,7 @@ bool migration_in_postcopy(void) > } > } > > -bool migration_postcopy_is_alive(int state) > +bool migration_postcopy_is_alive(MigrationStatus state) > { > switch (state) { > case

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

On Wed, 12 Jun 2024 15:29, Paolo Bonzini wrote: I think this is extremely useful to show where we could go in the task of creating more idiomatic bindings. On Tue, Jun 11, 2024 at 12:34 PM Manos Pitsidianakis wrote: +fn main() { +println!("cargo::rerun-if-env-changed=MESON_BUILD_DIR"); +

[PATCH 2/4] migration: Rename thread debug names

The postcopy thread names on dest QEMU are slightly confusing, partly I'll need to blame myself on 36f62f11e4 ("migration: Postcopy preemption preparation on channel creation"). E.g., "fault-fast" reads like a fast version of "fault-default", but it's actually the fast version of

[PATCH 4/4] migration/postcopy: Add postcopy-recover-setup phase

This patch adds a migration state on src called "postcopy-recover-setup". The new state will describe the intermediate step starting from when the src QEMU started an postcopy recovery request, until the migration channels are properly established, but before the recovery process take place. The

[PATCH 0/4] migration: New postcopy state, and some cleanups

The major goal of this patchset is patch 4, which introduced a new postcopy state so that we will send an event in postcopy reconnect failures that Libvirt would prefer to have. There's more information for that issue in the commit message alone. Patch 1-2 are cleanups that are not directly

[PATCH 1/4] migration/multifd: Avoid the final FLUSH in complete()

We always do the flush when finishing one round of scan, and during complete() phase we should scan one more round making sure no dirty page existed. In that case we shouldn't need one explicit FLUSH at the end of complete(), as when reaching there all pages should have been flushed.

[PATCH 3/4] migration: Use MigrationStatus instead of int

QEMU uses "int" in most cases even if it stores MigrationStatus. I don't know why, so let's try to do that right and see what blows up.. Signed-off-by: Peter Xu --- migration/migration.h | 9 + migration/migration.c | 13 +++-- 2 files changed, 12 insertions(+), 10

Re: [PATCH v2 0/9] plugins: Use unwind info for special gdb registers

Richard Henderson writes: > This is an attempt to fix > https://gitlab.com/qemu-project/qemu/-/issues/2208 > ("PC is not updated for each instruction in TCG plugins") > > I have only updated target/{i386,arm} so far, but basically all > targets need updating for the new callbacks. Extra points

Re: [PATCH v2 8/9] target/arm: Add aarch64_tcg_ops

Richard Henderson writes: > For the moment, this is an exact copy of arm_tcg_ops. > Export arm_cpu_exec_interrupt for the cross-file reference. > > Signed-off-by: Richard Henderson > --- > target/arm/internals.h | 1 + > target/arm/cpu.c | 2 +- > target/arm/cpu64.c | 30

Re: assert fails in s390x TCG

On 12/6/24 15:08, Claudio Fontana wrote: On 6/12/24 14:41, Philippe Mathieu-Daudé wrote: On 28/7/23 18:43, Richard Henderson wrote: On 7/28/23 09:05, Richard Henderson wrote: It's the page containing both code and a page table entry that concerns me.  It seems like a kernel bug, though

Re: [PATCH 0/3] memory: Constify IOMMUTLBEvent in memory_region_notify_iommu*()

On Wed, Jun 12, 2024 at 03:25:28PM +0200, Philippe Mathieu-Daudé wrote: > Trivial patches using const IOMMUTLBEvent. > > Philippe Mathieu-Daudé (3): > memory: Constify IOMMUTLBEvent in memory_region_notify_iommu_one() > memory: Constify IOMMUTLBEvent in memory_region_notify_iommu() >

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