On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote:
> There is already a hash32_bat_prot() function that does most if this
> and the rest can be inlined. Export hash32_bat_prot() and rename it to
> ppc_hash32_bat_prot() to match other functions and use it in
> get_bat_6xx_tlb().
Reviewed-by
Sorry, the patch missing "(( ))"
Replace "& VTD_IQA_QS" with "& (VTD_IQA_QS | VTD_IQA_DW_MASK))" is correct.
Revised patch as follows,
Signed-off-by: yeeli
---
hw/i386/intel_iommu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu
On Thu, Jul 4, 2024 at 2:01 AM Michael Roth wrote:
> Currently if the 'legacy-vm-type' property of the sev-guest object is
> left unset, QEMU will attempt to use the newer KVM_SEV_INIT2 kernel
> interface in conjunction with the newer KVM_X86_SEV_VM and
> KVM_X86_SEV_ES_VM KVM VM types.
>
> This c
On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote:
> Replace some BAT related constants with defines from mmu-hash32.h
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 26 +-
> 1 file changed, 13 insertions(+), 13
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Rename parameter of get_bat_6xx_tlb() from virtual to eaddr to match
> other functions.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 18 +-
> 1 file changed, 9 inser
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Pass raddr and prot in function parameters instead.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 26 +-
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
On 7/3/24 23:19, Xiaoyao Li wrote:
On 7/4/2024 11:14 AM, Ewan Hai wrote:
On 7/3/24 10:49, Xiaoyao Li wrote:
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macr
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Pass it as a function parameter and remove it from mmu_ctx_t.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 26 ++
> 1 file changed, 14 insertions(+), 12 dele
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> The ppc6xx_tlb_check() relies on the caller to initialise raddr field
> in ctx. Move this init from the only caller into the function.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 4
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> This is used only once and can be inlined.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu-hash32.c | 19 ---
> 1 file changed, 4 insertions(+), 15 deletions(-)
>
> diff --git a/t
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Add a function to get key bit from SR and use it instead of open coded
> version.
>
Nice.
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu-hash32.c | 9 ++---
> target/ppc/mmu-hash32.h | 5
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Instead of passing around ptem in context use it once in the same
> function so it can be removed from mmu_ctx_t.
The downside here is now updating the SPRs in different places.
You already passed hash back with a pointer elsewhere, wha
On Thu, May 30, 2024 at 12:24:58PM +, CLEMENT MATHIEU--DRIF wrote:
> This series belongs to a list of series that add SVM support for VT-d.
>
> Here we focus on the implementation of PRI support in the IOMMU and on a
> PCI-level
> API for PRI to be used by virtual devices.
>
> This work is b
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> This function is only called once and we can make the caller simpler
> by inlining it.
I'm inclined to agree. Splitting into function can be nice,
but translating return values here is pretty horrible.
I think it looks right.
Reviewed-
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> In mmu6xx_get_physical_address() the switch handles all cases so the
> default is never reached and can be dropped. Also group together cases
> which just return -4.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> In mmu6xx_get_physical_address() tagtet_page_bits local is declared
> only to use TARGET_PAGE_BITS once. Drop the unneeded variable.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 4 +
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> In mmu6xx_get_physical_address() ds is used as bool, declare it as
> such. Also use named constant instead of hex value.
Oh nx was bool, ignore my previous comment then.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Pass it as a parameter instead. Also use named constants instead of
> hex values when extracting bits from SR.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 24 --
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> This function is used only once, its return value is ignored and one
> of its parameter is a return value from a previous call. It is better
> to inline it in the caller and remove it.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/pp
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Return hash value via a parameter and remove it from mmu_ctx.t.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 19 ---
> 1 file changed, 8 insertions(+), 11 deletions(
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> The eaddr field of mmu_ctx_t is set once but never used so can be
> removed.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/tar
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Invert conditions to avoid deep nested ifs and return early instead.
> Remove some obvious comments that don't add more clarity.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 43
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Instead of using a local ret variable return directly and remove the
> local.
>
> Signed-off-by: BALATON Zoltan
Some people probably prefer the existing style but I don't
mind early returns.
Reviewed-by: Nicholas Piggin
> ---
> targ
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> In ppc6xx_tlb_pte_check() the pp variable is used only once to pass it
> to a function parameter with the same name. Remove the local and
> inline the value. Also use named constant for the hex value to make it
> clearer.
>
Reviewed-by:
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> In ppc6xx_tlb_pte_check() the pteh variable is used only once to
> compare to the h parameter of the function. Inline its value and use
> pteh name for the function parameter which is more descriptive.
>
> Signed-off-by: BALATON Zoltan
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> The ptev variable in ppc6xx_tlb_pte_check() is used only once and just
> obfuscates an otherwise clear value. Get rid of it.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 5 ++---
>
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> The ptem variable in ppc6xx_tlb_pte_check() is used only once,
> simplify by removing it as the value is already clear itself without
> adding a local name for it.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
>
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> The mmask local variable is a less descriptive local name for a
> constant. Drop it and use the constant directly in the two places it
> is needed.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu
On Mon May 27, 2024 at 9:12 AM AEST, BALATON Zoltan wrote:
> Reorganise ppc_hash32_pp_prot() swapping the if legs so it does not
> test for negative first and clean up to make it shorter. Also rename
> it to ppc_hash32_prot().
Rename makes sense since it's not entirely derived from pp but
also key
On 03/07/2024 21.45, Michael S. Tsirkin wrote:
On Wed, Jul 03, 2024 at 08:46:38PM +0200, Thomas Huth wrote:
On 03/07/2024 19.01, Richard Henderson wrote:
On 7/3/24 09:51, Michael S. Tsirkin wrote:
On Wed, Jul 03, 2024 at 09:31:45AM -0700, Richard Henderson wrote:
On 7/2/24 13:15, Michael S. T
On 03/07/2024 22.26, Michael S. Tsirkin wrote:
On Wed, Jul 03, 2024 at 08:46:38PM +0200, Thomas Huth wrote:
On 03/07/2024 19.01, Richard Henderson wrote:
On 7/3/24 09:51, Michael S. Tsirkin wrote:
On Wed, Jul 03, 2024 at 09:31:45AM -0700, Richard Henderson wrote:
On 7/2/24 13:15, Michael S. T
On Thu, Jul 4, 2024 at 2:26 AM Michael Roth wrote:
> > Michael, any ideas? Is there a way for the host to retrieve the supported
> > CPUID bits for SEV-SNP guests?
>
> If we want to support -cpu host, then I don't really see a way around
> needing to maintain a filter of some sort sanitize what g
From: Cédric Le Goater
Hello,
This series enables boot from eMMC on the rainier-bmc machine, which
is the default behavior and also on the AST2600 EVB using a machine
option to change the default.
It depends solely on the availability of an eMMC device model which is
currently being discussed u
From: Cédric Le Goater
The QEMU device representing the eMMC device of machine is currently
created with type SD_CARD. Change the type to EMMC now that it is
available.
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --gi
From: Cédric Le Goater
Report support on the AST2600 SoC if the boot-from-eMMC HW strapping
bit is set at the board level. AST2700 also has support but it is not
yet ready in QEMU and others SoCs do not have support, so return false
always for these.
Signed-off-by: Cédric Le Goater
---
include
From: Cédric Le Goater
This value is taken from a running Rainier machine.
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 135f4eb72215..abd2412ad8b9 100644
--- a/hw/arm/aspeed.c
+++
From: Cédric Le Goater
The default behavior of some Aspeed machines is to boot from the eMMC
device, like the rainier-bmc. Others like ast2600-evb could also boot
from eMMC if the HW strapping boot-from-eMMC bit was set. Add a
property to set or unset this bit. This is useful to test boot images.
From: Cédric Le Goater
The first boot area partition (64K) of the eMMC device should contain
an initial boot loader (u-boot SPL). Load it as a ROM only if an eMMC
device is available to boot from but no flash device is.
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 8 +---
1 file c
From: Cédric Le Goater
When the boot-from-eMMC HW strapping bit is set, use the 'boot-config'
property to set the boot config register to boot from the first boot
area partition of the eMMC device.
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 15 +++
1 file changed, 11 ins
From: Cédric Le Goater
To change default behavior of a machine and boot from eMMC, future
changes will add a machine option to let the user configure the
boot-from-eMMC HW strapping bit. Add a new machine attribute first.
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 6 +-
1 file c
From: Cédric Le Goater
Bit SCU500[2] of the AST2600 controls the boot device of the SoC.
Future changes will configure this bit to boot from eMMC disk images
specially built for this purpose.
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
include/hw/misc/aspeed_scu.h | 4 +++
On Thu, Jul 4, 2024 at 6:10 AM Xiaoyao Li wrote:
> > So there are specific ranges that are checked, mainly ones where there
> > is potential for guests to misbehave if they are being lied to. But
> > hypervisor-ranges are paravirtual in a sense so there's no assumptions
> > being made about what t
Hello Jamin,
I think that, first, we should introduce a container region. In this container
region would be mapped a sub region for the current set of registers. This
container region would be the one that the SoC maps as it is done today.
Then, in a second patch, we should introduce a extra su
From: yeeli
When dmar_readq or devmem2 read the DW of IQA always 0UL because
"& VTD_IQA_QS". So, try to fix it.
case:
after vtd_mem_write
IQA val: 0x100206801
after vtd_mem_read
IQA val: 0x100206001
Signed-off-by: yeeli
---
hw/i386/intel_iommu.c | 3 ++-
1 file changed, 2 insertions(+), 1 de
On 03/07/2024 14:32, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links,
> unless this email comes from a known sender and you know the content
> is safe.
>
Hi, thanks for your review! very efficient!
>
> Hi CMD,
>
> I've went through the series. Some general suggestio
On 03/07/2024 14:14, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links,
> unless this email comes from a known sender and you know the content
> is safe.
>
>
> On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
>> From: Clément Mathieu--Drif
>>
>> IOMMU have to implem
On 03/07/2024 14:04, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links,
> unless this email comes from a known sender and you know the content
> is safe.
>
>
> On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
>> From: Clément Mathieu--Drif
>>
>> Signed-off-by: Cléme
On 03/07/2024 09:29, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links,
> unless this email comes from a known sender and you know the content
> is safe.
>
>
> On 2024/7/2 23:29, CLEMENT MATHIEU--DRIF wrote:
>>
>> On 02/07/2024 15:33, Yi Liu wrote:
>>> Caution: Exte
On 03/07/2024 13:59, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links,
> unless this email comes from a known sender and you know the content
> is safe.
>
>
> On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
>> From: Clément Mathieu--Drif
>>
>> We use this informat
On 7/4/2024 8:34 AM, Michael Roth wrote:
On Tue, Jul 02, 2024 at 11:07:18AM +0800, Xiaoyao Li wrote:
On 5/30/2024 7:16 PM, Pankaj Gupta wrote:
From: Michael Roth
SEV-SNP firmware allows a special guest page to be populated with a
table of guest CPUID values so that they can be validated throu
According to RISC-V Debug specification, the optional textra32 and
textra64 trigger CSRs can be used to configure additional matching
conditions for the triggers. For example, if the textra.MHSELECT field
is set to 4 (mcontext), this trigger will only match or fire if the low
bits of mcontext/hcont
This commit allows program to write textra trigger CSR for type 2, 3, 6
triggers. In this preliminary patch, the textra.MHVALUE and the
textra.MHSELECT fields are allowed to be configured. Other fields, such
as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to
zero for now.
For
According to RISC-V Debug specification, the optional textra32 and textra64
trigger CSRs can be used to configure additional matching conditions for the
triggers.
This series support to write MHVALUE and MHSELECT fields into textra32 and
textra64 trigger CSRs. Besides, the additional matching cond
Loongarch ipi is added herei, it inherits from class
TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and
cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can
be used when ipi is emulated in userspace with kvm mode.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c
Loongarch ipi inherits from class LoongsonIPICommonClass, and it only
contains Loongarch 3A5000 virt machine specific interfaces, rather than
mix different machine implementations together.
Signed-off-by: Bibo Mao
---
hw/intc/Kconfig | 3 +++
hw/intc/meson.build | 1 +
hw/loo
Like loongarch ipi, reconstruct this driver by inheriting class
LoongsonIPICommonClass. Add extra function loongson_ipi_realize()
to implement mmio memory region.
Signed-off-by: Bibo Mao
---
hw/intc/loongson_ipi.c | 330 +++--
hw/intc/meson.build|
Loongson ipi common class and instance is created here, it comes
from file loongson_ipi mostly. For the new added loongson ipi
common class, there is four interfaces defined here:
1. Interfaces pre_save/post_load are used for future kvm child class
2. Interface get_iocsr_as can be used for differ
Now loongson ipi and loongarch ipi share the same code with different
macro, loongson ipi has its separate function such mmio region,
loongarch ipi has other requirement such as irqchip in kernel.
Interrupt irqchip has strong relationship with architecture, since
it sends irq to vcpu and interface
Since the downstream port is not checked, two slots can be linked to
a single port. However, this can prevent the driver from detecting the
device properly.
It is necessary to ensure that a downstream port is not linked more than
once.
Links:
https://lore.kernel.org/qemu-devel/oszpr01mb6453bc61d
On Fri Jun 14, 2024 at 9:36 AM AEST, Salil Mehta wrote:
> From: Jean-Philippe Brucker
>
> When a KVM vCPU is reset following a PSCI CPU_ON call, its power state
> is not synchronized with KVM at the moment. Because the vCPU is not
> marked dirty, we miss the call to kvm_arch_put_registers() that w
Hi,
The block layer codes has been reviewed by Stefan.
Could you help me review the scsi and nvme layer codes.
On 2024/6/27 10:53, 卢长奇 wrote:
> the block layer code has been reviewed by Stefan.
On 7/4/2024 11:14 AM, Ewan Hai wrote:
On 7/3/24 10:49, Xiaoyao Li wrote:
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and
> -Original Message-
> From: Peter Xu
> Sent: Wednesday, July 3, 2024 3:16 AM
> To: Wang, Yichen
> Cc: Paolo Bonzini ; Daniel P. Berrangé
> ; Eduardo Habkost ; Marc-André
> Lureau ; Thomas Huth ;
> Philippe Mathieu-Daudé ; Fabiano Rosas
> ; Eric Blake ; Markus Armbruster
> ; Laurent Vivie
On 7/3/24 10:49, Xiaoyao Li wrote:
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and VIA vendors to align their behavior wit
On Fri Jun 14, 2024 at 9:36 AM AEST, Salil Mehta wrote:
[...]
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 60b160d0b4..60b4778da9 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
[...]
> +/**
> + * qemu_get_cpu_archid:
> + * @cpu_index: possible vCPU fo
On Fri Jun 14, 2024 at 9:36 AM AEST, Salil Mehta wrote:
> PMU for all possible vCPUs must be initialized at the VM initialization time.
> Refactor existing code to accomodate possible vCPUs. This also assumes that
> all
> processor being used are identical.
>
> Past discussion for reference:
> Lin
On Fri Jun 7, 2024 at 9:56 PM AEST, Salil Mehta wrote:
> @@ -400,6 +411,12 @@ static void acpi_ged_initfn(Object *obj)
> memory_region_init_io(&ged_st->regs, obj, &ged_regs_ops, ged_st,
>TYPE_ACPI_GED "-regs", ACPI_GED_REG_COUNT);
> sysbus_init_mmio(sbd, &ged_s
Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC
machine.
Signed-off-by: Zhao Liu
---
Changes since RFC v2:
* Used cache_supported array.
---
hw/i386/pc.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 77415064c62e..1614a3b1bf19 1006
Introduce smp-cache object so that user could define cache properties.
In smp-cache object, define cache topology based on CPU topology level
with two reasons:
1. In practice, a cache will always be bound to the CPU container
(either private in the CPU container or shared among multiple
con
Allows cache to be defined at the thread and module level. This
increases flexibility for x86 users to customize their cache topology.
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.
User will configure smp cache topology via smp-cache object.
For this case, update the x86 CPUs' cache topology with user's
configuration in MachineState.
Signed-off-by: Zhao Liu
---
Changes since RFC v2:
* Used smp_cache array to override cache topology.
* Wrapped the updating into a function
Add cache_supported flags in SMPCompatProps to allow machines to
configure various caches support.
And implement check() method for machine's "smp-cache" link property,
which will check the compatibility of the cache properties with the
machine support.
Signed-off-by: Zhao Liu
---
Changes since
Signed-off-by: Zhao Liu
---
Changes since RFC v2:
* Rewrote the document of smp-cache object.
Changes since RFC v1:
* Use "*_cache=topo_level" as -smp example as the original "level"
term for a cache has a totally different meaning. (Jonathan)
---
qemu-options.hx | 58 ++
Cache topology needs to be defined based on CPU topology levels. Thus,
define CPU topology enumeration in qapi/machine.json to make it generic
for all architectures.
To match the general topology naming style, rename CPU_TOPO_LEVEL_SMT
and CPU_TOPO_LEVEL_PACKAGE to CPU_TOPO_LEVEL_THREAD and
CPU_TO
With smp-cache object support, add smp cache topology for machine by
linking the smp-cache object.
Also add a helper to access cache topology level.
Signed-off-by: Zhao Liu
---
Changes since RFC v2:
* Linked machine's smp_cache to smp-cache object instead of a builtin
structure. This is to g
Hi all,
Since the previous RFC v2, I've reimplemented smp-cache object based on
Daniel's comment (thanks Daniel!), which is both flexible to support
current cache topology requirements and extensible.
So, I officially convert the RFC to PATCH.
Background on smp cache topology can be found in the
Hi Cedric,
>
> On 7/3/24 10:16 AM, Jamin Lin wrote:
> > ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the
> > base address of dram is "0x4 " which is 64bits address.
> >
> > It have "Normal Priority Transmit Ring Base Address Register
> > High(0x17C)", "High Priority Tra
On Fri Jun 14, 2024 at 9:36 AM AEST, Salil Mehta wrote:
> ARM arch does not allow CPUs presence to be changed [1] after kernel has
> booted.
> Hence, firmware/ACPI/Qemu must ensure persistent view of the vCPUs to the
> Guest
> kernel even when they are not present in the QoM i.e. are unplugged or
On Tue, Jul 02, 2024 at 11:07:18AM +0800, Xiaoyao Li wrote:
> On 5/30/2024 7:16 PM, Pankaj Gupta wrote:
> > From: Michael Roth
> >
> > SEV-SNP firmware allows a special guest page to be populated with a
> > table of guest CPUID values so that they can be validated through
> > firmware before bein
On Wed, Jul 03, 2024 at 01:01:32PM +0200, Paolo Bonzini wrote:
> Some CPUID features may be provided by KVM for some guests, independent of
> processor support, for example TSC deadline or TSC adjust. They are not going
> to be present in named models unless the vendor implements them in hardware,
On Tue, Jun 25, 2024 at 10:51:43AM +0100, Daniel P. Berrangé wrote:
> On Mon, Jun 24, 2024 at 08:19:19PM -0500, Michael Roth wrote:
> > On Fri, Jun 14, 2024 at 11:39:24AM +0100, Daniel P. Berrangé wrote:
> > > The KVM_SEV_INIT2 ioctl was only introduced in Linux 6.10, which will
> > > only have bee
Currently if the 'legacy-vm-type' property of the sev-guest object is
left unset, QEMU will attempt to use the newer KVM_SEV_INIT2 kernel
interface in conjunction with the newer KVM_X86_SEV_VM and
KVM_X86_SEV_ES_VM KVM VM types.
This can lead to measurement changes if, for instance, an SEV guest w
On Wed, Jul 03, 2024 at 03:37:43PM -0700, Richard Henderson wrote:
> On 7/3/24 13:26, Michael S. Tsirkin wrote:
> > On Wed, Jul 03, 2024 at 08:46:38PM +0200, Thomas Huth wrote:
> > > On 03/07/2024 19.01, Richard Henderson wrote:
> > > > On 7/3/24 09:51, Michael S. Tsirkin wrote:
> > > > > On Wed, J
On Fri, Jun 07, 2024 at 12:56:41PM +0100, Salil Mehta wrote:
> Virtual CPU hotplug support is being added across various architectures[1][3].
> This series adds various code bits common across all architectures:
>
> 1. vCPU creation and Parking code refactor [Patch 1]
> 2. Update ACPI GED framewor
From: Sunil V L
so that ACPI table test can be supported.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Igor Mammedov
Message-Id: <20240625150839.1358279-12-suni...@ventanamicro.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
meson.build | 2
From: Stefano Garzarella
In vu_message_write() we use sendmsg() to send the message header,
then a write() to send the payload.
If sendmsg() fails we should avoid sending the payload, since we
were unable to send the header.
Discovered before fixing the issue with the previous patch, where
send
From: Sunil V L
Update the list of supported architectures to include RISC-V.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Igor Mammedov
Message-Id: <20240625150839.1358279-14-suni...@ventanamicro.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
From: Jonathan Cameron
New DCD command definitions updated in response to review comments
from Markus.
- Used Cxl instead of CXLX for newly added types.
- Expanded some abreviations in type names to be easier to read.
- Additional documentation for some fields.
- Replace slightly vague c
From: Akihiko Odaki
num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF
instead.
Signed-off-by: Akihiko Odaki
Message-Id: <20240627-reuse-v10-8-7ca0b8ed3...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
include/hw/pci/pcie_sriov.h | 1 -
From: Thomas Weißschuh
The missing functionality has been implemented now.
This reverts commit e739d1935c461d0668057e9dbba9d06f728d29ec.
Signed-off-by: Thomas Weißschuh
Message-Id: <20240527-pvpanic-shutdown-v8-8-5a28ec025...@t-8ch.de>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S.
From: Jonah Palmer
Add support to virtio-ccw devices for handling the extra data sent from
the driver to the device when the VIRTIO_F_NOTIFICATION_DATA transport
feature has been negotiated.
The extra data that's passed to the virtio-ccw device when this feature
is enabled varies depending on th
From: Akihiko Odaki
romsize is an uint32_t variable. Specifying -1 as an uint32_t value is
obscure way to denote UINT32_MAX.
Worse, if int is wider than 32-bit, it will change the behavior of a
construct like the following:
romsize = -1;
if (romsize != -1) {
...
}
When -1 is assigned to rom
From: Sunil V L
Same machine name can be used by different architectures. Hence, create
aarch64 folder and move all aarch64 related AML files for virt machine
inside.
Signed-off-by: Sunil V L
Reviewed-by: Igor Mammedov
Message-Id: <20240625150839.1358279-11-suni...@ventanamicro.com>
Reviewed-b
From: Sunil V L
Existing AARCH64 virt test functions do not have AARCH64 in their name.
To add RISC-V virt related test cases, better to rename existing
functions to indicate they are ARM only.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Igor Mammedov
Message-Id: <2024
From: Sunil V L
Since machine name can be common for multiple architectures (ex: virt),
add "arch" in the path to search for expected AML files. Since the AML
files are still under old path, add support for searching with and
without arch in the path.
Signed-off-by: Sunil V L
Acked-by: Alistair
From: Sunil V L
To test ACPI tables, edk2 needs to be booted with a disk image having
EFI partition. This image is created using UefiTestToolsPkg.
The image is generated using tests/uefi-test-tools source.
Signed-off-by: Sunil V L
Message-Id: <20240625150839.1358279-5-suni...@ventanamicro.com>
From: Akihiko Odaki
Disable SR-IOV VF devices by reusing code to power down PCI devices
instead of removing them when the guest requests to disable VFs. This
allows to realize devices and report VF realization errors at PF
realization time.
Signed-off-by: Akihiko Odaki
Message-Id: <20240627-reu
From: Sunil V L
edk2-funcs.sh which is used in this Makefile, was removed in the commit
c28a2891f3 ("edk2: update build script"). It is replaced with a python
based script. So, update the Makefile and add the configuration file as
required to support the python based build script.
Signed-off-by:
From: Akihiko Odaki
pci_new() aborts when creating a VF with a function number equals to or
is greater than PCI_DEVFN_MAX.
Signed-off-by: Akihiko Odaki
Message-Id: <20240627-reuse-v10-5-7ca0b8ed3...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
docs/pcie_s
From: Akihiko Odaki
A PF may automatically create VFs and the PF may be function 0.
Signed-off-by: Akihiko Odaki
Message-Id: <20240627-reuse-v10-3-7ca0b8ed3...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/ppc/spapr_pci.c | 4 +++-
1 file changed, 3 ins
1 - 100 of 392 matches
Mail list logo
