Guest and host formats in struct FWCfgVMCoreInfo are written in little endian
format. However, the hypervisor host might be big endian. We need to do
appropriate conversions between the formats before comparing the values. Fix it.
Signed-off-by: Ani Sinha
---
hw/misc/vmcoreinfo.c | 3 ++-
1 file
Hello Mike,
On 7/11/24 22:57, Mike Kowal wrote:
Hello Cedric,
This patch will be split into 5 patches to ease the review. I also acknowledge
most of your other comments.
Can you elaborate on the gic_get_current_cpu() comment?
Did you want me to use that method name to get a the current CPU
On Fri, 12 Jul 2024 00:23, Pierrick Bouvier wrote:
On 7/9/24 06:00, Daniel P. Berrangé wrote:
On Tue, Jul 09, 2024 at 02:28:38PM +0200, Paolo Bonzini wrote:
On Tue, Jul 9, 2024 at 2:09 PM Peter Maydell wrote:
* what is the actual baseline requirement? We definitely want
to support "usi
On Fri, Jul 12, 2024 at 11:06:49AM +0900, David Stevens wrote:
> On Thu, Jul 11, 2024 at 7:56 PM Alyssa Ross wrote:
> >
> > Adding David Stevens, who implemented SHMEM_MAP and SHMEM_UNMAP in
> > crosvm a couple of years ago.
> >
> > David, I'd be particularly interested for your thoughts on the ME
Collin Walling writes:
> It is beneficial to provide an interface to retrieve *all* deprecated
> features in one go. Management applications will need this information
> to determine which features need to be disabled regardless of the
> host-model's capabilities.
>
> To remedy this, deprecated f
On Tue, Jun 4, 2024 at 7:15 PM Yu-Ming Chang via wrote:
Something is strange with your `From` email address.
This seems to be a common problem with the Andes emails, do you mind
fixing this?
Alistair
>
> Both CSRRS and CSRRC always read the addressed CSR and cause any read side
> effects regar
On Thu, Jul 11, 2024 at 10:41:35AM -0400, Michael S. Tsirkin wrote:
> On Thu, Jul 11, 2024 at 03:25:12PM +0200, Igor Mammedov wrote:
> > On Mon, 8 Jul 2024 17:17:34 +0530
> > Sunil V L wrote:
> >
> > > The RISC-V BRS specification [1] requires NS16550 compatible UART to
> > > have the HID RSCV00
On 11/07/2024 23.35, Richard Henderson wrote:
On 7/11/24 12:23, Alex Bennée wrote:
Richard Henderson writes:
On 7/11/24 09:45, Richard Henderson wrote:
On 7/11/24 04:55, Thomas Huth wrote:
+ def fetch_asset(self, url, asset_hash):
+ cache_dir = os.path.expanduser("~/.cache/qemu/do
On 11/07/2024 20.49, Richard Henderson wrote:
On 7/11/24 09:45, Richard Henderson wrote:
On 7/11/24 04:55, Thomas Huth wrote:
+ def fetch_asset(self, url, asset_hash):
+ cache_dir = os.path.expanduser("~/.cache/qemu/download")
+ if not os.path.exists(cache_dir):
+ os
On 11/07/2024 18.45, Richard Henderson wrote:
On 7/11/24 04:55, Thomas Huth wrote:
+ def fetch_asset(self, url, asset_hash):
+ cache_dir = os.path.expanduser("~/.cache/qemu/download")
+ if not os.path.exists(cache_dir):
+ os.makedirs(cache_dir)
+ fname = os.pat
This work is based on the virtio-spi spec, virtio-spi driver introduced by
the following patch series:
- https://github.com/oasis-tcs/virtio-spec/tree/virtio-1.4/device-types/spi
- https://lwn.net/Articles/966715/
To test with rust-vmm vhost-user-spi daemon, start the vhost-daemon firstly:
vho
From: lxx <1733205...@qq.com>
This patch adds support for the Zilsd and Zcmlsd extension,
which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0
Co-developed-by: SUN Dongya
Co-developed-by: LIU Xu
Co-developed-by: ZHAO Fujin
---
target/riscv/cpu.c
In this version of the patch:
1. Adjusted the code formatting issue
2. Optimize the processing of all instructions
lxx (1):
target/riscv: Add Zilsd and Zcmlsd extension support
target/riscv/cpu.c | 4 +
target/riscv/cpu_cfg.h | 2 +
target/riscv/in
From: thomas
Patch 06b12970174 ("virtio-net: fix network stall under load")
added double-check to test whether the available buffer size
can satisfy the request or not, in case the guest has added
some buffers to the avail ring simultaneously after the first
check. It will be lucky if the availab
This commit introduces two helper functions
that facilitate the conversion between the
reservation types used in the NVME protocol
and those used in the block layer.
Reviewed-by: Klaus Jensen
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Changqi Lu
Signed-off-by: zhenwei pi
---
hw/nvme/nvme.h |
Hi,
Patch v9 has been modified, thanks to Stefan for the code review.
v8->v9:
- Fix double-free and remove persistent reservation operations at
nvme_is_write().
v7->v8:
- Fix num_keys may be less than 0 at scsi_pr_read_keys_complete().
- Fix buf memory leak at iscsi driver.
v6->v7:
- Add bufer
This commit introduces two helper functions
that facilitate the conversion between the
persistent reservation types used in the SCSI
protocol and those used in the block layer.
Signed-off-by: Changqi Lu
Signed-off-by: zhenwei pi
Reviewed-by: Stefan Hajnoczi
---
include/scsi/utils.h | 8 +
Add persistent reservation in/out operations in the
SCSI device layer. By introducing the persistent
reservation in/out api, this enables the SCSI device
to perform reservation-related tasks, including querying
keys, querying reservation status, registering reservation
keys, initiating and releasin
Add persistent reservation in/out operations for iscsi driver.
The following methods are implemented: bdrv_co_pr_read_keys,
bdrv_co_pr_read_reservation, bdrv_co_pr_register, bdrv_co_pr_reserve,
bdrv_co_pr_release, bdrv_co_pr_clear and bdrv_co_pr_preempt.
Signed-off-by: Changqi Lu
Signed-off-by: z
This commit enables ONCS to support the reservation
function at the controller level. Also enables rescap
function in the namespace by detecting the supported reservation
function in the backend driver.
Reviewed-by: Klaus Jensen
Signed-off-by: Changqi Lu
Signed-off-by: zhenwei pi
Reviewed-by: S
Add reservation acquire, reservation register,
reservation release and reservation report commands
in the nvme device layer.
By introducing these commands, this enables the nvme
device to perform reservation-related tasks, including
querying keys, querying reservation status, registering
reservati
Add constants for the NVMe persistent command protocol.
The constants include the reservation command opcode and
reservation type values defined in section 7 of the NVMe
2.0 specification.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Changqi Lu
Signed-off-by: zhenwei pi
---
include/block/nvme.h
Add constants for the persistent reservation in/out protocol
in the scsi/constant module. The constants include the persistent
reservation command, type, and scope values defined in sections
6.13 and 6.14 of the SCSI Primary Commands-4 (SPC-4) specification.
Signed-off-by: Changqi Lu
Signed-off-b
Add persistent reservation in/out operations for raw driver.
The following methods are implemented: bdrv_co_pr_read_keys,
bdrv_co_pr_read_reservation, bdrv_co_pr_register, bdrv_co_pr_reserve,
bdrv_co_pr_release, bdrv_co_pr_clear and bdrv_co_pr_preempt.
Signed-off-by: Changqi Lu
Signed-off-by: zhe
Add persistent reservation in/out operations
at the block level. The following operations
are included:
- read_keys:retrieves the list of registered keys.
- read_reservation: retrieves the current reservation status.
- register: registers a new reservation key.
- reserve:
On Thu, Jul 11, 2024 at 7:56 PM Alyssa Ross wrote:
>
> Adding David Stevens, who implemented SHMEM_MAP and SHMEM_UNMAP in
> crosvm a couple of years ago.
>
> David, I'd be particularly interested for your thoughts on the MEM_READ
> and MEM_WRITE commands, since as far as I know crosvm doesn't impl
On Wed, Jun 12, 2024 at 6:18 PM Jim Shu wrote:
>
> * Add 'wg=on' option to enable RISC-V WorldGuard
> * Add wgChecker to protect several resources:
> DRAM, FLASH, UART.
>
> Signed-off-by: Jim Shu
> ---
> docs/system/riscv/virt.rst | 10 +++
> hw/riscv/Kconfig | 1 +
> hw/riscv/vir
On Wed, Jul 10, 2024 at 5:05 PM Yong Huang wrote:
>
>
>
> On Wed, Jul 10, 2024 at 3:36 PM Jason Wang wrote:
>>
>> On Wed, Jul 10, 2024 at 2:26 PM Yong Huang wrote:
>> >
>> >
>> >
>> > On Wed, Jul 10, 2024 at 11:44 AM Jason Wang wrote:
>> >>
>> >> On Tue, Jul 9, 2024 at 10:56 AM Yong Huang wrot
From: Jiaxun Yang
I would like to be informed on changes made to the LoongArch virt machine.
I'm fairly familiar with Loongson-3 series platform hardware and doing
firmwre (U-Boot) development as hobbyist on LoongArch virt platform,
so I believe I can give positive review input to changes on tha
From: Dmitry Frolov
memcpy() is trying to READ 512 bytes from memory,
pointed by info->kernel_cmdline,
which was (presumable) allocated by g_strdup("");
Found with ASAN, making check with enabled sanitizers.
Signed-off-by: Dmitry Frolov
Reviewed-by: Song Gao
Message-Id: <20240628123910.577740-
From: Bibo Mao
There is abuse usage about local variable gap. Remove
duplicated assignment and solve Coverity reported error.
Resolves: Coverity CID 1546441
Fixes: 3cc451cbce ("hw/loongarch: Refine fwcfg memory map")
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20240612033637.167
After cpu_reset, DATF in CSR_CRMD is 0, DATM is 0.
See the manual[1] 6.4.
[1]:
https://github.com/loongson/LoongArch-Documentation/releases/download/2023.04.20/LoongArch-Vol1-v1.10-EN.pdf
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240705021839.1004374-2-gaos...@loongson.cn>
We set the value of register CSR_PRCFG3, but left out CSR_PRCFG1
and CSR_PRCFG2. Set CSR_PRCFG1 and CSR_PRCFG2 according to the
default values of the physical machine.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240705021839.1004374-1-gaos...@loongson.cn>
---
target/loongarch/c
From: Xianglai Li
Add devices that support tpm by default,
Fixed incomplete tpm acpi table information.
Signed-off-by: Xianglai Li
Reviewed-by: Song Gao
Message-Id: <20240624032300.999157-1-lixiang...@loongson.cn>
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/acpi
The following changes since commit 23901b2b721c0576007ab7580da8aa855d6042a9:
Merge tag 'pull-target-arm-20240711' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-11
12:00:00 -0700)
are available in the Git repository at:
https://gitlab.com/gaosong/qem
From: Bibo Mao
With KVM virtualization, debug exception is injected to guest kernel
rather than host for normal break intruction. Here hypercall
instruction with special code is used for sw breakpoint usage,
and detailed instruction comes from kvm kernel with user API
KVM_REG_LOONGARCH_DEBUG_INST
From: Feiyang Chen
Since srai.w is a valid instruction on la32, remove the avail_64 check
and simplify trans_srai_w().
Fixes: c0c0461e3a06 ("target/loongarch: Add avail_64 to check la64-only
instructions")
Reviewed-by: Richard Henderson
Signed-off-by: Feiyang Chen
Message-Id: <20240628033357.
On Wed, Jun 12, 2024 at 6:17 PM Jim Shu wrote:
>
> Add hard-coded state of WG extension. 'mwid' is the M-mode WID of CPU.
> 'mwidlist' is the list of allowed WID value of 'mlwid' CSR.
>
> These CPU states can be set by CPU option, or can be set by machine code
> via newly added APIs. If we want di
On Wed, Jun 12, 2024 at 6:17 PM Jim Shu wrote:
>
> We define CPU options for WG CSR support in RISC-V CPUs which
> can be set by machine/device emulation. The RISC-V CSR emulation
> will also check this feature for emulating WG CSRs.
>
> Signed-off-by: Jim Shu
> ---
> target/riscv/cpu.c
On Wed, Jun 12, 2024 at 6:18 PM Jim Shu wrote:
>
> Add a device for RISCV WG global config, which contains the number of
> worlds, reset value, and trusted WID ... etc.
>
> This global config is used by both CPU WG extension and wgChecker devices.
>
> Signed-off-by: Jim Shu
> ---
> hw/misc/Kconf
On Wed, Jun 12, 2024 at 6:15 PM Jim Shu wrote:
>
> RISC-V WorldGuard will add 5-bit world_id (WID) to the each memory
> transaction on the bus. The wgChecker in front of RAM or peripherals
> MMIO could do the access control based on the WID. It is similar to ARM
> TrustZone NS bit, but the WID is
700)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240711
for you to fetch changes up to 78341408e705e1b8dc92eaae2071ae0023d586b0:
target/loongarch: Fix cpu_reset set wrong CSR_CRMD (2024-07-11
15:5
On Wed, Jul 10, 2024 at 12:27 PM LIU Zhiwei
wrote:
>
> From: 甲一
>
> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> qemu-system-riscv64 can directly boot a RV32 Linux.
>
> This patch set has been tested with 6.9.0 Linux Image.
> And add an avocado test in tests/avocado.
>
> #
On 7/8/24 12:15, Alex Bennée wrote:
Pierrick Bouvier writes:
Add an explicit test to check expected memory values are read/written.
For sizes 8, 16, 32, 64 and 128, we generate a load/store operation.
For size 8 -> 64, we generate an atomic __sync_val_compare_and_swap too.
For 128bits memory a
On 7/7/24 11:25, Richard Henderson wrote:
On 7/6/24 12:13, Pierrick Bouvier wrote:
+++ b/tests/tcg/x86_64/test-plugin-mem-access.c
@@ -0,0 +1,89 @@
+#include
+#include
All new files should have license boilerplate and description.
You can use spdx to limit to just a couple of lines.
Added
On 7/8/24 09:06, Alex Bennée wrote:
Pierrick Bouvier writes:
A specific plugin test can now read and check a plugin output, to ensure
it contains expected values.
Tested-by: Xingtao Yao
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 7 +
On 7/8/24 04:00, Alex Bennée wrote:
Pierrick Bouvier writes:
Only multiarch tests are run with plugins, and we want to be able to run
per-arch test with plugins too.
Tested-by: Xingtao Yao
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 3 ++
On Thu, Jul 11, 2024 at 02:52:35PM -0700, Yichen Wang wrote:
> * Performance:
>
> We use two Intel 4th generation Xeon servers for testing.
>
> Architecture:x86_64
> CPU(s): 192
> Thread(s) per core: 2
> Core(s) per socket: 48
> Socket(s): 2
> NUMA node(s):
Currently, if a counter monitoring cycle/instret is stopped via
mcountinhibit we just update the state while the value is saved
during the next read. This is not accurate as the read may happen
many cycles after the counter is stopped. Ideally, the read should
return the value saved when the counte
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one requires Sscofpmf
to be enabled.
The cycle/instr
From: Kaiwen Xue
QEMU only calculates dummy cycles and instructions, so there is no
actual means to stop the icount in QEMU. Hence this patch merely adds
the functionality of accessing the cfg registers, and cause no actual
effects on the counting of cycle and instret counters.
Signed-off-by: At
From: Rajnesh Kanwal
Currently we start timer counter from write_mhpmcounter path only
without checking for mcountinhibit bit. This changes adds mcountinhibit
check and also programs the counter from write_mcountinhibit as well.
When a counter is stopped using mcountinhibit we simply update
the
scounteren/hcountern are also WARL registers similar to mcountern.
Only set the bits for the available counters during the write to
preserve the WARL behavior.
Signed-off-by: Atish Patra
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 12 ++--
From: Rajnesh Kanwal
In case of programmable counters configured to count inst/cycles
we often end-up with counter not incrementing at all from kernel's
perspective.
For example:
- Kernel configures hpm3 to count instructions and sets hpmcounter
to -1 and all modes except U mode are inhibi
mhpmeventhX CSRs are available for RV32. The predicate function
should check that first before checking sscofpmf extension.
Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support")
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
tar
From: Kaiwen Xue
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 6 ++
target/riscv/cpu_bits.h | 29 +
Create a new config for Smcntrpmf extension so that it can be enabled/
disabled from the qemu commandline.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 63f553c92b00..ef50130a91e7 100644
--- a/t
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 1 +
target/riscv/cpu_cfg.h | 1 +
2 files changed, 2 insertions(
This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. It is based on Kevin's earlier work but improves
it by actually implement privilege mode filtering by tracking the privilege
mode switches. This enables the privilege mode filtering for m
Currently, the INH fields are set in mhpmevent uncoditionally
without checking if a particular priv mode is supported or not.
Suggested-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 29 +
1 file changed, 25 insertions(+), 4 deletions(-)
di
From: Rajnesh Kanwal
Combining riscv_cpu_set_virt_enabled() and riscv_cpu_set_mode()
functions. This is to make complete mode change information
available through a single function.
This allows to easily differentiate between HS->VS, VS->HS
and VS->VS transitions when executing state update code
The timer is setup function is invoked in both hpmcounter
write and mcountinhibit write path. If the OF bit set, the
LCOFI interrupt is disabled. There is no benefitting in
setting up the qemu timer until LCOFI is cleared to indicate
that interrupts can be fired again.
Reviewed-by: Daniel Henrique
On Thu, Jul 11, 2024 at 06:12:44PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Thu, Jul 11, 2024 at 04:37:34PM -0300, Fabiano Rosas wrote:
> >
> > [...]
> >
> >> We also don't flush the iov at once, so f->buf seems redundant to
> >> me. But of course, if we touch any of that we must e
From: Hao Xiang
* Add test case to start and complete multifd live migration with DSA
offloading enabled.
* Add test case to start and cancel multifd live migration with DSA
offloading enabled.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
tests/qtest/mig
From: Hao Xiang
* Test DSA start and stop path.
* Test DSA configure and cleanup path.
* Test DSA task submission and completion path.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
tests/unit/meson.build | 6 +
tests/unit/test-dsa.c | 503 +
From: Hao Xiang
During live migration, if the latency between sender and receiver is
high and bandwidth is also high (a long and fat pipe), using a bigger
packet size can help reduce migration total time. The current multifd
packet size is 128 * 4kb. In addition, Intel DSA offloading performs
bet
From: Hao Xiang
Multifd sender path gets an array of pages queued by the migration
thread. It performs zero page checking on every page in the array.
The pages are classfied as either a zero page or a normal page. This
change uses Intel DSA to offload the zero page checking from CPU to
the DSA ac
On Thu, Jul 11, 2024 at 2:53 PM Yichen Wang wrote:
> diff --git a/migration/options.c b/migration/options.c
> index 645f55003d..f839493016 100644
> --- a/migration/options.c
> +++ b/migration/options.c
> @@ -29,6 +29,7 @@
> #include "ram.h"
> #include "options.h"
> #include "sysemu/kvm.h"
> +#
From: Hao Xiang
Create DSA task with operation code DSA_OPCODE_COMPVAL.
Here we create two types of DSA tasks, a single DSA task and
a batch DSA task. Batch DSA task reduces task submission overhead
and hence should be the default option. However, due to the way DSA
hardware works, a DSA batch ta
From: Hao Xiang
* Use a safe thread queue for DSA task enqueue/dequeue.
* Implement DSA task submission.
* Implement DSA batch task submission.
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
include/qemu/dsa.h | 46 ++
util/dsa.c | 222 +++
From: Hao Xiang
* DSA device open and close.
* DSA group contains multiple DSA devices.
* DSA group configure/start/stop/clean.
Signed-off-by: Hao Xiang
Signed-off-by: Bryan Zhang
Signed-off-by: Yichen Wang
---
include/qemu/dsa.h | 86 +
util/dsa.c | 303
From: Hao Xiang
* Create a dedicated thread for DSA task completion.
* DSA completion thread runs a loop and poll for completed tasks.
* Start and stop DSA completion thread during DSA device start stop.
User space application can directly submit task to Intel DSA
accelerator by writing to DSA's
v5
* Rebase on top of 39a032cea23e522268519d89bb738974bc43b6f6.
* Rename struct definitions with typedef and CamelCase names;
* Add build and runtime checks about DSA accelerator;
* Address all comments from v4 reviews about typos, licenses, comments,
error reporting, etc.
v4
* Rebase on top of 85
From: Hao Xiang
* Add a DSA task completion callback.
* DSA completion thread will call the tasks's completion callback
on every task/batch task completion.
* DSA submission path to wait for completion.
* Implement CPU fallback if DSA is not able to complete the task.
Signed-off-by: Hao Xiang
S
Signed-off-by: Yichen Wang
---
scripts/update-linux-headers.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index c34ac6454e..5aba95d9cb 100755
--- a/scripts/update-linux-headers.sh
+++ b/scripts/update-linux
From: Hao Xiang
Intel DSA offloading is an optional feature that turns on if
proper hardware and software stack is available. To turn on
DSA offloading in multifd live migration:
dsa-accel-path="[dsa_dev_path1] [dsa_dev_path2] ... [dsa_dev_pathX]"
This feature is turned off by default.
Signed-
From: Hao Xiang
Enable instruction set enqcmd in build.
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
meson.build | 14 ++
meson_options.txt | 2 ++
scripts/meson-buildoptions.sh | 3 +++
3 files changed, 19 insertions(+)
diff --git a/mes
From: Hao Xiang
1. Refactor multifd_send_thread function.
2. Introduce the batch task structure in MultiFDSendParams.
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
include/qemu/dsa.h | 41 ---
migration/multifd.c | 4 +
migration/multifd.h | 3 +
util/dsa.c | 270
On 7/11/24 12:23, Alex Bennée wrote:
Richard Henderson writes:
On 7/11/24 09:45, Richard Henderson wrote:
On 7/11/24 04:55, Thomas Huth wrote:
+ def fetch_asset(self, url, asset_hash):
+ cache_dir = os.path.expanduser("~/.cache/qemu/download")
+ if not os.path.exists(cache_d
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240711
for you to fetch changes up to 7f49089158a4db644fcbadfa90cd3d30a4868735:
target/arm: Convert PMULL to decodetree (2024-07-11 11:41:34 +0100)
target
** Changed in: qemu
Status: Unknown => New
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/2072564
Title:
qemu-aarch64-static segfaults running ldconfig.real (amd64 host)
Status in QEMU:
Ne
On 7/9/24 06:00, Daniel P. Berrangé wrote:
On Tue, Jul 09, 2024 at 02:28:38PM +0200, Paolo Bonzini wrote:
On Tue, Jul 9, 2024 at 2:09 PM Peter Maydell wrote:
* what is the actual baseline requirement? We definitely want
to support "using rustup on an older system" (should be no
probl
Hello Cedric,
This patch will be split into 5 patches to ease the review. I also
acknowledge most of your other comments.
Can you elaborate on the gic_get_current_cpu() comment? Did you want me
to use that method name to get a the current CPU? Also, is this
something that you think needs
Peter Xu writes:
> On Thu, Jul 11, 2024 at 04:37:34PM -0300, Fabiano Rosas wrote:
>
> [...]
>
>> We also don't flush the iov at once, so f->buf seems redundant to
>> me. But of course, if we touch any of that we must ensure we're not
>> dropping any major optimization.
>
> Yes some tests over tha
On 11.07.24 22:32, Collin Walling wrote:
It is beneficial to provide an interface to retrieve *all* deprecated
features in one go. Management applications will need this information
to determine which features need to be disabled regardless of the
host-model's capabilities.
To remedy this, depre
It is beneficial to provide an interface to retrieve *all* deprecated
features in one go. Management applications will need this information
to determine which features need to be disabled regardless of the
host-model's capabilities.
To remedy this, deprecated features are only filtered during a s
On Thu, Jul 11, 2024 at 04:37:34PM -0300, Fabiano Rosas wrote:
[...]
> We also don't flush the iov at once, so f->buf seems redundant to
> me. But of course, if we touch any of that we must ensure we're not
> dropping any major optimization.
Yes some tests over that would be more persuasive when
Peter Xu writes:
> On Thu, Jul 11, 2024 at 11:12:09AM -0300, Fabiano Rosas wrote:
>> What about the QEMUFile traffic? There's an iov in there. I have been
>> thinking of replacing some of qemu-file.c guts with calls to
>> multifd. Instead of several qemu_put_byte() we could construct an iov
>> an
On Thu, Jul 11, 2024 at 09:48:02AM -0700, Yichen Wang wrote:
> On Thu, Jul 11, 2024 at 8:45 AM Peter Xu wrote:
> >
> > On Wed, Jul 10, 2024 at 07:52:24PM -0700, Yichen Wang wrote:
> > > v5:
> > > - Rebase changes on top of 59084feb256c617063e0dbe7e64821ae8852d7cf
> > > - Add documentations about m
Richard Henderson writes:
> On 7/11/24 09:45, Richard Henderson wrote:
>> On 7/11/24 04:55, Thomas Huth wrote:
>>> + def fetch_asset(self, url, asset_hash):
>>> + cache_dir = os.path.expanduser("~/.cache/qemu/download")
>>> + if not os.path.exists(cache_dir):
>>> + os.
On 11/07/2024 10:04, Minwoo Im wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On 24-07-10 05:17:42, CLEMENT MATHIEU--DRIF wrote:
>>
>> On 09/07/2024 23:17, Minwoo Im wrote:
>>> Cautio
On 7/11/24 02:17, Stefan Hajnoczi wrote:
The following changes since commit 59084feb256c617063e0dbe7e64821ae8852d7cf:
Merge tag 'pull-aspeed-20240709' ofhttps://github.com/legoater/qemu into
staging (2024-07-09 07:13:55 -0700)
are available in the Git repository at:
https://gitlab.com/
On 7/10/24 11:00, David Hildenbrand wrote:
The following changes since commit 59084feb256c617063e0dbe7e64821ae8852d7cf:
Merge tag 'pull-aspeed-20240709' ofhttps://github.com/legoater/qemu into
staging (2024-07-09 07:13:55 -0700)
are available in the Git repository at:
https://github.co
On 7/11/24 09:45, Richard Henderson wrote:
On 7/11/24 04:55, Thomas Huth wrote:
+ def fetch_asset(self, url, asset_hash):
+ cache_dir = os.path.expanduser("~/.cache/qemu/download")
+ if not os.path.exists(cache_dir):
+ os.makedirs(cache_dir)
+ fname = os.path.j
On 6/18/24 04:17, Clément Léger wrote:
Since commit 03e471c41d8b ("qemu_init: increase NOFILE soft limit on
POSIX"), the maximum number of file descriptors that can be opened are
raised to nofile.rlim_max. On recent debian distro, this yield a maximum
of 1073741816 file descriptors. Now, when for
From: Klaus Jensen
Hi,
The following changes since commit 59084feb256c617063e0dbe7e64821ae8852d7cf:
Merge tag 'pull-aspeed-20240709' of https://github.com/legoater/qemu into
staging (2024-07-09 07:13:55 -0700)
are available in the Git repository at:
https://gitlab.com/birkelund/qemu.git
From: Minwoo Im
To prevent further bumping up the number of maximum VF te support, this
patch allocates a dynamic array (NvmeCtrl *)->sec_ctrl_list based on
number of VF supported by sriov_max_vfs property.
Reviewed-by: Klaus Jensen
Signed-off-by: Minwoo Im
Signed-off-by: Klaus Jensen
---
hw
From: Minwoo Im
Secondary controller list for virtualization has been managed by
Identify Secondary Controller List data structure with NvmeSecCtrlList
where up to 127 secondary controller entries can be managed. The
problem hasn't arisen so far because NVME_MAX_VFS has been 127.
This patch sep
From: Minwoo Im
VI and VQ resources cover queue resources in each VFs in SR-IOV.
Current maximum I/O queue pair size is 0x, we can expand them to
cover the full number of I/O queue pairs.
This patch also fixed Identify Secondary Controller List overflow due to
expand of number of secondary c
From: Minwoo Im
PF initializes SR-IOV VF BAR0 region in nvme_init_sriov() with bar_size
calcaulted by Primary Controller Capability such as VQFRSM and VIFRSM
rather than `max_ioqpairs` and `msix_qsize` which is for PF only.
In this case, the bar size reported in nvme_init_sriov() by PF and
nvme_
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