On 7/18/24 18:18, Cédric Le Goater wrote:
On 7/18/24 08:49, Jamin Lin wrote:
v1:
1. support ADC for AST2700
2. support I2C for AST2700
Jamin Lin (15):
aspeed/adc: Add AST2700 support
aspeed/soc: support ADC for AST2700
hw/i2c/aspeed: support to set the different memory size
hw/i2c/a
On 7/18/24 15:47, Joao Martins wrote:
On 17/07/2024 10:31, Joao Martins wrote:
On 17/07/2024 10:28, Cédric Le Goater wrote:
@@ -224,6 +300,11 @@ static void
iommufd_cdev_detach_container(VFIODevice *vbasedev,
{
Error *err = NULL;
+ if (vbasedev->hwpt) {
+ iommufd_cdev_aut
Yichen Wang writes:
> From: Bryan Zhang
>
> Adds support for 'qatzip' as an option for the multifd compression
> method parameter, and implements using QAT for 'qatzip' compression and
> decompression.
>
> Signed-off-by: Bryan Zhang
> Signed-off-by: Hao Xiang
> Signed-off-by: Yichen Wang
QAP
The crash was reported in MAC OS and NixOS, here is the link for this bug
https://gitlab.com/qemu-project/qemu/-/issues/2334
https://gitlab.com/qemu-project/qemu/-/issues/2321
In this bug, they are using the virtio_input device. The guest notifier was
not supported for this device, The function vi
On 19/07/2024 05:39, Duan, Zhenzhong wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
>> -Original Message-
>> From: Duan, Zhenzhong]
>> Subject: RE: [PATCH v1 03/17] intel_iommu:
On 19/07/2024 04:53, Duan, Zhenzhong wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
>> -Original Message-
>> From: CLEMENT MATHIEU--DRIF
>> Subject: Re: [PATCH v1 16/17] intel_
On 19/07/2024 04:47, Duan, Zhenzhong wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
>> -Original Message-
>> From: CLEMENT MATHIEU--DRIF
>> Subject: Re: [PATCH v1 03/17] intel_
On Tue, Jul 9, 2024 at 3:37 AM Daniel Henrique Barboza
wrote:
>
> From: Tomasz Jeznach
>
> Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
> This will add support for ATS translation requests in Fault/Event
> queues, Page-request queue and IOATC invalidations.
>
> Signed-of
>-Original Message-
>From: Duan, Zhenzhong]
>Subject: RE: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for
>scalable modern mode
>
>
>
>>-Original Message-
>>From: Liu, Yi L
>>Subject: Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for
>>scalable modern
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for
>scalable modern mode
>
>On 2024/7/19 10:47, Duan, Zhenzhong wrote:
>>
>>
>>> -Original Message-
>>> From: CLEMENT MATHIEU--DRIF
>>> Subject: Re: [PATCH v1 03/17] inte
On 2024/7/19 10:47, Duan, Zhenzhong wrote:
-Original Message-
From: CLEMENT MATHIEU--DRIF
Subject: Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for
scalable modern mode
On 18/07/2024 10:16, Zhenzhong Duan wrote:
Caution: External email. Do not open attachments or c
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v1 16/17] intel_iommu: Modify x-scalable-mode to be
>string option
>
>
>
>On 18/07/2024 10:16, Zhenzhong Duan wrote:
>> Caution: External email. Do not open attachments or click links, unless this
>email comes from a k
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for
>scalable modern mode
>
>
>
>On 18/07/2024 10:16, Zhenzhong Duan wrote:
>> Caution: External email. Do not open attachments or click links, unless this
>email comes
GDB already support LoongArch vector extension[1], QEMU gdb adds
LoongArch vector registers support, so that users can use 'info all-registers'
to get all vector registers values.
[1]:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1e9569f383a3d5a88ee07d0c2401bd95613c222e
Signed-o
Remove extioi INT_encode encode mode, because we don't emulate it.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240718083254.748179-1-gaos...@loongson.cn>
---
include/hw/intc/loongarch_extioi.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/intc/loongarch_extioi.h
From: Xianglai Li
loongarch added a common library for edk2 to
parse flash base addresses through fdt.
For compatibility with other architectures,
the flash block size in qemu is now changed to 256k.
Signed-off-by: Xianglai Li
Reviewed-by: Song Gao
Message-Id: <20240624033319.999631-1-lixiang.
The following changes since commit 23fa74974d8c96bc95cbecc0d4e2d90f984939f6:
Merge tag 'pull-target-arm-20240718' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-19
07:02:17 +1000)
are available in the Git repository at:
https://gitlab.com/gaosong/qem
>-Original Message-
>From: Joao Martins
>Subject: Re: [PATCH v4 05/12] vfio/iommufd: Introduce auto domain
>creation
>
>On 18/07/2024 08:44, Duan, Zhenzhong wrote:
>> If existing hwpt doesn't support dirty tracking.
>> Another device supporting dirty tracking attaches to that hwp
在 2024/7/18 下午10:10, Markus Armbruster 写道:
Fixes: a8a506c39070 (hw/loongarch: Add support loongson3 virt machine type.)
Signed-off-by: Markus Armbruster
---
qapi/machine.json | 2 ++
1 file changed, 2 insertions(+)
diff --git a/qapi/machine.json b/qapi/machine.json
index f9ea6b3e97..fcfd249e
Reviewed-by: Bibo Mao
On 2024/7/18 下午4:32, Song Gao wrote:
Remove extioi INT_encode encode mode, because we don't emulate it.
Signed-off-by: Song Gao
---
include/hw/intc/loongarch_extioi.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/intc/loongarch_extioi.h
b/include/hw/i
When injecting a new poisoned region through qmp_cxl_inject_poison(),
the newly injected region should not overlap with existing poisoned
regions.
The current validation method does not consider the following
overlapping region:
+---+---+---+
| a | b(a) | a |
+---+---+---+
(a is a newly
nce commit d74ec4d7dda6322bcc51d1b13ccbd993d3574795:
Merge tag 'pull-trivial-patches' ofhttps://gitlab.com/mjt0k/qemu into
staging (2024-07-18 10:07:23 +1000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-202407
Hi Cedric,
> Subject: Re: [PATCH v1 03/15] hw/i2c/aspeed: support to set the different
> memory size
>
> On 7/18/24 11:42, Jamin Lin wrote:
> > Hi Cedric,
> >
> >> Subject: Re: [PATCH v1 03/15] hw/i2c/aspeed: support to set the
> >> different memory size
> >>
> >> On 7/18/24 08:49, Jamin Lin wrote
Avoid a race condition with munmap in another thread.
For access_memset and access_memmove, manage the value
within the helper. For uses of access_{get,set}_byte,
manage the value across the for loops.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 43 +
Mark the reserve_addr check unlikely. Use tlb_vaddr_to_host
instead of probe_write, relying on the memset itself to test
for page writability. Use set/clear_helper_retaddr so that
we can properly unwind on segfault.
With this, a trivial loop around guest memset will spend
nearly 50% of runtime w
Use of these in helpers goes hand-in-hand with tlb_vaddr_to_host
and other probing functions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
accel/tcg/user-retaddr.h | 28
include/exec/cpu_ldst.h | 34 ++
accel/tcg/c
From: BALATON Zoltan
Instead of passing a bool and select a value within dcbz_common() let
the callers pass in the right value to avoid this conditional
statement. On PPC dcbz is often used to zero memory and some code uses
it a lot. This change improves the run time of a test case that copies
me
Use these in helper_dc_dva and the FEAT_MOPS routines to
avoid a race condition with munmap in another thread.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-a64.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/a
Avoid a race condition with munmap in another thread.
Use around blocks that exclusively use "host_fn".
Keep the blocks as small as possible, but without setting
and clearing for every operation on one page.
Signed-off-by: Richard Henderson
---
target/arm/tcg/sme_helper.c | 16 ++
ta
The 970 logic does not apply to dcbzep, which is an e500 insn.
Reviewed-by: Nicholas Piggin
Reviewed-by: BALATON Zoltan
Signed-off-by: Richard Henderson
---
target/ppc/mem_helper.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/ppc/m
Merge the two and pass the mmu_idx directly from translation.
Swap the argument order in dcbz_common to avoid extra swaps.
Reviewed-by: Nicholas Piggin
Signed-off-by: Richard Henderson
---
target/ppc/helper.h | 3 +--
target/ppc/mem_helper.c | 14 --
target/ppc/translate.c |
The current pairing of tlb_vaddr_to_host with extra is either
inefficient (user-only, with page_check_range) or incorrect
(system, with probe_pages).
For proper non-fault behaviour, use probe_access_flags with
its nonfault parameter set to true.
Acked-by: Alistair Francis
Signed-off-by: Richard
Eliminate the ifdef by using a predicate that is
always true with CONFIG_USER_ONLY.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x
We can determine at translation time whether the insn is or
is not dbczl. We must retain a runtime check against the
HID5 register, but we can move that to a separate function
that never affects other ppc models.
Reviewed-by: Nicholas Piggin
Reviewed-by: BALATON Zoltan
Signed-off-by: Richard He
Invert the conditional, indent the block, and use the macro
that expands to true for user-only.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 54 +--
1 file changed, 26 insertions(+), 28 deletions(-)
diff --git a/target/s390x/tcg/mem_helper
Changes for v3:
* Fix patch 3 (sve) vs goto do_fault (pmm)
* Fix patch 12 (rvv) vs watchpoints and goto ProbeSuccess (max chou).
* Apply r-b.
r~
BALATON Zoltan (1):
target/ppc/mem_helper.c: Remove a conditional from dcbz_common()
Richard Henderson (11):
accel/tcg: Move {set,clear}_help
On 7/12/24 10:14, Pierrick Bouvier wrote:
On 7/12/24 07:51, Alex Bennée wrote:
Pierrick Bouvier writes:
On 7/8/24 12:15, Alex Bennée wrote:
Pierrick Bouvier writes:
Add an explicit test to check expected memory values are read/written.
For sizes 8, 16, 32, 64 and 128, we generate a load/s
> -Original Message-
> From: Peter Maydell
> Sent: Friday, July 19, 2024 1:12 AM
> To: Jonathan Cameron
> Cc: Yao, Xingtao/姚 幸涛 ; fan...@samsung.com;
> qemu-devel@nongnu.org
> Subject: Re: [PATCH] mem/cxl_type3: Fix overlapping region validation error
>
> On Thu, 18 Jul 2024 at 17:37,
On 7/18/24 17:41, Richard Henderson wrote:
Python 3.12 warns:
TESTgdbstub MTE support on aarch64
/home/rth/qemu/src/tests/tcg/aarch64/gdbstub/test-mte.py:21: SyntaxWarning:
invalid escape sequence '\('
PATTERN_0 = "Memory tags for address 0x[0-9a-f]+ match \(0x[0-9a-f]+\)."
Double up
>
>
> As mentioned by Peter, we can use ranges_overlap() to improve the
> code readability. Other than that, looks good t me.
>
> btw, not sure only me or not, but the message does not display
> correctly in mutt, seems not a plain text message, but looks fine in
> outlook.
I am not sure as well
Python 3.12 warns:
TESTgdbstub MTE support on aarch64
/home/rth/qemu/src/tests/tcg/aarch64/gdbstub/test-mte.py:21: SyntaxWarning:
invalid escape sequence '\('
PATTERN_0 = "Memory tags for address 0x[0-9a-f]+ match \(0x[0-9a-f]+\)."
Double up the \ to pass one through to the pattern.
Sig
On Jul 19 2024, at 8:20 am, Amjad Alsharafi wrote:
> On Thu, Jul 18, 2024 at 05:20:36PM +0200, Kevin Wolf wrote:
>> Am 12.06.2024 um 14:43 hat Amjad Alsharafi geschrieben:
>> > When reading with `read_cluster` we get the `mapping` with
>> > `find_mapping_for_cluster` and then we call `open_fil
On Thu, Jul 18, 2024 at 05:20:36PM +0200, Kevin Wolf wrote:
> Am 12.06.2024 um 14:43 hat Amjad Alsharafi geschrieben:
> > When reading with `read_cluster` we get the `mapping` with
> > `find_mapping_for_cluster` and then we call `open_file` for this
> > mapping.
> > The issue appear when its the sa
This patch's main focus is to enable creating VMs with > 63GB
of RAM on Apple Silicon machines by using some new HVF APIs. In
pursuit of this a couple of things related to how we handle the
physical address range we expose to guests were altered:
The default IPA size on all Apple Silicon machines
On 7/18/24 23:32, Philippe Mathieu-Daudé wrote:
Since v4:
- Fix build failure due to rebase (Song)
- Loongarch -> LoongArch (Song)
- Added Song's tags
Since v3:
- Use DEFINE_TYPES() macro (unreviewed patch #1)
- Update MAINTAINERS
- Added Bibo's tags
Ho hum, I didn't notice v5 when I just revi
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
hw/intc/loongson_ipi.c | 9 -
1 file changed, 9 deletions(-)
Reviewed-by: Richard Henderson
r~
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
Loongarch IPI inherits from class LoongsonIPICommonClass, and it
only contains Loongarch 3A5000 virt machine specific interfaces,
rather than mix different machine implementations together.
Signed-off-by: Bibo Mao
[PMD: Rebased]
Co-
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
Now than LoongArch target can use the TYPE_LOONGARCH_IPI
model, restrict TYPE_LOONGSON_IPI to MIPS.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
Move the common code from loongson_ipi.c to loongson_ipi_common.c,
call parent_realize() instead of loongson_ipi_common_realize() in
loongson_ipi_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit de
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
In order to access loongson_ipi_core_read/write helpers
from loongson_ipi_common.c in the next commit, make their
prototype declaration public.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
Allow Loongson IPI implementations to have their own cpu_by_arch_id()
handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mat
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
Allow Loongson IPI implementations to have their own get_iocsr_as()
handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathi
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
In order to get LoongsonIPICommonClass in send_ipi_data()
in the next commit, propagate LoongsonIPICommonState.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
Move the IPICore structure and corresponding common fields
of LoongsonIPICommonState to "hw/intc/loongson_ipi_common.h".
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
It is easier to manage one array of MMIO MR rather
than one per vCPU.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daud
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Re
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loong
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-of
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_finalize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-o
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
We'll have to add LoongsonIPIClass in few commits,
so rename LoongsonIPI as LoongsonIPIState for clarity.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
On 7/18/24 18:38, Philippe Mathieu-Daudé wrote:
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 21 +
Peter Xu writes:
> On Thu, Jul 18, 2024 at 06:27:32PM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Thu, Jul 18, 2024 at 04:39:00PM -0300, Fabiano Rosas wrote:
>> >> v2 is ready, but unfortunately this approach doesn't work. When client A
>> >> takes the payload, it fills it with i
On Thu, Jul 18, 2024 at 06:27:32PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Thu, Jul 18, 2024 at 04:39:00PM -0300, Fabiano Rosas wrote:
> >> v2 is ready, but unfortunately this approach doesn't work. When client A
> >> takes the payload, it fills it with it's data, which may includ
Peter Xu writes:
> On Thu, Jul 18, 2024 at 04:39:00PM -0300, Fabiano Rosas wrote:
>> v2 is ready, but unfortunately this approach doesn't work. When client A
>> takes the payload, it fills it with it's data, which may include
>> allocating memory. MultiFDPages_t does that for the offset. This mea
On Thu, Jul 18, 2024 at 04:39:00PM -0300, Fabiano Rosas wrote:
> v2 is ready, but unfortunately this approach doesn't work. When client A
> takes the payload, it fills it with it's data, which may include
> allocating memory. MultiFDPages_t does that for the offset. This means
> we need a round of
On 7/16/2024 9:10 AM, Zhao Liu wrote:
> kvm_install_msr_filters() uses KVM_MSR_FILTER_MAX_RANGES as the bound
> when traversing msr_handlers[], while other places still compute the
> size by ARRAY_SIZE(msr_handlers).
>
> In fact, msr_handlers[] is an array with the fixed size
> KVM_MSR_FILTER_M
On 7/16/2024 9:10 AM, Zhao Liu wrote:
> Currently, there're following incorrect error handling cases in
> kvm_arch_init():
> * Missed to handle failure of kvm_get_supported_feature_msrs().
> * Missed to return when KVM_CAP_X86_DISABLE_EXITS enabling fails.
> * MSR filter related cases called exi
On 7/16/2024 9:10 AM, Zhao Liu wrote:
> At present, the error code of MSR filter enablement attempts to print in
> error_report().
>
> Unfortunately, this behavior doesn't work because the MSR filter-related
> functions return the boolean and current error_report() use the wrong
> return value.
On 7/16/2024 9:10 AM, Zhao Liu wrote:
> MSR_KVM_SYSTEM_TIME_NEW and MSR_KVM_WALL_CLOCK_NEW are bound to
> kvmclock2 (KVM_FEATURE_CLOCKSOURCE2).
>
> Add the save/load support for these 2 MSRs just like kvmclock MSRs.
>
> Signed-off-by: Zhao Liu
Reviewed-by: Zide Chen
> ---
> target/i386/cp
On 7/16/2024 9:10 AM, Zhao Liu wrote:
> The KVM_X86_DISABLE_EXITS_HTL typo has been fixed in commit
> 77d361b13c19 ("linux-headers: Update to kernel mainline commit
> b357bf602").
>
> Drop the related workaround.
>
> Signed-off-by: Zhao Liu
Reviewed-by: Zide Chen
> ---
> target/i386/kvm/k
On 7/16/2024 9:10 AM, Zhao Liu wrote:
> MSR_KVM_SYSTEM_TIME and MSR_KVM_WALL_CLOCK are attached with the (old)
> kvmclock feature (KVM_FEATURE_CLOCKSOURCE).
>
> So, just save/load them only when kvmclock (KVM_FEATURE_CLOCKSOURCE) is
> enabled.
>
> Signed-off-by: Zhao Liu
Reviewed-by: Zide C
On 7/16/2024 9:10 AM, Zhao Liu wrote:
> Add feature definitions for KVM_CPUID_FEATURES in CPUID (
> CPUID[4000_0001].EAX and CPUID[4000_0001].EDX), to get rid of lots of
> offset calculations.
>
> Signed-off-by: Zhao Liu
Reviewed-by: zide.c...@intel.com
> ---
> v3: Resolved a rebasing confl
On 7/16/2024 9:10 AM, Zhao Liu wrote:
> These 2 MSRs have been already defined in kvm_para.h (standard-headers/
> asm-x86/kvm_para.h).
>
> Remove QEMU local definitions to avoid duplication.
>
> Reviewed-by: Xiaoyao Li
> Signed-off-by: Zhao Liu
Reviewed-by: zide.c...@intel.com
> ---
> ta
github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240718-1
for you to fetch changes up to daff9f7f7a457f78ce455e6abf19c2a37dfe7630:
roms/opensbi: Update to v1.5 (2024-07-18 12:08:45 +1000)
RISC-V PR for 9.1
* Support the zi
On 7/18/24 17:51, Kevin Wolf wrote:
Am 16.07.2024 um 16:41 hat Andrey Drobyshev geschrieben:
From: "Denis V. Lunev"
We have observed that some clusters in the QCOW2 files are zeroed
while preallocation filter is used.
We are able to trace down the following sequence when prealloc-filter
is us
Peter Xu writes:
> On Thu, Jul 11, 2024 at 11:12:09AM -0300, Fabiano Rosas wrote:
>> What about the QEMUFile traffic? There's an iov in there. I have been
>> thinking of replacing some of qemu-file.c guts with calls to
>> multifd. Instead of several qemu_put_byte() we could construct an iov
>> an
Am 18.07.24 um 11:17 schrieb Peter Maydell:
> On Wed, 17 Jul 2024 at 21:11, Volker Rümelin wrote:
>> Fix the search function in Sphinx generated html docs when built
>> with Sphinx >= 6.0.0.
>>
>> Quote from the Sphinx blog at
>> https://blog.readthedocs.com/sphinx6-upgrade
>>
>> Sphinx 6 is out a
Am 26.06.2024 um 16:50 hat Vladimir Sementsov-Ogievskiy geschrieben:
> Actually block job is not completed without the final flush. It's
> rather unexpected to have broken target when job was successfully
> completed long ago and now we fail to flush or process just
> crashed/killed.
>
> Mirror jo
Am 09.01.2024 um 14:13 hat Vladimir Sementsov-Ogievskiy geschrieben:
> From: Leonid Kaplan
>
> BLOCK_IO_ERROR events comes from guest, so we must throttle them.
> We still want per-device throttling, so let's use device id as a key.
>
> Signed-off-by: Leonid Kaplan
> Signed-off-by: Vladimir Sem
Am 29.06.2024 um 16:25 hat Michael Tokarev geschrieben:
> Existing code was long, unclear and twisty.
>
> Signed-off-by: Michael Tokarev
> ---
> block/curl.c | 44 ++--
> 1 file changed, 18 insertions(+), 26 deletions(-)
>
> diff --git a/block/curl.c b/bl
On 7/18/24 9:39 AM, Markus Armbruster wrote:
> Collin Walling writes:
>
>> As s390 CPU models progress and deprecated properties are dropped
>> outright, it will be cumbersome for management apps to query the host
>> for a comprehensive list of deprecated properties that will need to be
>> disabl
Am 18.07.2024 um 14:36 hat Markus Armbruster geschrieben:
> BlockdevSnapshotInternal is the arguments type of command
> blockdev-snapshot-internal-sync. Its doc comment contains this note:
>
> # .. note:: In a transaction, if @name is empty or any snapshot matching
> #@name exists, th
On Thu, Jul 18, 2024 at 06:07:37PM GMT, Alexandre Ghiti wrote:
> The Svvptc extension describes a uarch that does not cache invalid TLB
> entries: that's the case for qemu so there is nothing particular to
> implement other than the introduction of this extension.
>
> Since qemu already exposes Sv
On Thu, Jul 18, 2024 at 05:07:53AM -0400, Yao Xingtao wrote:
> style="display:none
> !important;display:none;visibility:hidden;mso-hide:all;font-size:1px;color:#ff;line-height:1px;height:0px;max-height:0px;opacity:0;overflow:hidden;">
> When injecting a new poisoned region through qmp_cxl_in
The virtiofs_submounts test has been removed in commit 5da7701e2a
("virtiofsd: Remove test"), so we don't need this files anymore.
Signed-off-by: Thomas Huth
---
.../virtiofs_submounts.py.data/cleanup.sh | 46 --
.../guest-cleanup.sh | 30
.../virtiofs_sub
On Thu, Jul 18, 2024 at 3:22 AM Markus Armbruster wrote:
>
> Daniel P. Berrangé writes:
>
> > On Thu, Jul 18, 2024 at 08:15:01AM +0200, Markus Armbruster wrote:
> >> Looks like this one fell through the cracks.
> >>
> >> Octavian Purdila writes:
> >>
> >> > Add path option to the pty char backen
On 7/18/24 07:59, Alex Bennée wrote:
This is a simple control flow tracking plugin that uses the latest
inline and conditional operations to detect and track control flow
changes. It is currently an exercise at seeing how useful the changes
are.
Based-on: <20240312075428.244210-1-pierrick.bouv..
On Thu, 18 Jul 2024 at 17:37, Jonathan Cameron via
wrote:
>
> On Thu, 18 Jul 2024 05:07:53 -0400
> Yao Xingtao wrote:
>
> > When injecting a new poisoned region through qmp_cxl_inject_poison(),
> > the newly injected region should not overlap with existing poisoned
> > regions.
> >
> > The curren
On 7/16/2024 3:18 PM, Cédric Le Goater wrote:
Hello Mike,
On 7/16/24 21:56, Michael Kowal wrote:
These changes provide enhanced support of the External Interrupt
Virtualization
Engine. The changes are focused on the following areas:
- Cache Watch, Cache Flush and Sync Injection
- Virtua
On 7/18/24 02:45, Alex Bennée wrote:
Using bare printf's in plugins is perfectly acceptable but they do
rather mess up the output of "make check-tcg". Convert the printfs to
use g_string and then output with the plugin output helper which will
already be captured to .pout files by the test harnes
On Thu, 18 Jul 2024 05:07:53 -0400
Yao Xingtao wrote:
> When injecting a new poisoned region through qmp_cxl_inject_poison(),
> the newly injected region should not overlap with existing poisoned
> regions.
>
> The current validation method does not consider the following
> overlapping region:
>
On Thu, Jul 18, 2024 at 11:43:54AM -0400, Steven Sistare wrote:
> On 7/17/2024 3:24 PM, Peter Xu wrote:
> [...]
> >
> > PS to Steve: and I think I left tons of other comments in previous version
> > outside this patch too, but I don't think they're fully discussed when this
> > series was sent. I
On 7/18/24 08:49, Jamin Lin wrote:
v1:
1. support ADC for AST2700
2. support I2C for AST2700
Jamin Lin (15):
aspeed/adc: Add AST2700 support
aspeed/soc: support ADC for AST2700
hw/i2c/aspeed: support to set the different memory size
hw/i2c/aspeed: support discontinuous register memor
On 7/17/24 15:06, Cédric Le Goater wrote:
The image was built using the process described in commit c8cb19876d3e
("hw/sd/sdcard: Support boot area in emmc image") with artefacts from
the latest successful build of the IBM P10 BMC platform available on:
https://jenkins.openbmc.org/job/ci-open
On 7/17/24 08:30, Cédric Le Goater wrote:
Hello,
This series enables boot from eMMC on the rainier-bmc machine, which
is the default behavior and also on the AST2600 EVB using a machine
option to change the default.
First 6 patches adjust the machine setup and HW strapping to boot from
eMMC, th
On 7/12/24 18:36, Cédric Le Goater wrote:
Coverity reports a possible integer overflow because routine
aspeeed_smc_hclk_divisor() has a codepath returning 0, which could
lead to an integer overflow when computing variable 'hclk_shift' in
the caller aspeed_smc_dma_calibration().
The value passed
On Thu, Jul 18, 2024 at 04:58:10PM +0100, Peter Maydell wrote:
> On Thu, 30 May 2024 at 12:11, Gerd Hoffmann wrote:
> >
> > It's 2024. 4k display resolutions are a thing these days.
> > Raise width and height limits of the qemu vnc server.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.
Since qemu already exposes Svvptc behaviour, let's enable it by default
since it allows to drastically
On Thu, 30 May 2024 at 12:11, Gerd Hoffmann wrote:
>
> It's 2024. 4k display resolutions are a thing these days.
> Raise width and height limits of the qemu vnc server.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1596
> Signed-off-by: Gerd Hoffmann
> ---
> ui/vnc.h | 4 ++--
> 1
Steve,
On Sun, Jun 30, 2024 at 12:40:23PM -0700, Steve Sistare wrote:
> What?
Thanks for trying out with the cpr-transfer series. I saw that that series
missed most of the cc list here, so I'm attaching the link here:
https://lore.kernel.org/r/1719776648-435073-1-git-send-email-steven.sist...@o
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