Hi Konstantin
> Subject: Re: [PATCH v3 0/6] Support GPIO for AST2700
>
> On Fri, Sep 27, 2024 at 06:29:22AM GMT, Jamin Lin wrote:
> > > Also, your emails have an invalid "From" field set to
> > > "qemu-devel@nongnu.org" when retrieved with the b4 command.
>
> This is almost certainly done by the
Hi Thomas,
> Subject: Re: [PATCH v5 7/7] hw/gpio/aspeed: Add test case for AST2700
>
> On 27/09/2024 10.33, Jamin Lin wrote:
> > Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
> >
> > Signed-off-by: Jamin Lin
> > ---
> > tests/qtest/aspeed_gpio-test.c | 68
> ++
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v3 06/17] intel_iommu: Implement stage-1 translation
>
>On 2024/9/11 13:22, Zhenzhong Duan wrote:
>> From: Yi Liu
>>
>> This adds stage-1 page table walking to support stage-1 only
>> transltion in scalable modern mode.
>
>a typo
Hi Cedric,
> Subject: Re: [PATCH v5 6/7] aspeed/soc: Support GPIO for AST2700 and correct
> irq 130
>
> Hello Jamin,
>
> On 9/27/24 10:33, Jamin Lin wrote:
> > The register set of GPIO have a significant change since AST2700.
> > Each GPIO pin has their own individual control register and users
Hi,
On Tuesday, September 24, 2024 4:16:26 PM GMT+5:30 Eugenio Perez Martin wrote:
> On Tue, Sep 24, 2024 at 7:31 AM Sahil wrote:
> > Hi,
> >
> > I have a small update.
> >
> > On Monday, September 16, 2024 10:04:28 AM GMT+5:30 Sahil wrote:
> > > On Thursday, September 12, 2024 3:24:27 PM GMT+5
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v3 05/17] intel_iommu: Rename slpte to pte
>
>On 2024/9/11 13:22, Zhenzhong Duan wrote:
>> From: Yi Liu
...
>> @@ -1918,13 +1919,13 @@ static bool
>vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
>>
>> cc_entry
On Sun, Sep 29, 2024 at 03:26:58PM -0500, Michael Galaxy wrote:
>
> On 9/29/24 13:14, Michael S. Tsirkin wrote:
> > !---|
> >This Message Is From an External Sender
> >This message came from outside your organization.
> > |---
On 9/29/24 12:38 PM, Peter Maydell wrote:
On Sat, 28 Sept 2024 at 21:40, Daniel Henrique Barboza
wrote:
On 9/28/24 8:34 AM, Peter Maydell wrote:
The assertion failure is
ERROR:../tests/qtest/riscv-iommu-test.c:72:test_reg_reset: assertion
failed (cap & RISCV_IOMMU_CAP_VERSION == 0x10): (
On 9/29/24 13:14, Michael S. Tsirkin wrote:
!---|
This Message Is From an External Sender
This message came from outside your organization.
|---!
On Sat, Sep 28
On Sat, Sep 28, 2024 at 12:52:08PM -0500, Michael Galaxy wrote:
> A bounce buffer defeats the entire purpose of using RDMA in these cases.
> When using RDMA for very large transfers like this, the goal here is to map
> the entire memory region at once and avoid all CPU interactions (except for
> me
Fix the handling of the ELF note that describes the PVH entrypoint
v2: fix broken ELF note handling on big endian hosts
Ard Biesheuvel (2):
hw/elf_ops: Implement missing endian swabbing for ELF notes
hw/x86: Always treat the PVH entrypoint as a 32-bit LE field
hw/i386/x86-common.c | 7
ELF notes have type and size fields in the elf_note header that need to
be swabbed before use if the host endianness differs from the endianness
of the ELF binary.
Signed-off-by: Ard Biesheuvel
---
include/hw/elf_ops.h.inc | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-
The PVH entrypoint is entered in 32-bit mode, and is documented as being
a 32-bit field. Linux happens to widen the field in the ELF note to 64
bits so treating it as a 64-bit field works for booting the kernel.
However, Xen documents the ELF note with the following example
ELFNOTE(Xen, XEN_ELF
From: Hyman Huang
To enable the responsive throttle that will be implemented
in the next commit, introduce the cpu-responsive-throttle
parameter.
Signed-off-by: Hyman Huang
---
migration/migration-hmp-cmds.c | 8
migration/options.c| 20
migration/opt
From: Hyman Huang
Currently, the convergence algorithm determines that the migration
cannot converge according to the following principle:
The dirty pages generated in current iteration exceed a specific
percentage (throttle-trigger-threshold, 50 by default) of the number
of transmissions. Let's
From: Hyman Huang
v2:
1. background sync - Throw out the idea of "not updating the bitmap"
when the RAMBlock of the RAM list is iterated during migration;
re-implement the background RAM dirty sync using Peter's updated
method.
2. responsive throttle - Rename the "cpu-responsive throttl
From: Hyman Huang
When VM is configured with huge memory, the current throttle logic
doesn't look like to scale, because migration_trigger_throttle()
is only called for each iteration, so it won't be invoked for a long
time if one iteration can take a long time.
The background dirty sync aim to
When the file-posix driver emulates append write, it holds the lock
whenever accessing wp, which limits the IO queue depth to one.
The write IO flow can be optimized to allow concurrent writes. The lock
is held in two cases:
1. Assumed that the write IO succeeds, update the wp before issuing the
w
When using a VDPA device, it is important to ensure that the MAC
address is correctly set.
There are only three acceptable situations for MAC setup; any other
configuration will fail to boot.
tested by ConnectX-6 Dx device
Cindy Lu (3):
virtio_net: Add the check for vdpa's mac address
virtio_
When using a VDPA device, the following situations are
also acceptable: the hardware MAC address is not 0,
and the MAC address in the QEMU command line is 0.
Signed-off-by: Cindy Lu
---
hw/net/virtio-net.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/net/virtio-net.c b/hw
While the hardware MAC address is 0 and the MAC address in
the QEMU command line is also 0, this configuration is
acceptable.
Signed-off-by: Cindy Lu
---
hw/net/virtio-net.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 5c610d807
When using a VDPA device, it is important to ensure that the MAC
address is correctly set. The MAC address in the hardware should
match the MAC address from the QEMU command line. This is a recommended
configuration and will allow the system to boot.
Signed-off-by: Cindy Lu
---
hw/net/virtio-net
On Sat, 28 Sept 2024 at 22:01, Daniel Henrique Barboza
wrote:
>
>
>
> On 9/28/24 5:22 PM, Peter Maydell wrote:
> > On Tue, 24 Sept 2024 at 23:19, Alistair Francis
> > wrote:
> >> +/* Register helper functions */
> >> +static inline uint32_t riscv_iommu_reg_mod32(RISCVIOMMUState *s,
> >> +un
On Sat, 28 Sept 2024 at 21:40, Daniel Henrique Barboza
wrote:
>
>
>
> On 9/28/24 8:34 AM, Peter Maydell wrote:
> > The assertion failure is
> > ERROR:../tests/qtest/riscv-iommu-test.c:72:test_reg_reset: assertion
> > failed (cap & RISCV_IOMMU_CAP_VERSION == 0x10): (0 == 16)
>
> The root cause is t
On 2024/9/11 13:22, Zhenzhong Duan wrote:
From: Yi Liu
This adds stage-1 page table walking to support stage-1 only
transltion in scalable modern mode.
a typo. s/tansltion/translation/
Signed-off-by: Yi Liu
Co-developed-by: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signe
This patch series add a new extension - zoned format - to the
qcow2 driver thereby allowing full zoned storage emulation on
the qcow2 img file. Users can attach such a qcow2 file to the
guest as a zoned device.
Write pointer are preserved in the zoned metadata. It will be
recovered after power cyc
To configure the zoned format feature on the qcow2 driver, it
requires settings as: the device size, zone model, zone size,
zone capacity, number of conventional zones, limits on zone
resources (max append bytes, max open zones, and max_active_zones).
To create a qcow2 image with zoned format feat
By adding zone operations and zoned metadata, the zoned emulation
capability enables full emulation support of zoned device using
a qcow2 file. The zoned device metadata includes zone type,
zoned device state and write pointer of each zone, which is stored
to an array of unsigned integers.
Each zo
Add the specs for the zoned format feature of the qcow2 driver.
The qcow2 file then can emulate real zoned devices, either passed
through by virtio-blk device or NVMe ZNS drive to the guest
given zoned information.
Signed-off-by: Sam Li
Reviewed-by: Stefan Hajnoczi
---
docs/system/qemu-block-dr
The zoned format feature can be tested by:
$ tests/qemu-iotests/check -qcow2 zoned-qcow2
Signed-off-by: Sam Li
Reviewed-by: Stefan Hajnoczi
---
tests/qemu-iotests/tests/zoned-qcow2 | 148 +++
tests/qemu-iotests/tests/zoned-qcow2.out | 173 +++
2 files cha
From: Sam Li
By adding zone operations and zoned metadata, the zoned emulation
capability enables full emulation support of zoned device using
a qcow2 file. The zoned device metadata includes zone type,
zoned device state and write pointer of each zone, which is stored
to an array of unsigned int
From: Sam Li
To configure the zoned format feature on the qcow2 driver, it
requires settings as: the device size, zone model, zone size,
zone capacity, number of conventional zones, limits on zone
resources (max append bytes, max open zones, and max_active_zones).
To create a qcow2 image with zo
This patch series add a new extension - zoned format - to the
qcow2 driver thereby allowing full zoned storage emulation on
the qcow2 img file. Users can attach such a qcow2 file to the
guest as a zoned device.
Write pointer are preserved in the zoned metadata. It will be
recovered after power cyc
From: Sam Li
Add the specs for the zoned format feature of the qcow2 driver.
The qcow2 file then can emulate real zoned devices, either passed
through by virtio-blk device or NVMe ZNS drive to the guest
given zoned information.
Signed-off-by: Sam Li
Reviewed-by: Stefan Hajnoczi
---
docs/syste
From: Sam Li
The zoned format feature can be tested by:
$ tests/qemu-iotests/check -qcow2 zoned-qcow2
Signed-off-by: Sam Li
Reviewed-by: Stefan Hajnoczi
---
tests/qemu-iotests/tests/zoned-qcow2 | 148 +++
tests/qemu-iotests/tests/zoned-qcow2.out | 173 +
On 2024/9/11 13:22, Zhenzhong Duan wrote:
From: Yi Liu
Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation,
rename variable and functions from slpte to pte whenever possible.
But some are SST only, they are renamed with sl_ prefix.
Signed-off-by: Yi Liu
Co-developed-
The check of cpu->phys_bits to be in range between
[32, TARGET_PHYS_ADDR_SPACE_BITS] in host_cpu_realizefn()
is duplicated with check in x86_cpu_realizefn().
Since the ckeck in x86_cpu_realizefn() is called later and can cover all
the x86 cases. Remove the one in host_cpu_realizefn().
Opportunist
From: Philippe Mathieu-Daudé
Nothing in LoongArch fw_cfg.c requires target specific definitions.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Song Gao
Message-Id: <20240927213254.17552-3-phi...@linaro.org>
Signed-off-by: Song Gao
---
hw/loongarch/meson.build | 2 +-
1 file changed, 1 i
From: Bibo Mao
Variable env->cf[i] is defined as bool type, it is treated as int type
with shift operation. However the max possible width is 56 for the shift
operation, exceeding the width of int type. And there is existing api
read_fcc() which is converted to u64 type with bitwise shift, it can
From: Jiaxun Yang
Use stl_p to write instructions so that host endian conversion
will be performed.
Replace mailbox read/write on LoongArch32 systems with 32bit IOCSR
instructions to prevent illegal instructions.
Signed-off-by: Jiaxun Yang
Reviewed-by: Song Gao
Message-Id: <20240914-loongarch
From: Jiaxun Yang
Refector EFI style booting data structure generation to
support 32bit EFI variant on LoongArch32 CPU.
All data structs are filled with padding members if necessary
and marked as QEMU_PACKED to avoid host ABI alignment impact.
Host endian is being cared as well.
It also fixed
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Song Gao
Message-Id: <20240927213254.17552-2-phi...@linaro.org>
Signed-off-by: Song Gao
---
include/hw/loongarch/virt.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/loongarch/virt.h b/include/hw/l
-loongarch-20240929
for you to fetch changes up to f7c8ef7bad7495d8c84b262a8b243efe39e56b13:
hw/loongarch/fw_cfg: Build in common_ss[] (2024-09-29 16:22:56 +0800)
pull-loongarc
From: Bibo Mao
ACPI ged is used for power management on LoongArch virt platform, in
general it is parsed from acpi table. However if system boot directly from
elf kernel, no UEFI bios is provided and acpi table cannot be used also.
Here acpi ged pm register is exposed with FDT table, it is compa
From: Bibo Mao
Macro definition is added for acpi sleep control register, ged emulation
driver can use the macro , also it can be used in FDT table if ged is
exposed with FDT table.
Signed-off-by: Bibo Mao
Reviewed-by: Igor Mammedov
Message-Id: <20240918014206.2165821-2-maob...@loongson.cn>
Si
在 2024/9/28 上午5:32, Philippe Mathieu-Daudé 写道:
LoongArch fw_cfg.c doesn't use target specific declarations,
build it as common object.
Philippe Mathieu-Daudé (2):
hw/loongarch/virt: Remove unnecessary 'cpu.h' inclusion
hw/loongarch/fw_cfg: Build in common_ss[]
include/hw/loongarch/virt.
在 2024/9/14 下午8:10, Jiaxun Yang 写道:
Hi all,
This series refactored booting protocol generation code
to better accommodate different host ABI / Alignment and
endianess.
It also enhanced LoongArch32 support.
Thanks
Signed-off-by: Jiaxun Yang
---
Jiaxun Yang (2):
hw/loongarch/boot: Refac
在 2024/9/18 上午9:42, Bibo Mao 写道:
ACPI ged is used for power management on LoongArch virt platform, in
general it is parsed from acpi table. However if system boot directly from
elf kernel, no UEFI bios is provided and acpi table cannot be used also.
Here acpi ged pm register is exposed with FDT
在 2024/9/18 上午9:42, Bibo Mao 写道:
ACPI ged is used for power management on LoongArch virt platform, in
general it is parsed from acpi table. However if system boot directly from
elf kernel, no UEFI bios is provided and acpi table cannot be used also.
Here acpi ged pm register is exposed with FDT
在 2024/9/14 下午2:46, Bibo Mao 写道:
Variable env->cf[i] is defined as bool type, it is treated as int type
with shift operation. However the max possible width is 56 for the shift
operation, exceeding the width of int type. And there is existing api
read_fcc() which is converted to u64 type with bit
KVM LBT supports on LoongArch requires the linux-header kvm_para.h,
also unistd_64.h is required by unistd.h on LoongArch since 6.11
Signed-off-by: Bibo Mao
---
scripts/update-linux-headers.sh | 4
1 file changed, 4 insertions(+)
diff --git a/scripts/update-linux-headers.sh b/scripts/updat
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
eflags (eflags) and x87 fpu stack pointer (ftop).
Now LBT feature is added in kvm mode, not supported in TCG mode since
it is not emulated. Feature variable lbt is
Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate.
And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added
to save/restore lbt registers.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu.h | 12
target/loongarch/kvm/kvm.c | 62 +++
Loongson Binary Translation (LBT) is used to accelerate binary
translation. LBT feature is added in kvm mode, not supported in TCG
mode since it is not emulated.
Here lbt=on/off property is added to parse command line to
enable/disable lbt feature. Also fix registers relative lbt are saved
and res
54 matches
Mail list logo
