[PULL v3 22/35] bsd-user: Implement RISC-V TLS register setup

t Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-5-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch.h | 27 +++ bsd-user/riscv/target_arch_cpu.c | 29 + 2 files changed, 56 inserti

[PULL v3 25/35] bsd-user: Add RISC-V signal trampoline setup function

t; Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_sigtramp.h | 41 +++ 1 file changed, 41 insertions(+) create mode 100644 bsd-user/riscv/target_arch_sigtramp.h diff --git a/bsd-user/riscv/target_arch_sigtramp.h b/bsd-user/riscv/target_arch_sigtramp.h new file m

[PULL v3 33/35] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-16-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/signal.c | 53 +++

[PULL v3 11/35] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc

command failed add '#include "asm/unistd.h"' to util/cpuinfo-riscv.c fixes build Signed-off-by: Milan P. Stanić Reviewed-by: Alistair Francis Message-ID: <20240905150702.2484-1-...@arvanta.net> Signed-off-by: Alistair Francis --- util/cpuinfo-riscv.c | 1 + 1 file chang

[PULL v3 20/35] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-3-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 inse

[PULL v3 08/35] target/riscv/kvm: Fix the group bit setting of AIA

same for the group bit setting. Signed-off-by: Andrew Jones Reviewed-by: Daniel Henrique Barboza Message-ID: <20240821075040.498945-2-ajo...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff -

[PULL v3 32/35] bsd-user: Implement RISC-V signal trampoline setup functions

-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-15-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/signal.c | 63 + 1 file changed

[PULL v3 17/35] target/riscv/cpu_helper: Fix linking problem with semihosting disabled

Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Message-ID: <20240906094858.718105-1-th...@redhat.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 ++ target/riscv/Kconfig | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/

[PULL v3 35/35] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-18-itac...@freebsd.org> Signed-off-by: Alistair Francis --- configs/targets/riscv

[PULL v3 23/35] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-6-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create

[PULL v3 16/35] target/riscv32: Fix masking of physical address

ies.") Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-ID: <20240909083241.43836-2-ajo...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --

[PULL v3 24/35] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-7-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_reg.h | 88

[PULL v3 00/35] riscv-to-apply queue

MSIC interrupt state updates Alexandre Ghiti (1): target: riscv: Add Svvptc extension support Alistair Francis (1): target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Alvin Chang (2): target/riscv: Preliminar

[PULL v3 07/35] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU

From: Alistair Francis The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc and Zbs bit-manipulation sub-extensions ratified in v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable them in QEMU as well. 1: https://github.com/lowRISC/opentitan/pull/9748 Signed-o

[PULL v3 34/35] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-17-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/signal.c | 54 + 1 file changed, 54 insertions(+) diff --git a/bsd

[PULL v3 27/35] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-10-itac...@freebsd.org> Signed-off-by: Alistair Fr

[PULL v3 29/35] bsd-user: Define RISC-V system call structures and constants

Singh Co-authored-by: Jessica Clarke Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-12-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_syscall.h | 38 + 1 file changed, 38 insertions(+) create mode 10064

[PULL v3 31/35] bsd-user: Define RISC-V signal handling structures and constants

-14-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_signal.h | 75 + 1 file changed, 75 insertions(+) create mode 100644 bsd-user/riscv/target_arch_signal.h diff --git a/bsd-user/riscv/target_arch_signal.h b/bsd-user

[PULL v3 21/35] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-4-itac...@freebsd.org> Signed-off-by: Alistair F

[PULL v3 04/35] tests/acpi: Add expected ACPI SRAT AML file for RISC-V

output is not added. Signed-off-by: Haibo Xu Reviewed-by: Sunil V L Acked-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/riscv64/virt/SRAT.numamem | Bin 0 -> 108 bytes 2 files changed, 1 delet

[PULL v3 28/35] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-11-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) creat

[PULL v3 18/35] hw/intc: riscv-imsic: Fix interrupt state updates.

of eistate are converted to atomic operations. Signed-off-by: Tomasz Jeznach Reviewed-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- hw/intc/riscv_imsic.c | 50 +++ 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/hw

[PULL v3 30/35] bsd-user: Add generic RISC-V64 target definitions

Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-13-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target.h | 20 1 file changed, 20 insertions(+) create mode 100644 bsd-user/riscv/target.h diff --git a/bsd-user/riscv/target.h

[PULL v3 13/35] target/riscv: Add textra matching condition for the triggers

textra.MHSELECT is 4, we compare textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis Message-ID: <20240826024657.26255

[PULL v3 26/35] bsd-user: Implement RISC-V sysarch system call emulation

in Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-9-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_sysarch.h | 41 1 file changed, 41 insertions(+) create mode 100644 bsd-user/riscv/tar

[PULL v3 19/35] bsd-user: Implement RISC-V CPU initialization and main loop

-by: Jessica Clarke Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-2-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_cpu.h | 40 1 file changed, 40 insertions(+) create mode 100644 bsd-user

[PULL v3 15/35] target: riscv: Add Svvptc extension support

ault since it allows to drastically reduce the number of sfence.vma emitted by S-mode. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Message-ID: <20240828083651.203861-1-alexgh...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/ris

[PULL v3 14/35] hw/riscv: Respect firmware ELF entry point

FW_TEXT_START values other than 0x8000. Signed-off-by: Samuel Holland Reviewed-by: Alistair Francis Message-ID: <20240817002651.3209701-1-samuel.holl...@sifive.com> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h| 4 ++-- hw/riscv/boot.c| 11 ++- hw

[PULL v3 09/35] target/riscv: Stop timer with infinite timecmp

quot;) Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20240829084002.1805006-2-ajo...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/time_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/time_helper.c b/target/riscv/time

[PULL v3 01/35] target/riscv: Add a property to set vl to ceil(AVL/2)

-by: Jason Chien Reviewed-by: Frank Chang Message-ID: <20240722175004.23666-1-jason.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 1 + target/riscv/vector_helper.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/

[PULL v3 05/35] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule

ion implied rule helpers") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240824173338.31-1-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deleti

[PULL v3 02/35] tests/acpi: Add empty ACPI SRAT data file for RISC-V

From: Haibo Xu As per process documented (steps 1-3) in bios-tables-test.c, add empty AML data file for RISC-V ACPI SRAT table and add the entry in bios-tables-test-allowed-diff.h. Signed-off-by: Haibo Xu Reviewed-by: Sunil V L Acked-by: Alistair Francis Message-ID

[PULL v3 12/35] target/riscv: Preliminary textra trigger CSR writting support

Reviewed-by: Alistair Francis Message-ID: <20240826024657.262553-2-alvi...@andestech.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 10 ++ target/riscv/debug.c| 69 + 2 files changed, 73 insertions(+), 6 deletions(-) diff -

[PULL v3 03/35] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V

From: Haibo Xu Add ACPI SRAT table test case for RISC-V when NUMA was enabled. Signed-off-by: Haibo Xu Reviewed-by: Sunil V L Acked-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test.c | 28 1 file changed, 28

Re: [PATCH] hw/char/riscv_htif: Fix htif_mm_write that causes infinite loop in ACT.

On Fri, Sep 27, 2024 at 11:26 PM MingZhu Yan wrote: > > Applications sometimes only write the lower 32-bit payload bytes, this is used > in ACT tests. As a workaround, this refers to the solution of sail-riscv. I'm not sure what ACT is, but this feels like a guest bug, not a QEMU issue. Alistair

[PULL v2 05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule

ion implied rule helpers") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240824173338.31-1-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deleti

[PULL v2 42/47] bsd-user: Add generic RISC-V64 target definitions

Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-13-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target.h | 20 1 file changed, 20 insertions(+) create mode 100644 bsd-user/riscv/target.h diff --git a/bsd-user/riscv/target.h

[PULL v2 44/47] bsd-user: Implement RISC-V signal trampoline setup functions

-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-15-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/signal.c | 63 + 1 file changed

[PULL v2 11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc

command failed add '#include "asm/unistd.h"' to util/cpuinfo-riscv.c fixes build Signed-off-by: Milan P. Stanić Reviewed-by: Alistair Francis Message-ID: <20240905150702.2484-1-...@arvanta.net> Signed-off-by: Alistair Francis --- util/cpuinfo-riscv.c | 1 + 1 file chang

[PULL v2 31/47] bsd-user: Implement RISC-V CPU initialization and main loop

-by: Jessica Clarke Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-2-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_cpu.h | 40 1 file changed, 40 insertions(+) create mode 100644 bsd-user

[PULL v2 45/47] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-16-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/signal.c | 53 +++

[PULL v2 12/47] target/riscv: Preliminary textra trigger CSR writting support

Reviewed-by: Alistair Francis Message-ID: <20240826024657.262553-2-alvi...@andestech.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 10 ++ target/riscv/debug.c| 69 + 2 files changed, 73 insertions(+), 6 deletions(-) diff -

[PULL v2 28/47] target/riscv32: Fix masking of physical address

ies.") Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-ID: <20240909083241.43836-2-ajo...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --

[PULL v2 27/47] target: riscv: Add Svvptc extension support

ault since it allows to drastically reduce the number of sfence.vma emitted by S-mode. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Message-ID: <20240828083651.203861-1-alexgh...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/ris

[PULL v2 36/47] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-7-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_reg.h | 88

[PULL v2 40/47] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-11-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) creat

[PULL v2 34/47] bsd-user: Implement RISC-V TLS register setup

t Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-5-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch.h | 27 +++ bsd-user/riscv/target_arch_cpu.c | 29 + 2 files changed, 56 inserti

[PULL v2 21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

nd g-stage elements, although we don't support it yet. We'll introduce them next. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Acked-by: Alistair Francis Message-ID: <20240903201633.93182-9-dbarb...@ventanamicro.com> Signed-off-by:

[PULL v2 37/47] bsd-user: Add RISC-V signal trampoline setup function

t; Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_sigtramp.h | 41 +++ 1 file changed, 41 insertions(+) create mode 100644 bsd-user/riscv/target_arch_sigtramp.h diff --git a/bsd-user/riscv/target_arch_sigtramp.h b/bsd-user/riscv/target_arch_sigtramp.h new file m

[PULL v2 43/47] bsd-user: Define RISC-V signal handling structures and constants

-14-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_signal.h | 75 + 1 file changed, 75 insertions(+) create mode 100644 bsd-user/riscv/target_arch_signal.h diff --git a/bsd-user/riscv/target_arch_signal.h b/bsd-user

[PULL v2 41/47] bsd-user: Define RISC-V system call structures and constants

Singh Co-authored-by: Jessica Clarke Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-12-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_syscall.h | 38 + 1 file changed, 38 insertions(+) create mode 10064

[PULL v2 24/47] qtest/riscv-iommu-test: add init queues test

t from the software/OS when initializing the IOMMU. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Acked-by: Alistair Francis Message-ID: <20240903201633.93182-12-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- tests/qtest/libqos/riscv-iommu.h | 30 +

[PULL v2 33/47] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-4-itac...@freebsd.org> Signed-off-by: Alistair F

[PULL v2 23/47] hw/riscv/riscv-iommu: add DBG support

Francis Message-ID: <20240903201633.93182-11-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 17 +++ hw/riscv/riscv-iommu.c | 59 + 2 files changed, 76 insertions(+) diff --git a/hw/riscv/riscv

[PULL v2 39/47] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-10-itac...@freebsd.org> Signed-off-by: Alistair Fr

[PULL v2 46/47] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-17-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/signal.c | 54 + 1 file changed, 54 insertions(+) diff --git a/bsd

[PULL v2 38/47] bsd-user: Implement RISC-V sysarch system call emulation

in Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-9-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_sysarch.h | 41 1 file changed, 41 insertions(+) create mode 100644 bsd-user/riscv/tar

[PULL v2 35/47] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-6-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create

[PULL v2 04/47] tests/acpi: Add expected ACPI SRAT AML file for RISC-V

output is not added. Signed-off-by: Haibo Xu Reviewed-by: Sunil V L Acked-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/riscv64/virt/SRAT.numamem | Bin 0 -> 108 bytes 2 files changed, 1 delet

[PULL v2 47/47] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-18-itac...@freebsd.org> Signed-off-by: Alistair Francis --- configs/targets/riscv

[PULL v2 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device

iel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Gerd Hoffmann Message-ID: <20240903201633.93182-5-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- docs/specs/pci-ids.rst | 2 ++ include/hw/pci/pci.h | 1 + 2 files changed, 3 insertions(+) diff --git a/docs/spec

[PULL v2 29/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled

Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Message-ID: <20240906094858.718105-1-th...@redhat.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 ++ target/riscv/Kconfig | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/

[PULL v2 09/47] target/riscv: Stop timer with infinite timecmp

quot;) Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20240829084002.1805006-2-ajo...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/time_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/time_helper.c b/target/riscv/time

[PULL v2 03/47] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V

From: Haibo Xu Add ACPI SRAT table test case for RISC-V when NUMA was enabled. Signed-off-by: Haibo Xu Reviewed-by: Sunil V L Acked-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test.c | 28 1 file changed, 28

[PULL v2 02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V

From: Haibo Xu As per process documented (steps 1-3) in bios-tables-test.c, add empty AML data file for RISC-V ACPI SRAT table and add the entry in bios-tables-test-allowed-diff.h. Signed-off-by: Haibo Xu Reviewed-by: Sunil V L Acked-by: Alistair Francis Message-ID

[PULL v2 08/47] target/riscv/kvm: Fix the group bit setting of AIA

same for the group bit setting. Signed-off-by: Andrew Jones Reviewed-by: Daniel Henrique Barboza Message-ID: <20240821075040.498945-2-ajo...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff -

[PULL v2 16/47] hw/riscv: add RISC-V IOMMU base emulation

: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20240903201633.93182-4-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- meson.build |1 + hw/riscv/riscv-iommu-bits.h | 18 + hw/riscv/riscv-iommu.h | 145 +

[PULL v2 14/47] exec/memtxattr: add process identifier to the transaction attributes

Reviewed-by: Jason Chien Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza Message-ID: <20240903201633.93182-2-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- include/exec/memattrs.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/exec/mematt

[PULL v2 07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU

From: Alistair Francis The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc and Zbs bit-manipulation sub-extensions ratified in v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable them in QEMU as well. 1: https://github.com/lowRISC/opentitan/pull/9748 Signed-o

[PULL v2 19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug

From: Tomasz Jeznach Generate device tree entry for riscv-iommu PCI device, along with mapping all PCI device identifiers to the single IOMMU device instance. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Message

[PULL v2 15/47] hw/riscv: add riscv-iommu-bits.h

en Reviewed-by: Alistair Francis Message-ID: <20240903201633.93182-3-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 345 1 file changed, 345 insertions(+) create mode 100644 hw/riscv/riscv-iommu-bits.h diff --git a

[PULL v2 26/47] hw/riscv: Respect firmware ELF entry point

FW_TEXT_START values other than 0x8000. Signed-off-by: Samuel Holland Reviewed-by: Alistair Francis Message-ID: <20240817002651.3209701-1-samuel.holl...@sifive.com> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h| 4 ++-- hw/riscv/boot.c| 11 ++- hw

[PULL v2 22/47] hw/riscv/riscv-iommu: add ATS support

: Frank Chang Acked-by: Alistair Francis Message-ID: <20240903201633.93182-10-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 43 +++- hw/riscv/riscv-iommu.h | 1 + hw/riscv/riscv-iommu.c

[PULL v2 01/47] target/riscv: Add a property to set vl to ceil(AVL/2)

-by: Jason Chien Reviewed-by: Frank Chang Message-ID: <20240722175004.23666-1-jason.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 1 + target/riscv/vector_helper.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/

[PULL v2 30/47] hw/intc: riscv-imsic: Fix interrupt state updates.

of eistate are converted to atomic operations. Signed-off-by: Tomasz Jeznach Reviewed-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- hw/intc/riscv_imsic.c | 50 +++ 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/hw

[PULL v2 32/47] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-ID: <20240916155119.14610-3-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 inse

[PULL v2 13/47] target/riscv: Add textra matching condition for the triggers

textra.MHSELECT is 4, we compare textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis Message-ID: <20240826024657.26255

[PULL v2 20/47] test/qtest: add riscv-iommu-pci tests

e RISC-V libqos machine. Start with basic tests: a PCI sanity check and a reset state register test. The reset test was taken from the RISC-V IOMMU spec chapter 5.2, "Reset behavior". More tests will be added later. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Acked-by:

[PULL v2 18/47] hw/riscv: add riscv-iommu-pci reference device

: Alistair Francis Message-ID: <20240903201633.93182-6-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-pci.c | 202 + hw/riscv/meson.build | 2 +- 2 files changed, 203 insertions(+), 1 deletion(-) create mode

[PULL v2 25/47] docs/specs: add riscv-iommu

From: Daniel Henrique Barboza Add a simple guideline to use the existing RISC-V IOMMU support we just added. This doc will be updated once we add the riscv-iommu-sys device. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240903201633.93182-13-db

[PULL v2 00/47] riscv-to-apply queue

linking problem with semihosting disabled * Fix IMSIC interrupt state updates Alexandre Ghiti (1): target: riscv: Add Svvptc extension support Alistair Francis (1): target: riscv: Enable Bit Manip for OpenTitan Ibex

Re: [PATCH v7 00/17] bsd-user: Comprehensive RISCV Support

On Tue, Sep 17, 2024 at 1:54 AM Ajeet Singh wrote: > > Key Changes Compared to Version 6: > Included "signal-common.h" in target_arch_cpu.h > > Mark Corbin (15): > bsd-user: Implement RISC-V CPU initialization and main loop > bsd-user: Add RISC-V CPU execution loop and syscall handling > bsd

Re: [PULL 00/47] riscv-to-apply queue

On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell wrote: > > On Thu, 12 Sept 2024 at 06:30, Alistair Francis wrote: > > > > The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f: > > > > Merge tag 'pull-testing-gdbstub-oct-100924-1'

[PULL 13/47] target/riscv: Add textra matching condition for the triggers

textra.MHSELECT is 4, we compare textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis Message-ID: <20240826024657.26255

[PULL 12/47] target/riscv: Preliminary textra trigger CSR writting support

Reviewed-by: Alistair Francis Message-ID: <20240826024657.262553-2-alvi...@andestech.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 10 ++ target/riscv/debug.c| 69 + 2 files changed, 73 insertions(+), 6 deletions(-) diff -

[PULL 24/47] qtest/riscv-iommu-test: add init queues test

t from the software/OS when initializing the IOMMU. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Acked-by: Alistair Francis Message-ID: <20240903201633.93182-12-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- tests/qtest/libqos/riscv-iommu.h | 30 +

[PULL 23/47] hw/riscv/riscv-iommu: add DBG support

Francis Message-ID: <20240903201633.93182-11-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 17 +++ hw/riscv/riscv-iommu.c | 59 + 2 files changed, 76 insertions(+) diff --git a/hw/riscv/riscv

[PULL 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device

iel Henrique Barboza Reviewed-by: Frank Chang Reviewed-by: Gerd Hoffmann Message-ID: <20240903201633.93182-5-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- docs/specs/pci-ids.rst | 2 ++ include/hw/pci/pci.h | 1 + 2 files changed, 3 insertions(+) diff --git a/docs/spec

[PULL 28/47] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-4-itac...@freebsd.org> Signed-off-by: Alistair F

[PULL 22/47] hw/riscv/riscv-iommu: add ATS support

: Frank Chang Acked-by: Alistair Francis Message-ID: <20240903201633.93182-10-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 43 +++- hw/riscv/riscv-iommu.h | 1 + hw/riscv/riscv-iommu.c

[PULL 46/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled

Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Message-ID: <20240906094858.718105-1-th...@redhat.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 ++ target/riscv/Kconfig | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/

[PULL 39/47] bsd-user: Implement RISC-V signal trampoline setup functions

-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-15-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/signal.c | 63 + 1 file changed

[PULL 40/47] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-16-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/signal.c | 53 + 1 f

[PULL 42/47] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-18-itac...@freebsd.org> Signed-off-by: Alistair Francis --- configs/targets/riscv

[PULL 26/47] bsd-user: Implement RISC-V CPU initialization and main loop

-by: Jessica Clarke Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-2-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_cpu.h | 39 1 file changed, 39 insertions(+) create mode 100644 bsd-user

[PULL 41/47] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-17-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/signal.c | 54 + 1 file changed, 54 insertions(+) diff --git a/bsd

[PULL 20/47] test/qtest: add riscv-iommu-pci tests

e RISC-V libqos machine. Start with basic tests: a PCI sanity check and a reset state register test. The reset test was taken from the RISC-V IOMMU spec chapter 5.2, "Reset behavior". More tests will be added later. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Acked-by:

[PULL 45/47] target/riscv32: Fix masking of physical address

ies.") Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-ID: <20240909083241.43836-2-ajo...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --

[PULL 38/47] bsd-user: Define RISC-V signal handling structures and constants

tac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_signal.h | 75 + 1 file changed, 75 insertions(+) create mode 100644 bsd-user/riscv/target_arch_signal.h diff --git a/bsd-user/riscv/target_arch_signal.h b/bsd-user

[PULL 30/47] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-6-itac...@freebsd.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create

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