32-bit BE
host during the week-end.
Aurelien
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bit guests, but I guess that's something acceptable, as
it's not a regression.
Aurelien
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Thanks, this look good. I have tried it with my test image, and it
doesn't break it.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Acked-by: Aurelien Jarno <aurel...@aurel32.net>
I consider this as a bugfix, not a new feature, so that should be fine
despite the soft freeze. Do
out the exact comand line that is
> > > used to compile this file?
> >
> > Yes, lt was added with the extended immidiate facility. So either use
> > -march=z9-109 (introduced in
> > 2005) or replace the lt with an l + ltr to also run on older models.
> >
>
;
> #else
> int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> CPUTLBEntry *tlbentry = >tlb_table[mmu_idx][index];
That looks fine to me, sorry for the typo.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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t;fullma...@gmail.com>
> ---
> Changes from v1:
> * Add the 'https://' part to the link in hw/sh4/shix.c.
>
> hw/sh4/shix.c | 2 +-
> target-sh4/README.sh4 | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Thanks for the new version.
Acked-by: Au
front. It will go over
the 80 characters limits, but I think that's fine in such a case.
I guess this will be merged through the trivial queue, that seems the
best to me.
Aurelien
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-*/
> -void float_raise(int8_t flags, float_status *status);
> +void float_raise(uint8_t flags, float_status *status);
>
>
> /*--------
> | If `a' is denormal and we are in flush-to-zero mode
On 2016-08-09 22:12, Peter Maydell wrote:
> On 9 August 2016 at 20:16, Aurelien Jarno <aurel...@aurel32.net> wrote:
> > On 2016-08-09 15:02, Pranith Kumar wrote:
> >> Change the flag type to 'int' to fix the implicit conversion error.
> >>
> >> Suggested-b
/* should denormalised results go to zero and set the inexact flag? */
> flag flush_to_zero;
This changes the size of the structure, and thus of the CPU*State
structures. I don't think it's something we want to do, especially given
we currently only use 7 flags, so 7 bits an
iewed-by: Aurelien Jarno <aurel...@aurel32.net>
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the
optimization time and the level of optimization.
Nevertheless I think it's the correct way to go forward for now and
this patch fixes real issues on hosts with limited registers. Maybe just
add a note saying there *might* be better ways to do that.
Reviewed-by: Aurelien Jarno <aurel
e logfile is the
terminal. As such when not dumping to the file, the alignment is wrong.
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On 2016-06-23 20:48, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/tcg.c | 26 ++
> 1 file changed, 26 insertions(+)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
e. The other alternative would have been to use
the TCGTempSet with the bitmap functions like in optimize.c, and use
only 2 bits per temp. That something that can be done later though.
All that said and provided you change the name:
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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> 2 files changed, 17 insertions(+), 18 deletions(-)
This looks fine and goes in the right direction of having all the data
at the same location. In the long term it might be useful to have the
TCG stream and the associated data together to implement more agressive
optimisations
16;
> -signed next : 16;
> +/* Index of the prex/next op, or 0 for the end of the list. */
It's not introduced by your patch, but you might want to fix the typo
prex -> prev.
> +unsigned prev : 16;
> +unsigned next : 16;
> } TCGOp;
>
> -QEMU_BUILD_BUG_ON(NB_OPS > 0xff);
> -QEMU_BUILD_BUG_ON(OPC_BUF_SIZE >= 0x7fff);
> -QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE >= 0x7fff);
> +/* Make sure operands fit in the bitfields above. */
> +QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
> +QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16));
> +QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 16));
> +
> +/* Make sure that we don't overflow 64 bits without noticing. */
> +QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8);
>
> struct TCGContext {
> uint8_t *pool_cur, *pool_end;
It seems that gen_first_op_idx and gen_last_op_idx are now unused.
Shouldn't they be removed?
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re and given the kind of optimisations we are doing there
it became quite difficult to compare the generated code with and without
liveness.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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pstrcat(buf, sizeof(buf), "_1");
> -ts->name = strdup(buf);
> +ts2->name = strdup(buf);
> } else {
> ts->base_type = type;
> ts->type = type;
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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A small improvement, probably for later: we can zero the s->op_arg_life
structure, and then access it directly instead of using the arg_life
temporary variable.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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On 2016-06-18 22:48, Hervé Poussineau wrote:
> Hi Aurélien,
>
> Le 20/05/2016 à 21:56, Aurelien Jarno a écrit :
> > On 2016-05-20 15:05, Hervé Poussineau wrote:
> > > Incidentally, this fixes YAMON on big endian guest.
> > >
> > > Signed-off-
ixed for 2.7, but this is
> complex enough I'd prefer another set of eyes.
I'll try to have a look during the week-end. Sorry about the delay.
--
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aurel...@aurel32.net http://www.aurel32.net
uration mismatch but QEMU would previously
> incorrectly jump & wind up printing a continuous stream of the letter E.
>
> Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
> Cc: Aurelien Jarno <aurel...@aurel32.net>
> Cc: Leon Alrae <leon.al...@imgtec.com>
>
ked at it and test it. It's all fine, sorry for the
delay.
Acked-by: Aurelien Jarno <aurel...@aurel32.net>
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aurel...@aurel32.net http://www.aurel32.net
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
> +kernel_cmdline);
> +if (r < 0) {
> +fprintf(stderr, "couldn't set /chosen/bootargs\n");
> +}
> +}
>
ister will now read
> back as MAX_ETH_FRAME_SIZE rather than 0 if written with
> an overlarge value.
>
> Do we have any documentation on how this (simulated)
> device is supposed to behave in this case?
This device is not supported by the linux kernel for more than 2.5 years
(since v3.7). Do we want to keep this device in QEMU?
Aurelien
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mes to avoid a confusion.
Unless I missed something, it seems that the is_user/mmu_idx argument is
never used. Should we maybe just drop it?
Otherwise it looks fine.
--
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aurel...@aurel32.net http://www.aurel32.net
case 0x1c0:
> return pcic->par;
> case 0x1c4:
Thanks for the patch. I confirm it builds and works fine.
Acked-by: Aurelien Jarno <aurel...@aurel32.net>
--
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aurel...@aurel32.net http://www.aurel32.net
ath as I know this is
> something you've had issues with before and I couldn't quite figure out how to
> reproduce your TRIM tests from before.
I have just tested the TRIM path, all works fine with your 2 patches
applied.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9
_op_call: /* Always emitted via tcg_out_call. */
> @@ -1716,6 +1720,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
> { INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } },
> { INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ&qu
(size == 2) {
> +return lduw_le_p(buf);
> +} else if (size == 4) {
> +return ldl_le_p(buf);
> +} else {
> +g_assert_not_reached();
> + }
The device is configured is little endian, and then the little endian
value converted into native endianness. Wouldn't it be simple to declare
it as DEVICE_NATIVE_ENDIAN?
Aurelien
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of sizeof(). Fix that.
Cc: Stefan Weil <s...@weilnetz.de>
Cc: Leon Alrae <leon.al...@imgtec.com>
LP: https://bugs.launchpad.net/qemu/+bug/1577841
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target-mips/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
ng));
> >
> > ** Affects: qemu
> > Importance: Undecided
> > Status: New
>
> This might be an error. I think it should be
>
> memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
>
I confirm this is the correct version of the co
ed to the inner guest.
>
> Fixes: b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR")
> Signed-off-by: James Hogan <james.ho...@imgtec.com>
> Cc: Leon Alrae <leon.al...@imgtec.com>
> Cc: Yongbok Kim <yongbok@imgtec.com>
> Cc: Aurelien
fore by chance by loading
a random value into the register. That said to look deeper into it, it
would be better to be able to reproduce the issue.
Aurelien
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On 2016-04-22 20:00, Sergey Fedorov wrote:
> On 22/04/16 19:51, Aurelien Jarno wrote:
> > On 2016-04-22 18:47, Aurelien Jarno wrote:
> >> On 2016-04-22 19:08, Sergey Fedorov wrote:
> >>> From: Sergey Fedorov <serge.f...@gmail.com>
> >>>
> >>
On 2016-04-22 18:47, Aurelien Jarno wrote:
> On 2016-04-22 19:08, Sergey Fedorov wrote:
> > From: Sergey Fedorov <serge.f...@gmail.com>
> >
> > Ensure direct jump patching in MIPS is atomic by using
> > atomic_read()/atomic_set() for code patching.
> >
>
t32_t *)jmp_addr;
> -*ptr = deposit32(*ptr, 0, 26, addr >> 2);
> +uint32_t insn = atomic_read(ptr);
> +atomic_set(ptr, deposit32(insn, 0, 26, addr >> 2));
> flush_icache_range(jmp_addr, jmp_addr + 4);
Does it really make sense to read and write the value at
ces. This patch replaces all the calls to assert into
calss to tcg_debug_assert.
Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tcg/aarch64/tcg-target.inc.c | 24
Check for CONFIG_DEBUG_TCG instead of NDEBUG, drop now useless code.
Cc: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tcg/aarch64/tcg-target.inc.c | 4 ++--
tcg/arm/tcg-target.inc.c | 2 +-
tcg/i386/tcg-target.inc.c| 2 +-
David Gibson <da...@gibson.dropbear.id.au>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
hw/misc/macio/cuda.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
index c7472aa..f15f301 100644
--- a/hw/misc/macio/cuda.
^
>
> Make it an array of ints to fix the build and match other architectures.
>
> Fixes: 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different
> order")
> Signed-off-by: James Hogan <james.ho...@imgtec.com>
> Cc: Aurelien Jarno <au
; int msb = ctz32(~a2) - 1;
> -assert(use_mips32r2_instructions);
> - assert(is_p2m1(a2));
> +tcg_debug_assert(use_mips32r2_instructions);
> +tcg_debug_assert(is_p2m1(a2));
> tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
> break;
> }
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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next days.
I have a few comments on the individual patches, I'll send them asap.
Note that I don't have an R6 machine, so I haven't been able to test
that part.
Aurelien
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+++++
I don't think you want to add this file to the git.
--
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+-
> 1 file changed, 13 insertions(+), 13 deletions(-)
Thanks for the cleanup.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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gt; ++--
> include/fpu/softfloat.h | 16 ++---
> include/qemu/osdep.h| 7 ---
> 4 files changed, 104 insertions(+), 99 deletions(-)
Great work.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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---
> Would anybody else like to be listed here (ie to be cc'd on softfloat
> patches) ? Richard? Aurelien?
As long as it is in "Odd Fixes" mode, it would like to get it listed
please. I don't have time to follow the whole mailing list anymore, so
being Cc'd n on softfloat pa
On 2016-01-15 14:21, Peter Maydell wrote:
> On 13 January 2016 at 16:03, Aurelien Jarno <aurel...@aurel32.net> wrote:
> > The roundAndPackFloat16 function should return a float16 value, not a
> > float32 one. Fix that.
> >
> > Cc: Peter Maydell <pete
+-
> hw/ppc/spapr_events.c | 4 +-
> include/fpu/softfloat.h| 68 ++
> include/hw/i386/pc.h | 2 +-
> migration/ram.c| 2 +-
> target-alpha/fpu_helper.c | 2 +-
> target-mips/kvm.c | 4 +-
> target-mips/msa_helper.c
The roundAndPackFloat16 function should return a float16 value, not a
float32 one. Fix that.
Cc: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
fpu/softfloat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Peter, given you
TCGv t1 = tcg_temp_new();
> gen_load_gpr(t1, rs);
The resulting binary code should be the same, but less #ifdef means less
risk of breakage, as the code is always compiled.
--
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On 2015-12-17 12:00, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/tcg.c | 113
> ++
> tcg/tcg.h | 6 ++--
> 2 files changed, 57 insertions(+), 62 deletions(-)
Rev
+--
> target-tricore/translate.c| 22 ++--
> target-unicore32/translate.c | 2 +-
> target-xtensa/translate.c | 10 +++---
> tcg/tcg.c | 21 +++
> tcg/tcg.h | 38 +++-
> 22 files changed, 282 insertions(+)
veness analysis already ensures that temps are dead.
> - Keep an assert for safety. */
> -assert(ts->val_type == TEMP_VAL_DEAD);
> -#else
> -temp_dead(s, ts);
> +/* ??? Liveness does not yet incorporate indirect bases.
: sign extend ? */
And here.
> -tcg_out_movi(s, ts->type, reg, ts->val);
> } else {
> -tcg_abort();
> +TCGRegSet arg_set;
> +
> + tcg_regset_clear(arg_set);
> + tcg_regset_set_reg(arg_set
This is simple bar the existing reserved_regs check.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/tcg.c | 65
> +++
> tcg/tcg.h | 4 ++--
> 2 files changed, 38 insertions(+), 31 del
On 2015-12-17 12:00, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/tcg.c | 26 +++---
> tcg/tcg.h | 8
> 2 files changed, 19 insertions(+), 15 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@au
rming an abort() which can happen all the time in an
assert which can happen only when TCG debug is enabled. Is it really
something we want? Maybe we should add a tcg_assert() function.
Otherwise it looks fine.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
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On 2015-12-17 12:00, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/tcg.c | 10 --
> tcg/tcg.h | 5 -
> 2 files changed, 15 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
On 2015-12-17 12:00, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/tcg.c | 48 +++-
> 1 file changed, 23 insertions(+), 25 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net
On 2015-12-17 12:00, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/tcg.c | 55 ---
> 1 file changed, 28 insertions(+), 27 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel
On 2015-12-17 12:00, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/tcg.c | 16 +++-
> 1 file changed, 7 insertions(+), 9 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
On 2015-12-10 07:31, Richard Henderson wrote:
> On 12/10/2015 12:02 AM, Aurelien Jarno wrote:
> >Note: I don't really get the reason for the current 16MB limit. With the
> >standard branch instructions the offset is coded on 24 bits, but shifted
> >right by 2, which should gi
ail.com>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
include/exec/exec-all.h | 24
tcg/arm/tcg-target.c| 8 +++-
translate-all.c | 2 --
3 files changed, 7 insertions(+), 27 deletions(-)
Note: I don't really get the reason fo
TB linking.
> Any suggest for this issue?
I already posted a patch a long time ago to remove the 16MB limit on ARM
hosts:
http://lists.gnu.org/archive/html/qemu-devel/2012-10/msg01684.html
However as you can see in the thread, it has been rejected as it doesn't
not bring improvement in all
On 2015-12-08 11:51, Laurent Desnogues wrote:
> Hello,
>
> On Tue, Dec 8, 2015 at 11:39 AM, Aurelien Jarno <aurel...@aurel32.net> wrote:
> [...]
> > I already posted a patch a long time ago to remove the 16MB limit on ARM
> > hosts:
> >
> > http://lis
cvt.s.d and cvt.d.s are FP operations and thus need to convert input
sNaN into corresponding qNaN. Explicitely use the floatXX_maybe_silence_nan
functions for that as the floatXX_to_floatXX functions do not do that.
Cc: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Aurelien Jarno
On 2015-12-03 13:19, Aurelien Jarno wrote:
> On 2015-12-02 10:36, Richard Henderson wrote:
> > On 12/01/2015 08:32 AM, Aurelien Jarno wrote:
> > >On 2015-12-01 08:19, Richard Henderson wrote:
> > >>If there are a lot of guest memory ops in the TB, the
On 2015-12-02 10:36, Richard Henderson wrote:
> On 12/01/2015 08:32 AM, Aurelien Jarno wrote:
> >On 2015-12-01 08:19, Richard Henderson wrote:
> >>If there are a lot of guest memory ops in the TB, the amount of
> >>code generated by tcg_out_tb_finalize could be well mor
On 2015-12-01 08:19, Richard Henderson wrote:
> If there are a lot of guest memory ops in the TB, the amount of
> code generated by tcg_out_tb_finalize could be well more than 1k.
> In the short term, increase the reservation larger than any TB
> seen in practice.
>
> Reported-
In the short term, increase the reservation larger than any TB
> > seen in practice.
> >
> > Reported-by: Aurelien Jarno <aurel...@aurel32.net>
> > Signed-off-by: Richard Henderson <r...@twiddle.net>
> > ---
> >
> > Reported and discussed with Aurelien on
On 2015-12-01 17:34, Aurelien Jarno wrote:
> On 2015-12-01 16:28, Peter Maydell wrote:
> > On 1 December 2015 at 16:19, Richard Henderson <r...@twiddle.net> wrote:
> > > If there are a lot of guest memory ops in the TB, the amount of
> > > code generated by tcg_o
t didn't update the PC initialisation for KVM to use
> ram_low_size. Fix that now.
>
> Fixes: 71c199c81d29 ("mips_malta: provide ememsize env variable to kernels")
> Signed-off-by: James Hogan <james.ho...@imgtec.com>
> Cc: Paul Burton <paul.bur...@imgtec.com>
&g
checks
> that may break a program that uses these instructions.
That is correct. That said these instructions do require at least a
MIPS32R2 or a MIPS64R1 CPU. I guess we should add these checks now that
check_cop1x do not guard them anymore.
--
Aurelien Jarno GPG:
ng it into mul_i32 and
> mul*h_i32 TCG ops.
>
> Signed-off-by: James Hogan <james.ho...@imgtec.com>
> Reviewed-by: Richard Henderson <r...@twiddle.net>
> Cc: Aurelien Jarno <aurel...@aurel32.net>
> ---
> Changes in v2:
> - Use a common OPC_MUL definition. us
by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/tcg-opc.h | 12
> 1 file changed, 4 insertions(+), 8 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Note that it will conflict with the "tcg: Rename debug_insn_start to
insn_start" p
; prediction stack hardware which may detect only particular encodings of
> the return instruction.
>
> Signed-off-by: James Hogan <james.ho...@imgtec.com>
> Reviewed-by: Richard Henderson <r...@twiddle.net>
> Cc: Aurelien Jarno <aurel...@aurel32.net>
> ---
> Changes
Reviewed-by: Richard Henderson <r...@twiddle.net>
> Cc: Aurelien Jarno <aurel...@aurel32.net>
> ---
> Changes in v3:
> - Whoops. Fix jr.hb r6 encoding (Leon)
> ---
> disas/mips.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Aurelien Jarno <aurel...@au
usy, could you take them? (at the moment I don't have
> anything handy to test the mips backend).
Sorry I have been indeed a bit busy. I can send a pull request in the
next days. As you prefer.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
Z ret, v1, c1
> OR ret, ret, TMP1
>
> Which does the following:
> ret = cond ? v1 : v2
>
> Signed-off-by: James Hogan <james.ho...@imgtec.com>
> Cc: Richard Henderson <r...@twiddle.net>
> Cc: Aurelien Jarno <aurel...@aurel32.net>
> ---
&g
s.ho...@imgtec.com>
> Reviewed-by: Richard Henderson <r...@twiddle.net>
> Cc: Aurelien Jarno <aurel...@aurel32.net>
> ---
> tcg/mips/tcg-target.h | 7 +++
> 1 file changed, 7 insertions(+)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
> diff --gi
On 2015-10-02 17:50, Yongbok Kim wrote:
> Add enum for BREAK32
>
> Signed-off-by: Yongbok Kim <yongbok@imgtec.com>
> ---
> target-mips/translate.c |3 ++-
> 1 files changed, 2 insertions(+), 1 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel
_init(_ctx.tb_ctx.tb_lock);
> }
>
> @@ -717,8 +709,6 @@ void tcg_exec_init(unsigned long tb_size)
> {
> cpu_gen_init();
> code_gen_alloc(tb_size);
> -tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer;
> -tcg_register_jit(tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_buffer_size);
> page_init();
> #if defined(CONFIG_SOFTMMU)
> /* There's no guest base to take into account, so go ahead and
Otherwise the patch looks fine to me.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
hout any issue, except on SH4. I realized SH4
broken in some rare cases, but not directly by this patchset. There is
an issue when a delay slot is split in two parts when reaching the
maximum number of TCG ops. Given the patch 2 adds more TCG ops, it
triggers more often. It is already possible to trigger
terpreted as a bug in the guest code.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
| 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
target-unicore32/translate.c | 24 ++--
> target-xtensa/translate.c | 25 +++------
> 18 files changed, 160 insertions(+), 239 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
f the RAM, as the two do not seem that related. It
happens that at some point we don't really increases performances
anymore, and always defining it as 32MB might actually be a good idea.
Personally I am using a patch that limits it to 128MB.
--
Aurelien Jarno GPG: 4096R/1DDD8
te_to_opc(env, tb, data);
>
> #ifdef CONFIG_PROFILER
> -s->restore_time += profile_getclock() - ti;
> -s->restore_count++;
> +tcg_ctx.restore_time += profile_getclock() - ti;
> +tcg_ctx.restore_count++;
> #endif
> return 0;
> }
> @@ -969,7 +1035,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
> tb_page_addr_t phys_pc, phys_page2;
> target_ulong virt_page2;
> tcg_insn_unit *gen_code_buf;
> -int gen_code_size;
> +int gen_code_size, search_size;
> #ifdef CONFIG_PROFILER
> int64_t ti;
> #endif
> @@ -1025,11 +1091,13 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
> #endif
>
> gen_code_size = tcg_gen_code(_ctx, gen_code_buf);
> +search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size);
>
> #ifdef CONFIG_PROFILER
> tcg_ctx.code_time += profile_getclock();
> tcg_ctx.code_in_len += tb->size;
> tcg_ctx.code_out_len += gen_code_size;
> +tcg_ctx.search_out_len += search_size;
> #endif
>
> #ifdef DEBUG_DISAS
> @@ -1041,8 +1109,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
> }
> #endif
>
> -tcg_ctx.code_gen_ptr = (void *)(((uintptr_t)gen_code_buf +
> -gen_code_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
> +tcg_ctx.code_gen_ptr = (void *)
> +ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size,
> + CODE_GEN_ALIGN);
>
> /* check next page if needed */
> virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
If you fix the coding style issue I mentioned above, you get:
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
re32/translate.c | 44 ---
> target-xtensa/translate.c | 39 ---
> tcg/tcg.h | 4
> 22 files changed, 90 insertions(+), 736 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
> ---
> tcg/tcg.c | 59 +++
> tcg/tcg.h | 2 --
> 2 files changed, 19 insertions(+), 42 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
--
> target-unicore32/translate.c | 5 +++--
> target-xtensa/translate.c | 5 +++--
> tcg/tcg.c | 11 ++-
> tcg/tcg.h | 2 ++
> translate-all.c | 2 +-
> 22 files changed, 79 insertions(+), 66 deletions(-)
Revi
t; translate-all.c | 131
> ++--
> 2 files changed, 59 insertions(+), 74 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
target-ppc/cpu.h| 1 -
> target-s390x/cpu.h | 1 -
> target-sh4/cpu.h| 1 -
> target-sparc/cpu.h | 1 -
> target-tilegx/cpu.h | 1 -
> target-xtensa/cpu.h | 1 -
> 16 files changed, 16 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net&g
ns(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ell <peter.mayd...@linaro.org>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target-sparc/translate.c | 19 ++-
> 1 file changed, 10 insertions(+), 9 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
.net>
> ---
> target-sparc/translate.c | 21 ++---
> 1 file changed, 10 insertions(+), 11 deletions(-)
>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
derson <r...@twiddle.net>
> ---
> target-sparc/translate.c | 55
>
> 1 file changed, 28 insertions(+), 27 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
TCG_MAX_INSNS;
> +}
>
> if (in_superpage(, pc_start)) {
> pc_mask = (1ULL << 41) - 1;
Given we have the same pattern in all targets, I do wonder if it
wouldn't be better to just setup (cflags & CF_COUNT_MASK) to
TCG_MAX_INSNS instead of 0
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