This remove the corresponding error messages in TCG mode, and allow to
simplify the s390_assign_subch_ioeventfd() function.
CC: Cornelia Huck
Cc: Christian Borntraeger
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
hw/s390x/virtio-ccw.c | 4
target-s390x/cpu.h| 6 +-
2
The I/O-Interruption Subclass field corresponds to bits 2 to 5 (BE
notation) of the Interruption-Identification Word. The value should
be shift by 27 instead of 24.
Cc: Christian Borntraeger
Cc: Cornelia Huck
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-s390x/ioinst.h | 2
env->io_index[] should be set to -1 during CPU reset to mark the
I/O interrupt queue as empty.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-s390x/cpu.c b/target-s390x/cp
-off-by: Aurelien Jarno
---
target-s390x/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index cc9cc37..ba7a887 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -131,6 +131,7 @@ static void s390_cpu_initial_reset(CPUState *s)
if
the last patch of the
series. However a few fixes are needed first to make the s390-ccw
machine fully functional under TCG.
Alexander Graf (2):
s390/ioinst: fix endianness in ioinst_schib_valid
target-s390x: wire up I/O instructions in TCG mode
Aurelien Jarno (8):
s390/ioinst: fix
x27;t set the value of general
register 2 to 0 as in the current code. We also need to exit the CPU
loop after a reset, which means a new PSW.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.h | 2 +-
target-s390x/insn-data.def | 2 +-
target-
From: Alexander Graf
The ioinst_schib_valid gets a SCHIB in guest endianness, we should
byteswap the fields we access.
Cc: Christian Borntraeger
Cc: Cornelia Huck
Signed-off-by: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-s390x/ioinst.c | 6 +++---
1 file changed, 3 insertions
mips32_op = OPC_TLBINV;
> +goto do_cp0;
> +case TLBINVF:
> +mips32_op = OPC_TLBINVF;
> +goto do_cp0;
> case WAIT:
> mips32_op = OPC_WAIT;
> goto do_cp0;
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
t, rs);
> +gen_store_srsgpr(rs, rt);
> break;
> default:
> goto pool32axf_invalid;
Reviewed-by: Aurelien Jarno
Note however that your subject should be {RD,WR}PGPR to correctly match
both instructions.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
nelia Huck
Cc: Christian Borntraeger
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
pc-bios/s390-ccw/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/pc-bios/s390-ccw/Makefile b/pc-bios/s390-ccw/Makefile
index 009bb8d..746603a 100644
--- a/pc-bios/s390-ccw/Mak
On 2015-06-15 10:48, Pavel Dovgaluk wrote:
> > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > On 2015-06-15 07:53, Pavel Dovgaluk wrote:
> > > > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > > > On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
On 2015-06-15 10:39, Pavel Dovgaluk wrote:
> > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > On 2015-06-15 07:53, Pavel Dovgaluk wrote:
> > > > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > > > On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
On 2015-06-15 07:53, Pavel Dovgaluk wrote:
> > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
> > > This patch fixes exception handling in MIPS.
> > > MIPS instructions generate several types of exceptions.
> &g
lem in terms of tracability and trust
> >> of the code we're shipping to people... We must fix this for 2.4
> >> (or ideally ASAP) I think.
> >
> > Okay. I will set up a cronjob to use git-svn to grab the latest
> > OpenBIOS from upstream soon.
>
>
r the PER
exception immediately after.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h | 3 +++
target-s390x/helper.c | 54 ++
target-s390x/helper.h | 1 +
target-s390x/misc_help
low core memory when a program exception
happens.
Cc: Richard Henderson
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.c | 6 ++
target-s390x/cpu.h | 12 +++-
target-s390x/helper.c| 1 +
target-s390x/translate.c | 29
.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.h | 1 +
target-s390x/misc_helper.c | 8
target-s390x/translate.c | 8
3 files changed, 17 insertions(+)
diff --git a/target-s390x/helper.h b/target-s390x/helper.h
index 8d89cff..f7
helper.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/misc_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index ca3aabe..241f82e 100644
--- a/target-s390x/misc_helper.c
+++ b
er as the C memmove
function.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/mem_helper.c | 84 +++
1 file changed, 27 insertions(+), 57 deletions(-)
diff --git a/target-s390x/mem_helper.c b/target-
This PER event happens each time the STURA or STURG instructions are
used. As they use helpers, we can just save the event in the PER code
there, if enabled.
Cc: Richard Henderson
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-s390x/mem_helper.c | 16
1 file
case, don't try to retranslate the code, but
assume that the CPU state (and especially the program counter) has been
saved before calling the helper. Then invalidate the TB based on this
address.
Signed-off-by: Aurelien Jarno
---
translate-all.c | 20 +++-
1 file change
s using goto_tb, as we have disabled
them in the previous patch.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.h | 1 +
target-s390x/misc_helper.c | 11 +++
target-s390x/translate.c | 39 +++
3 fi
This function checks if an address is in between the PER starting
address and the PER ending address, taking care of a possible
address range loop.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h | 11 +++
1 file changed, 11 insertions
ing, breakpoints and watchpoints.
Aurelien Jarno (15):
softmmu: provide tlb_vaddr_to_host function for user mode
target-s390x: function to adjust the length wrt page boundary
target-s390x: mvc_fast_memset: access memory through softmmu
target-s390x: mvc_fast_memmove: access memory through softmmu
To avoid to many #ifdef in target code, provide a tlb_vaddr_to_host for
both user and softmmu modes. In the first case the function always
succeed and just call the g2h function.
Signed-off-by: Aurelien Jarno
---
include/exec/cpu_ldst.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions
trigger the watchpoint. For now we assume it comes
from the default ASC.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu-qom.h| 1 +
target-s390x/cpu.c| 1 +
target-s390x/cpu.h| 1 +
target-s390x/helper.c | 75
This function returns the ATMID field that is stored in the
per_perc_atmid lowcore entry.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h | 12
1 file changed, 12 insertions(+)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
performances improvements.
At the same time change the name of the function to fast_memset as it's
not specific to mvc and use the same argument order as the C memset
function.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/mem_helper.c
This patch adds a function to adjust the length of a transfer so that
it doesn't cross a page boundary in softmmu mode. It does nothing in
user mode.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/mem_helper.c | 11 +++
1 file change
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h | 16
1 file changed, 16 insertions(+)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 584e74b..4ff3f5c 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -364,6
> 7 files changed, 166 insertions(+), 134 deletions(-)
The whole series is:
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-06-12 16:12, Riku Voipio wrote:
> On Thursday, June 4, 2015 10:55:12 PM EEST, Aurelien Jarno wrote:
> >On 2015-06-02 21:50, Richard Henderson wrote:
> >>On 05/24/2015 03:51 PM, Aurelien Jarno wrote: ...
>
> >I have added them in my sh4-next branch [1], they
In preparation for more efficient setting of this field.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 14 +++-
target-sh4/gdbstub.c | 4 +-
target-sh4/helper.c| 2 +-
target-sh4/op_helper.c | 32 ++--
target-sh4/translate.c | 213
Splitting Q and M out of SR, it's possible to optimize div1 by using
TCG code instead of an helper.
At the same time removed the now unused gen_copy_bit_i32 function.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 12 +++--
target-sh4/hel
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.c | 3 +-
target-sh4/cpu.h | 30 ++--
target-sh4/gdbstub.c
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 44d0e94..e8b9217 100644
--- a/target-sh4/translate.c
+++ b/target-sh4
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index bcdf4f3..5c90fe3 100644
--- a/target-sh4/translate.c
+++ b/target-sh4
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index e8b9217..28259f9 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -18,7 +18,6
From: Richard Henderson
Only exposing FPU and LLSC as the only features
supported by the translator.
Signed-off-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
linux-user/elfload.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/linux-user/elfload.c
The documentation is clear to use 16-bit accesses for all registers.
Signed-off-by: Aurelien Jarno
---
hw/sh4/r2d.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 4221060..5e22ed7 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index b8abfd5..9ab3ba0 100644
--- a/target-sh4/translate.c
+++ b/target-sh4
ssor style
----
Aurelien Jarno (9):
sh4/r2d: convert to new MMIO accessor style
target-sh4: use bit number for SR constants
target-sh4: Split out T from SR
target-sh4: optimize addc using add2
target-sh4: optimize subc
From: Richard Henderson
Signed-off-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
linux-user/main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/main.c b/linux-user/main.c
index 6989b82..a0d3e58 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3925,6
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 5c90fe3..b8abfd5 100644
--- a/target-sh4/translate.c
+++ b/target
supposed to adjust the length if
needed, but does so only if iommu_ops is defined. I therefore wonder if
you therefore shouldn't model this DMA translation tables by using IOMMU
ops instead of subregions.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
}
> @@ -1684,6 +1685,7 @@ generate_exception (DisasContext *ctx, int excp)
> {
> save_cpu_state(ctx, 1);
> gen_helper_0e0i(raise_exception, excp);
> +ctx->bstate = BS_STOP;
> }
>
Why do we need to stop the translation here? The exception might be
conditional (for e
; respectively.
>
> The series applies on top of the Config5.FRE patches.
>
> Regards,
> Leon
The whole series is:
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
20 +++-
> target-mips/translate_init.c | 4 +++-
> 6 files changed, 32 insertions(+), 7 deletions(-)
Reviewed-by: Aurelien Jarno
As a side note, I have seen that you have added a check for MIPS2 to the
ERET instruction. This is correct, but given in practice we don't
emulate any M
Most of the calls to tcg_opt_gen_mov are preceeded by a test to check if
the source temp is a constant. Fold that into the tcg_opt_gen_mov
function.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/optimize.c | 89 --
1 file
cpu_fprintf(f, "Config0 0x%08x Config1 0x%08x LLAddr 0x"
> TARGET_FMT_lx "\n",
> +cpu_fprintf(f, "Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
> +PRIx64 "\n",
> env->CP0_Config0, env->CP0_Config1, env->lladdr);
> cpu_fprintf(f, "Config2 0x%08x Config3 0x%08x\n",
> env->CP0_Config2, env->CP0_Config3);
> @@ -19547,7 +19548,7 @@ void cpu_state_reset(CPUMIPSState *env)
> }
> #endif
> env->PABITS = env->cpu_model->PABITS;
> -env->PAMask = (target_ulong)((1ULL << env->cpu_model->PABITS) - 1);
> +env->PAMask = (1ULL << env->cpu_model->PABITS) - 1;
> env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
> env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
> env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-06-04 14:07, Richard Henderson wrote:
> On 06/04/2015 12:53 PM, Aurelien Jarno wrote:
> > +
> > static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args,
> > TCGArg dst, TCGArg src)
> > {
> > +if (t
We can get the opcode using the TCGOp pointer. It needs to be
dereferenced, but it's anyway done a few lines below to write
the new value.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/optimize.c | 40
1 file changed, 20 insertions(+
On 2015-06-02 21:50, Richard Henderson wrote:
> On 05/24/2015 03:51 PM, Aurelien Jarno wrote:
> >On 2015-05-23 15:06, Richard Henderson wrote:
> >>As reported by Rich the other day. As I don't have a user-land
> >>binary that depends on this, I merely note that
Most of the calls to tcg_opt_gen_mov are preceeded by a test to check if
the source temp is a constant. Fold that into the tcg_opt_gen_mov
function.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/optimize.c | 89 --
1 file
Each call to tcg_opt_gen_mov is preceeded by a test to check if the
source and destination temps are copies. Fold that into the
tcg_opt_gen_mov function.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/optimize.c | 27 +--
1 file changed, 9 insertions(+), 18
The tcg_constant_folding folding ends up doing all the optimizations
(which is a good thing to avoid looping on all ops multiple time), so
make it clear and just rename it tcg_optimize.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/optimize.c | 7 +--
1 file changed, 1
We can get the opcode using the TCGOp pointer. It needs to be
dereferenced, but it's anyway done a few lines below to write
the new value.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/optimize.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --
omments to explain the tricks used in div1
Changes v1 -> v2:
- rebased
- added last patch
Aurelien Jarno (8):
target-sh4: use bit number for SR constants
target-sh4: Split out T from SR
target-sh4: optimize addc using add2
target-sh4: optimize subc using sub2
target-sh4: optimize
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.c | 3 +-
target-sh4/cpu.h | 30 ++--
target-sh4/gdbstub.c
This patch series does some small cleanups to make the optimizer code
more readable. It doesn't bring any functional change.
Aurelien Jarno (5):
tcg/optimize: remove opc argument from tcg_opt_gen_movi
tcg/optimize: remove opc argument from tcg_opt_gen_mov
tcg/optimize: fold temp c
Splitting Q and M out of SR, it's possible to optimize div1 by using
TCG code instead of an helper.
At the same time removed the now unused gen_copy_bit_i32 function.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 12 +++--
target-sh4/hel
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 5c90fe3..b8abfd5 100644
--- a/target-sh4/translate.c
+++ b/target
In preparation for more efficient setting of this field.
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 14 +++-
target-sh4/gdbstub.c | 4 +-
target-sh4/helper.c| 2 +-
target-sh4/op_helper.c | 32 ++--
target-sh4/translate.c | 213
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index b8abfd5..9ab3ba0 100644
--- a/target-sh4/translate.c
+++ b/target-sh4
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 5453a86..4c75575 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -18,7 +18,6
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 44d0e94..5453a86 100644
--- a/target-sh4/translate.c
+++ b/target
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index bcdf4f3..5c90fe3 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -644,15 +644,12
Signed-off-by: Aurelien Jarno
---
tcg/tcg.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 8b43bbb..c5e2ce9 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1998,6 +1998,16 @@ static void tcg_reg_alloc_op(TCGContext *s,
if (!IS_DEAD_ARG(i
This avoid emitting a move
and using a register for the movcond instruction when used as "move if
true" on x86-64. This might bring more improvements on RISC TCG targets
which don't have outputs aliased to inputs.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
triggered by the second one.
Aurelien Jarno (2):
tcg: fix register allocation with two aliased dead inputs
tcg: fix dead computation for repeated input arguments
tcg/tcg.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
--
2.1.4
B7_4 + sr_t_in
>adc sr_t_out, 0 // cout(B11_8 + B7_4 + sr_t_in)
add %ebp, %r13d // %ebp is now B11_8
adc %ebx, %r12d // %ebx is now cpu_sr_t
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-06-02 21:25, Aurelien Jarno wrote:
> The following changes since commit f5790c3bc81702c98c7ddadedb274758cff8cbe7:
>
> Revert "target-alpha: Add vector implementation for CMPBGE" (2015-05-22
> 12:30:13 +0100)
>
> are available in the git repository at:
lt;= ram_size) {
> +if (*raddr < ram_size) {
> sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
> if (*flags & PAGE_READ) {
> *sk |= SK_R;
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
Besides RISBHG and RISBLG, all high-word instructions are not
implemented. Fix that.
Cc: Alexander Graf
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 47 ++
target-s390x/translate.c | 51
The documentation is clear to use 16-bit accesses for all registers.
Signed-off-by: Aurelien Jarno
---
hw/sh4/r2d.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 4221060..5e22ed7 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
af
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 10 ++
target-s390x/translate.c | 80 --
2 files changed, 81 insertions(+), 9 deletions(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn
This complete the floating point support sign handling facility.
Cc: Alexander Graf
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index
This is needed to pass the gcc.c-torture/execute/ieee/20010114-2.c test
in the gcc testsuite.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/fpu_helper.c | 31 +++
target-s390x/helper.h | 3 +++
target-s390x/insn
represents (length - 1).
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/mem_helper.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 04500ab..b4e5d44 100644
--- a/target-s390x
uot;
- fixed FIXBR argument in patch 6
- add specification exception for odd r1 in patch 8
- pass more values as arguments in patch 8
- add the 4 last patches
Aurelien Jarno (16):
target-s390x: fix exception for invalid operation code
target-s390x: fix CLGIT instruction
target-s390x: cha
0x0001 to generate a trap.
Cc: Alexander Graf
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index d508bc2..c7ebd21 100644
--- a/target
: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 6b47766..90d273c 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -112,7
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/mem_helper.c | 53 ++-
1 file changed, 20 insertions(+), 33 deletions(-)
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 30a2a6d..04500ab 100644
--- a/target
It is part of the basic zArchitecture instructions.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2 ++
target-s390x/mem_helper.c | 39 +++
target-s390x
STORE CLOCK FAST should be in the SCF facility.
Cc: Alexander Graf
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index
Change to match the PoP. In practice both format RIL-a and RIL-b have
the same fields. They differ on the way we decode the fields, and it's
done correctly in QEMU.
Cc: Alexander Graf
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 4 ++--
1
Use constants to define the MMU indexes, and add a function to do
the reverse conversion of cpu_mmu_index.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git
RISBGN is the same as RISBG, but without setting the condition code.
CLT and CLGT are the same as CLRT and CLGRT, but using memory for the
second operand.
Cc: Alexander Graf
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 3 +++
target-s390x
It belongs to the DFP rounding facility.
Cc: Alexander Graf
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index c09f8a1
The COMPARE LOGICAL IMMEDIATE AND TRAP instruction should compare the
numbers as unsigned, as its name implies.
Cc: Alexander Graf
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
It is part of the basic zArchitecture instructions. Allow it to be call
from EXECUTE.
Cc: Alexander Graf
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2 ++
target-s390x/mem_helper.c | 24
--- a/tests/endianness-test.c
> +++ b/tests/endianness-test.c
> @@ -31,8 +31,6 @@ struct TestCase {
>
> static const TestCase test_cases[] = {
> { "i386", "pc", -1 },
> -{ "mips", "magnum", 0x9000, .bswap = true },
> -{ "mips", "pica61", 0x9000, .bswap = true },
> { "mips", "mips", 0x1400, .bswap = true },
> { "mips", "malta", 0x1000, .bswap = true },
> { "mips64", "magnum", 0x9000, .bswap = true },
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-06-02 13:58, Richard Henderson wrote:
> On 06/02/2015 01:10 PM, Aurelien Jarno wrote:
> > It looks like we have to go through the MMIO functions to get the
> > TLB_NOTDIRTY bit cleaned correctly. This is something we don't want for
> > probe_write, so we def
On 2015-06-02 13:54, Richard Henderson wrote:
> On 06/02/2015 04:26 AM, Aurelien Jarno wrote:
> > int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> > -CPUTLBEntry *tlbentry = &env->tlb_table[mmu_idx][index];
> > +CPUTLBEntry *tl
On 2015-06-03 09:09, Aurelien Jarno wrote:
> On 2015-06-02 19:01, Christopher Covington wrote:
> > Hi Aurelien,
> >
> > On 06/01/2015 05:29 PM, Aurelien Jarno wrote:
> > > Use the bit number for SR constants instead of using a bit mask. This
> > > make
On 2015-06-02 19:01, Christopher Covington wrote:
> Hi Aurelien,
>
> On 06/01/2015 05:29 PM, Aurelien Jarno wrote:
> > Use the bit number for SR constants instead of using a bit mask. This
> > make possible to also use the constants for shifts.
> >
> > Reviewed-
On 2015-06-02 13:26, Aurelien Jarno wrote:
> The softmmu code already provides a tlb_vaddr_to_host function, which
> returns the host address corresponding to a guest virtual address,
> *if it is already in the QEMU MMU TLB*.
>
> This patch is an attempt to have a function which
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index f9bc24c..a7a8f39 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -642,17 +642,15
In preparation for more efficient setting of this field.
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 14 +++-
target-sh4/gdbstub.c | 4 +-
target-sh4/helper.c| 2 +-
target-sh4/op_helper.c | 32 ++--
target-sh4/translate.c | 212
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.c | 3 +-
target-sh4/cpu.h | 30 ++--
target-sh4/gdbstub.c
901 - 1000 of 4131 matches
Mail list logo
