On Wed, 31 Jul 2024 09:57:19 +0100
Jonathan Cameron wrote:
> On Wed, 31 Jul 2024 09:11:33 +0200
> Mauro Carvalho Chehab wrote:
>
> > Em Tue, 30 Jul 2024 13:17:09 +0200
> > Igor Mammedov escreveu:
> >
> > > On Mon, 22 Jul 2024 08:45:56 +020
On Mon, 29 Jul 2024 19:42:39 +0700
Manish wrote:
> On 29/07/24 7:18 pm, Igor Mammedov wrote:
> > !---|
> >CAUTION: External Email
> >
> > |
On Tue, 30 Jul 2024 09:29:37 +0100
Peter Maydell wrote:
> On Tue, 30 Jul 2024 at 08:26, Igor Mammedov wrote:
> >
> > On Mon, 22 Jul 2024 08:45:53 +0200
> > Mauro Carvalho Chehab wrote:
> >
> > > Having magic numbers inside the code is not a good idea, as
On Mon, 22 Jul 2024 08:45:58 +0200
Mauro Carvalho Chehab wrote:
> There is one reference to ACPI 4.0 and several references
> to ACPI 6.x versions.
>
> Update them to point to ACPI 6.5 whenever possible.
when it comes to APCI doc comments, they should point to
the 1st (earliest) revision that p
On Mon, 22 Jul 2024 08:45:56 +0200
Mauro Carvalho Chehab wrote:
that's quite a bit of code that in 99% won't ever be used
(assuming error injection testing scenario),
not to mention it's a hw depended one and governed by different specs.
Essentially we would need to create _whole_ lot of QAPI
co
On Mon, 22 Jul 2024 08:45:55 +0200
Mauro Carvalho Chehab wrote:
> From: Jonathan Cameron
>
> Add error notification to GHES v2 using the GPIO source.
>
> Signed-off-by: Jonathan Cameron
> Signed-off-by: Mauro Carvalho Chehab
> ---
> hw/acpi/ghes.c | 8 ++--
> include/hw/acpi/ghe
On Mon, 22 Jul 2024 08:45:54 +0200
Mauro Carvalho Chehab wrote:
> From: Jonathan Cameron
>
> Creates a GED - Generic Event Device and set a GPIO to
> be used or error injection.
QEMU already has GED device, so question is why it wasn't
used for event delivery?
I nutshell, I'd really prefer thi
On Mon, 22 Jul 2024 08:45:53 +0200
Mauro Carvalho Chehab wrote:
> Having magic numbers inside the code is not a good idea, as it
> is error-prone. So, instead, create a macro with the number
> definition.
>
> Signed-off-by: Mauro Carvalho Chehab
> Reviewed-by: Jonathan Cameron
> ---
> hw/arm/
On Sat, 20 Jul 2024 16:28:25 -0400
Steven Sistare wrote:
> On 7/16/2024 5:19 AM, Igor Mammedov wrote:
> > On Sun, 30 Jun 2024 12:40:24 -0700
> > Steve Sistare wrote:
> >
> >> Allocate anonymous memory using mmap MAP_ANON or memfd_create depending
> >>
On Wed, 24 Jul 2024 23:00:13 +0800
Zhao Liu wrote:
> Hi Igor,
>
> On Wed, Jul 24, 2024 at 02:54:32PM +0200, Igor Mammedov wrote:
> > Date: Wed, 24 Jul 2024 14:54:32 +0200
> > From: Igor Mammedov
> > Subject: Re: [PATCH v1] target/i386: Always set leaf 0x1f
> >
ID 1558552
> Fixes: 08c3286822 ("accel/kvm: Extract common KVM vCPU {creation,parking}
> code")
> Reported-by: Peter Maydell
> Suggested-by: Peter Maydell
> Message-ID:
>
> Signed-off-by: Salil Mehta
Reviewed-by: Igor Mammedov
> ---
> accel/kvm/kvm-al
On Thu, 25 Jul 2024 04:30:42 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Jul 25, 2024 at 10:22:15AM +0200, Igor Mammedov wrote:
> > On Thu, 13 Jun 2024 18:30:15 +0100
> > Jiaxun Yang wrote:
> >
> > > Implement S3 and S4 sleep with ACP
On Wed, 24 Jul 2024 23:27:31 -0400
Yao Xingtao via wrote:
> Since the downstream port is not checked, two slots can be linked to
> a single port. However, this can prevent the driver from detecting the
> device properly.
>
> It is necessary to ensure that a downstream port is not linked more tha
On Thu, 13 Jun 2024 18:30:14 +0100
Jiaxun Yang wrote:
> Hi all,
>
> This series implemented S3 and S4 sleep for loongarch virt machine
> and microvm.
>
> For loongarch/virt a kernel patch is requried [1].
>
> [1]:
> https://lore.kernel.org/loongarch/20240613-loongarch64-sleep-v1-0-a245232af..
On Thu, 13 Jun 2024 18:30:16 +0100
Jiaxun Yang wrote:
> Wire up S3 and S4 sleep by setting relevant slp-typs bits for
> GED and generate _S3 and _S4 methods in acpi table.
>
> Signed-off-by: Jiaxun Yang
> ---
> hw/loongarch/acpi-build.c | 18 ++
> hw/loongarch/virt.c | 3
On Thu, 13 Jun 2024 18:30:15 +0100
Jiaxun Yang wrote:
> Implement S3 and S4 sleep with ACPI_GED_REG_SLEEP_CTL.SLP_TYP
> writes.
>
> Implement wakeup callback and WAK_STS register to inform guest
> about current states.
>
> All new functions are gated by "slp-typs" property, it is defaulted
> to
On Sat, 15 Jun 2024 09:45:48 +0800
maobibo wrote:
> On 2024/6/14 下午10:03, Daniel P. Berrangé wrote:
> > On Fri, Jun 14, 2024 at 01:17:39PM +0800, maobibo wrote:
> >>
> >>
> >> On 2024/6/14 下午12:27, Jiaxun Yang wrote:
> >>>
> >>>
> >>> 在2024年6月14日六月 上午4:32，maobibo写道：
> It is interesting
On Wed, 24 Jul 2024 12:13:28 +0100
John Levon wrote:
> On Wed, Jul 24, 2024 at 03:59:29PM +0530, Manish wrote:
>
> > > > Leaf 0x1f is superset of 0xb, so it makes sense to set 0x1f equivalent
> > > > to 0xb by default and workaround windows issue.>
> > > > This change adds a
> > > > new property
On Wed, 24 Jul 2024 07:52:26 +
"manish.mishra" wrote:
> From: Manish Mishra
>
> QEMU does not set 0x1f in case VM does not have extended CPU topology
> and expects guests to fallback to 0xb. Some versions of Windows does not
> like this behavior and expects this leaf to be populated. As a r
On Mon, 22 Jul 2024 10:18:59 +
"manish.mishra" wrote:
> QEMU does not set 0x1f in case VM does not have extended CPU topology
> and expects guests to fallback to 0xb. Some versions of windows i.e.
> windows 10, 11 does not like this behavior and expects this leaf to be
^^
On Mon, 22 Jul 2024 09:35:17 +0200
Thomas Huth wrote:
> On 16/07/2024 14.59, Igor Mammedov wrote:
> > CI often fails 'cross-i686-tci' job due to runner slowness
> > Log shows that test almost complete, with a few remaining
> > when bios-tables-test timeout hits
On Tue, 16 Jul 2024 11:43:00 +
Salil Mehta wrote:
> Hi Igor,
>
> > From: Igor Mammedov
> > Sent: Tuesday, July 16, 2024 10:52 AM
> > To: Salil Mehta
> >
> > On Tue, 16 Jul 2024 03:38:29 +
> > Salil Mehta wrote:
> >
> &g
Xianglai Li
> Tested-by: Miguel Luis
> Reviewed-by: Vishnu Pajjuri
> Tested-by: Zhao Liu
> Reviewed-by: Zhao Liu
I haven't tested it but looks fine to me,
it missing migration bits, but as long as there is no actual users
in this release it could be a patch on top later on.
Ac
On Tue, 16 Jul 2024 09:06:59 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Jul 16, 2024 at 02:59:30PM +0200, Igor Mammedov wrote:
> > CI often fails 'cross-i686-tci' job due to runner slowness
> > Log shows that test almost complete, with a few remaining
>
On Tue, 16 Jul 2024 16:28:07 +0200
Igor Mammedov wrote:
> On Tue, 16 Jul 2024 17:56:11 +0530
> Sunil V L wrote:
>
> > On Mon, Jul 15, 2024 at 02:43:52PM +0200, Igor Mammedov wrote:
> > > On Sun, 14 Jul 2024 03:46:36 -0400
> > > "Michael S. Tsirkin"
On Tue, 16 Jul 2024 17:56:11 +0530
Sunil V L wrote:
> On Mon, Jul 15, 2024 at 02:43:52PM +0200, Igor Mammedov wrote:
> > On Sun, 14 Jul 2024 03:46:36 -0400
> > "Michael S. Tsirkin" wrote:
> >
> > > On Fri, Jul 12, 2024 at 03:50:10PM +0200, Igor Mamme
.
stderr:
TAP parsing error: Too few tests run (expected 8, got 7)
At the same time overall job running time is only ~30 out of 1hr allowed.
Increase bios-tables-test instance timeout on 5min as a fix
for slow CI runners.
Signed-off-by: Igor Mammedov
---
tests/qtest/meson.build | 2 +-
1 file
number
> and Y is the INTx.
>
> GPEX is currently used by riscv, aarch64/virt and x86/microvm machines.
> So, this change will alter the DSDT for those systems.
>
> [1] - ACPI 5.1: 6.2.13.1 Example: Using _PRT to Describe PCI IRQ Routing
>
> Signed-off-by: Sunil V L
/acpi.adoc
this should point to text like in previous patch and not to commit
> (commit: 7bfa87e86ad5658283731207dbfc8ab3744d3265)
>
> Signed-off-by: Sunil V L
> Acked-by: Alistair Francis
with above fixed:
Reviewed-by: Igor Mammedov
> ---
> hw/riscv/virt-acpi-bu
n-isa/riscv-brs/blob/main/acpi.adoc
> (commit : 241575b3189c5d9e60b5e55e78cf0443092713bf)
in spec links 'See RVI ACPI IDs' and right below it 'additional guidance',
do lead nowhere hence do not clarify anything.
>
> Signed-off-by: Sunil V L
> Acked-by: Alistair
On Tue, 16 Jul 2024 03:38:29 +
Salil Mehta wrote:
> Hi Igor,
>
> On 15/07/2024 15:11, Igor Mammedov wrote:
> > On Mon, 15 Jul 2024 14:19:12 +
> > Salil Mehta wrote:
> >
> >>> From: qemu-arm-bounces+salil.mehta=huawei@nongnu.or
On Sun, 30 Jun 2024 12:40:24 -0700
Steve Sistare wrote:
> Allocate anonymous memory using mmap MAP_ANON or memfd_create depending
> on the value of the anon-alloc machine property. This affects
> memory-backend-ram objects, guest RAM created with the global -m option
> but without an associated
On Mon, 15 Jul 2024 14:19:12 +
Salil Mehta wrote:
> > From: qemu-arm-bounces+salil.mehta=huawei@nongnu.org > arm-bounces+salil.mehta=huawei@nongnu.org> On Behalf Of Salil
> > Mehta via
> > Sent: Monday, July 15, 2024 3:14 PM
> > To: Igo
On Fri, 12 Jul 2024 12:08:14 +0100
Jonathan Cameron wrote:
> These are very similar to the recently added Generic Initiators
> but instead of representing an initiator of memory traffic they
> represent an edge point beyond which may lie either targets or
> initiators. Here we add these ports su
On Fri, 12 Jul 2024 12:08:13 +0100
Jonathan Cameron wrote:
> Reduce the direct use of PCI internals inside ACPI table creation.
>
> Suggested-by: Igor Mammedov
> Tested-by: "Huang, Ying"
> Signed-off-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
> ---
> v
On Fri, 12 Jul 2024 12:08:12 +0100
Jonathan Cameron wrote:
> Rather than relying on PCI internals, use the new acpi_property
> to obtain the ACPI _UID values. These are still the same
> as the PCI Bus numbers so no functional change.
>
> Suggested-by: Igor Mammedov
> Teste
can be made completely independent of PCI internals.
>
> Suggested-by: Igor Mammedov
> Tested-by: "Huang, Ying"
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Igor Mammedov
> ---
> v5: Add missing property description.
> ---
> hw/pci-bridge/pci_expander_
> hw/acpi/pci.c file and header. If support for ACPI Device Handles is
> added in the future, perhaps this will be moved again.
>
> Also push the struct AcpiGenericInitiator down into the c file as not
> used outside pci.c.
>
> Suggested-by: Igor Mammedov
> Tested-by: "H
> hw/acpi/pci.c file and header. If support for ACPI Device Handles is
> added in the future, perhaps this will be moved again.
>
> Also push the struct AcpiGenericInitiator down into the c file as not
> used outside pci.c.
>
> Suggested-by: Igor Mammedov
> Tested-by: "H
qemu_open().
>
> Cc: David Hildenbrand
> Cc: Igor Mammedov
> Signed-off-by: Zhao Liu
Reviewed-by: Igor Mammedov
> ---
> backends/hostmem-epc.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/backends/hostmem-epc.c b/backends/hostmem-epc.c
On Mon, 15 Jul 2024 11:27:57 +
Salil Mehta wrote:
> Hi Michael,
>
> > From: Michael S. Tsirkin
> > Sent: Monday, July 15, 2024 12:13 PM
> > To: Salil Mehta
> >
> > On Sat, Jul 13, 2024 at 07:25:09PM +0100, Salil Mehta wrote:
> > > [Note: References are present at the last after th
On Sat, 13 Jul 2024 19:25:09 +0100
Salil Mehta wrote:
> [Note: References are present at the last after the revision history]
>
> Virtual CPU hotplug support is being added across various architectures
> [1][3].
> This series adds various code bits common across all architectures:
>
> 1. vCPU
ed-by: Miguel Luis
> Reviewed-by: Shaoqin Huang
> Reviewed-by: Vishnu Pajjuri
> Tested-by: Zhao Liu
Acked-by: Igor Mammedov
> ---
> gdbstub/gdbstub.c | 13 +
> hw/core/cpu-common.c | 4 +++-
> include/exec/gdbstub.h | 6 ++
> 3 files
gt;
> Co-developed-by: Keqian Zhu
> Signed-off-by: Keqian Zhu
> Signed-off-by: Salil Mehta
> Reviewed-by: Gavin Shan
> Tested-by: Vishnu Pajjuri
> Reviewed-by: Jonathan Cameron
> Tested-by: Xianglai Li
> Tested-by: Miguel Luis
> Reviewed-by: Shaoqin Huang
> Te
On Mon, 15 Jul 2024 14:49:25 +0200
Igor Mammedov wrote:
> On Sat, 13 Jul 2024 19:25:10 +0100
> Salil Mehta wrote:
>
> > KVM vCPU creation is done once during the vCPU realization when Qemu vCPU
> > thread
> > is spawned. This is common to all the architectures as
On Sat, 13 Jul 2024 19:25:12 +0100
Salil Mehta wrote:
> ACPI GED (as described in the ACPI 6.4 spec) uses an interrupt listed in the
> _CRS object of GED to intimate OSPM about an event. Later then demultiplexes
> the
> notified event by evaluating ACPI _EVT method to know the type of event. Use
off-by: Salil Mehta
> Reviewed-by: Jonathan Cameron
> Reviewed-by: Gavin Shan
> Tested-by: Vishnu Pajjuri
> Tested-by: Xianglai Li
> Tested-by: Miguel Luis
> Reviewed-by: Shaoqin Huang
> Tested-by: Zhao Liu
Reviewed-by: Igor Mammedov
> ---
> hw/acpi/generic
Reviewed-by: Alex Bennée
> Reviewed-by: Jonathan Cameron
> Reviewed-by: Gavin Shan
> Reviewed-by: David Hildenbrand
> Reviewed-by: Shaoqin Huang
> Tested-by: Vishnu Pajjuri
> Tested-by: Xianglai Li
> Tested-by: Miguel Luis
> Tested-by: Zhao Liu
> Revie
ishnu Pajjuri
> Reviewed-by: Jonathan Cameron
> Tested-by: Xianglai Li
> Tested-by: Miguel Luis
> Reviewed-by: Shaoqin Huang
> Reviewed-by: Vishnu Pajjuri
> Reviewed-by: Nicholas Piggin
> Tested-by: Zhao Liu
> Reviewed-by: Zhao Liu
> Reviewed-by:
On Sun, 14 Jul 2024 03:46:36 -0400
"Michael S. Tsirkin" wrote:
> On Fri, Jul 12, 2024 at 03:50:10PM +0200, Igor Mammedov wrote:
> > On Fri, 12 Jul 2024 13:51:04 +0100
> > Daniel P. Berrangé wrote:
> >
> > > On Fri, Jul 12, 2024 at 02:43:19PM +0200, I
with help of '-device' option[s] (pcdimm,nvdimm,...)
2) SMBIOS 3.1.0 7.18.5 Memory Device — Extended Size
PS:
* tested on 8Tb host with RHEL6 guest, which seems to parse
type 17 SMBIOS table entries correctly (according to 'dmidecode').
Signed-off-by: Igor Mammedov
---
v2:
On Fri, 12 Jul 2024 13:51:04 +0100
Daniel P. Berrangé wrote:
> On Fri, Jul 12, 2024 at 02:43:19PM +0200, Igor Mammedov wrote:
> > On Mon, 8 Jul 2024 17:17:32 +0530
> > Sunil V L wrote:
> >
> > > This series adds few updates to RISC-V ACPI namespace for virt pl
On Mon, 8 Jul 2024 17:17:32 +0530
Sunil V L wrote:
> This series adds few updates to RISC-V ACPI namespace for virt platform.
> Additionally, it has patches to enable ACPI table testing for RISC-V.
>
> 1) PCI Link devices need to be created outside the scope of the PCI root
> complex to ensure
path
> as well.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Sunil V L
Reviewed-by: Igor Mammedov
> ---
> tests/qtest/bios-tables-test.c | 14 --
> 1 file changed, 14 deletions(-)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-tes
On Mon, 8 Jul 2024 17:17:35 +0530
Sunil V L wrote:
> so that CI tests don't fail when those ACPI tables are updated in the
> next patch. This is as per the documentation in bios-tables-tests.c.
>
> Signed-off-by: Sunil V L
Reviewed-by: Igor Mammedov
> ---
> tests
On Mon, 8 Jul 2024 17:17:36 +0530
Sunil V L wrote:
> Currently, PCI link devices (PNP0C0F) are always created within the
> scope of the PCI root bridge. However, RISC-V needs these link devices
> to be created outside to ensure the probing order in the OS. This
> matches the example given in the
On Mon, 8 Jul 2024 17:17:34 +0530
Sunil V L wrote:
> The RISC-V BRS specification [1] requires NS16550 compatible UART to
> have the HID RSCV0003. So, update the HID for the UART.
>
> [1] - https://github.com/riscv-non-isa/riscv-brs
it point's repo with a bunch of files,
please make it easier
On Mon, 8 Jul 2024 17:17:33 +0530
Sunil V L wrote:
> PLIC and APLIC should be in namespace as well. So, add them using the
> defined HID.
>
> Signed-off-by: Sunil V L
> Acked-by: Alistair Francis
> ---
> hw/riscv/virt-acpi-build.c | 47 ++
> 1 file changed
On Mon, 8 Jul 2024 17:17:33 +0530
Sunil V L wrote:
> PLIC and APLIC should be in namespace as well. So, add them using the
> defined HID.
defined where? REader shouldn't be forced to go over all web to find
source. Cite it here.
>
> Signed-off-by: Sunil V L
> Acked-by: Alistair Francis
> --
On Thu, 11 Jul 2024 07:13:27 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Jul 11, 2024 at 09:48:22AM +0200, Igor Mammedov wrote:
> > Currently SMBIOS maximum memory device chunk is capped at 16Gb,
> > which is fine for the most cases (QEMU uses it to describe initial
>
On Tue, 2 Jul 2024 14:14:13 +0100
Jonathan Cameron wrote:
> Rather than relying on PCI internals, use the new acpi_property
> to obtain the ACPI _UID values. These are still the same
> as the PCI Bus numbers so no functional change.
>
> Suggested-by: Igor Mammedov
> Signe
can be made completely independent of PCI internals.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Jonathan Cameron
>
> ---
> v4: Generalize to all TYPE_PXB_BUS. The handling for primary root
> bridges is separate and doesn't overlap with this change.
> ---
&g
On Thu, 11 Jul 2024 13:53:31 +0200
Igor Mammedov wrote:
> On Tue, 2 Jul 2024 14:14:10 +0100
> Jonathan Cameron wrote:
>
> > Using a property allows us to hide the internal details of the PCI device
> > from the code to build a SRAT Generic Initiator Affinity Structur
> hw/acpi/pci.c file and header. If support for ACPI Device Handles is
> added in the future, perhaps this will be moved again.
>
> Also push the struct AcpiGenericInitiator down into the c file as not
> used outside pci.c.
>
> Suggested-by: Igor Mammedov
> Signed-off-by
On Tue, 2 Jul 2024 14:14:10 +0100
Jonathan Cameron wrote:
> Using a property allows us to hide the internal details of the PCI device
> from the code to build a SRAT Generic Initiator Affinity Structure with
> PCI Device Handle.
>
> Suggested-by: Igor Mammedov
> Signed-off-by
On Thu, 11 Jul 2024 09:43:46 +0100
Daniel P. Berrangé wrote:
> On Thu, Jul 11, 2024 at 09:48:22AM +0200, Igor Mammedov wrote:
> > Currently SMBIOS maximum memory device chunk is capped at 16Gb,
> > which is fine for the most cases (QEMU uses it to describe initial
> > RAM
On Thu, 11 Jul 2024 10:19:27 +0200
Philippe Mathieu-Daudé wrote:
> Hi Igor,
>
> On 11/7/24 09:48, Igor Mammedov wrote:
> > Currently SMBIOS maximum memory device chunk is capped at 16Gb,
> > which is fine for the most cases (QEMU uses it to describe initial
> > RAM (t
On Thu, 11 Jul 2024 03:29:40 +
Salil Mehta wrote:
> Hi Igor,
>
>
> On 06/07/2024 14:28, Igor Mammedov wrote:
> > On Fri, 7 Jun 2024 12:56:45 +0100
> > Salil Mehta wrote:
> >
> >> OSPM evaluates _EVT method to map the event. The CPU hotplug event
&
'
guest OS, either by fixing up the next machine type or
giving users a CLI option to customize it.
1) SMBIOS 3.1.0 7.18.5 Memory Device — Extended Size
PS:
* tested on 8Tb host with RHEL6 guest, which seems to parse
type 17 SMBIOS table entries correctly (according to 'dmidecode&#
On Mon, 8 Jul 2024 23:30:01 +
Salil Mehta wrote:
> Hi Igor,
>
> On 08/07/2024 13:32, Igor Mammedov wrote:
> > On Sat, 6 Jul 2024 15:43:01 +
> > Salil Mehta wrote:
> >
> >> Hi Igor,
> >> Thanks for taking out time to review.
> >
On Mon, 8 Jul 2024 05:32:28 +
Salil Mehta wrote:
> On 06/07/2024 14:45, Igor Mammedov wrote:
> > On Fri, 7 Jun 2024 12:56:49 +0100
> > Salil Mehta wrote:
> >
> >> GED interface is used by many hotplug events like memory hotplug, NVDIMM
> >> hotplug
On Mon, 8 Jul 2024 05:26:00 +
Salil Mehta wrote:
> On 06/07/2024 14:35, Igor Mammedov wrote:
> > On Fri, 7 Jun 2024 12:56:46 +0100
> > Salil Mehta wrote:
> >
> >> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO
> >> por
On Mon, 8 Jul 2024 05:21:06 +
Salil Mehta wrote:
> Hi Igor,
>
> On 06/07/2024 14:28, Igor Mammedov wrote:
> > On Fri, 7 Jun 2024 12:56:45 +0100
> > Salil Mehta wrote:
> >
> >> OSPM evaluates _EVT method to map the event. The CPU hotplug event
> >
On Mon, 8 Jul 2024 05:12:48 +
Salil Mehta wrote:
> On 06/07/2024 13:46, Igor Mammedov wrote:
> > On Fri, 7 Jun 2024 12:56:44 +0100
> > Salil Mehta wrote:
> >
> >> ACPI GED (as described in the ACPI 6.4 spec) uses an interrupt listed in
> >> the
&
On Sat, 6 Jul 2024 15:43:01 +
Salil Mehta wrote:
> Hi Igor,
> Thanks for taking out time to review.
>
> On Sat, Jul 6, 2024 at 1:12 PM Igor Mammedov wrote:
>
> > On Fri, 7 Jun 2024 12:56:42 +0100
> > Salil Mehta wrote:
> >
> > > KVM
and can cover all
> teh x86 case. Remove the one in host_cpu_realizefn().
>
> Signed-off-by: Xiaoyao Li
Reviewed-by: Igor Mammedov
> ---
> target/i386/host-cpu.c | 12 +---
> 1 file changed, 1 insertion(+), 11 deletions(-)
>
> diff --git a/target/i386/h
On Fri, 7 Jun 2024 12:56:49 +0100
Salil Mehta wrote:
> GED interface is used by many hotplug events like memory hotplug, NVDIMM
> hotplug
> and non-hotplug events like system power down event. Each of these can be
> selected using a bit in the 32 bit GED IO interface. A bit has been reserved
>
On Fri, 7 Jun 2024 12:56:48 +0100
Salil Mehta wrote:
> Add common function to help unregister the GDB register space. This shall be
> done in context to the CPU unrealization.
>
> Note: These are common functions exported to arch specific code. For example,
> for ARM this code is being referred
by: Vishnu Pajjuri
> Reviewed-by: Gavin Shan
> Tested-by: Xianglai Li
> Tested-by: Miguel Luis
> Reviewed-by: Shaoqin Huang
> Tested-by: Zhao Liu
Acked-by: Igor Mammedov
> ---
> include/exec/cpu-common.h | 8
> include/hw/core/cpu.h
On Fri, 7 Jun 2024 12:56:46 +0100
Salil Mehta wrote:
> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO port
> based and existing CPUs AML code assumes _CRS objects would evaluate to a
> system
> resource which describes IO Port address. But on ARM arch CPUs control
> de
On Fri, 7 Jun 2024 12:56:45 +0100
Salil Mehta wrote:
> OSPM evaluates _EVT method to map the event. The CPU hotplug event eventually
> results in start of the CPU scan. Scan figures out the CPU and the kind of
> event(plug/unplug) and notifies it back to the guest. Update the GED AML _EVT
> metho
On Fri, 7 Jun 2024 12:56:44 +0100
Salil Mehta wrote:
> ACPI GED (as described in the ACPI 6.4 spec) uses an interrupt listed in the
> _CRS object of GED to intimate OSPM about an event. Later then demultiplexes
> the
> notified event by evaluating ACPI _EVT method to know the type of event. Use
On Fri, 7 Jun 2024 12:56:43 +0100
Salil Mehta wrote:
> CPU ctrl-dev MMIO region length could be used in ACPI GED and various other
> architecture specific places. Move ACPI_CPU_HOTPLUG_REG_LEN macro to more
> appropriate common header file.
>
> Signed-off-by: Salil Mehta
> Reviewed-by: Alex Ben
On Fri, 7 Jun 2024 12:56:42 +0100
Salil Mehta wrote:
> KVM vCPU creation is done once during the vCPU realization when Qemu vCPU
> thread
> is spawned. This is common to all the architectures as of now.
>
> Hot-unplug of vCPU results in destruction of the vCPU object in QOM but the
> correspond
thout arch in the path.
we probably should remove fallback path lookup after series is merged.
it' fine to do it as a follow up patch.
>
> Signed-off-by: Sunil V L
> Acked-by: Alistair Francis
> Reviewed-by: Igor Mammedov
On Mon, 1 Jul 2024 14:27:50 +
"Gao,Shiyuan" wrote:
> > > > > If I want to use ACPI PCI hotplug in the pxb bridge, what else need
> > > > > to be done?
> > > >
> > > > does it have to be hotplug directly into pxb or
> > > > would be it be sufficient to have hotplug support
> > > > on pci-br
On Fri, 28 Jun 2024 15:34:58 +0100
Alex Bennée wrote:
> Alex Bennée writes:
>
> > Incorrect brace positions causes an unintended overflow on 32 bit
> > builds and shenanigans result.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413
> > Suggested-by: Mark Cave-Ayland
> > Sig
On Thu, 20 Jun 2024 17:03:16 +0100
Jonathan Cameron wrote:
> These are very similar to the recently added Generic Initiators
> but instead of representing an initiator of memory traffic they
> represent an edge point beyond which may lie either targets or
> initiators. Here we add these ports su
On Wed, 26 Jun 2024 17:53:52 +
Salil Mehta wrote:
> Hi Gavin,
>
> > From: Gavin Shan
> > Sent: Wednesday, June 26, 2024 5:13 AM
> > To: Salil Mehta ; Igor Mammedov
> >
> >
> > Hi Salil and Igor,
> >
> > On 6/26/24 9:51 AM
On Fri, 28 Jun 2024 03:04:28 +
"Gao,Shiyuan" wrote:
> > > that OS cannot get control of SHPC hotplug and hotplug device to
> > > the PCI bridge will fail when we use SHPC Native type:
> > >
> > > [3.336059] shpchp :00:03.0: Requesting control of SHPC hotplug via
> > >OSHP (\_SB_.PCI0.S
On Thu, 27 Jun 2024 15:09:12 +0200
Igor Mammedov wrote:
> On Thu, 20 Jun 2024 17:03:13 +0100
> Jonathan Cameron wrote:
>
> > Using a property allows us to hide the internal details of the PCI device
> > from the code to build a SRAT Generic Initiator Affinity Structur
On Thu, 27 Jun 2024 14:46:14 +0100
Jonathan Cameron wrote:
> On Thu, 27 Jun 2024 15:27:58 +0200
> Igor Mammedov wrote:
>
> > On Thu, 20 Jun 2024 17:03:15 +0100
> > Jonathan Cameron wrote:
> >
> > > This allows the ACPI SRAT Generic Port Affinity Struct
On Fri, 7 Jun 2024 14:17:24 +
Ricardo Ribalda wrote:
> Signed-off-by: Ricardo Ribalda
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
> b/tests/qtest/bios-tables-test-allowed-diff.h
>
},
>
> Package (0x04)
> {
> 0x0001,
> Zero,
> LNKS,
> Zero
> },
> Context:
> https://lore.
On Thu, 27 Jun 2024 14:51:55 +0200
Igor Mammedov wrote:
> On Thu, 20 Jun 2024 17:03:17 +0100
> Jonathan Cameron wrote:
>
> > The test to be added exercises many corners of the SRAT and HMAT table
> did you mean 'corner
On Tue, 25 Jun 2024 11:52:24 +0800
Shiyuan Gao wrote:
> SHPC driver will be loaded fail in i440fx machine, the dmesg shows
> that OS cannot get control of SHPC hotplug and hotplug device to
> the PCI bridge will fail when we use SHPC Native type:
>
> [3.336059] shpchp :00:03.0: Requesting
On Thu, 20 Jun 2024 17:03:15 +0100
Jonathan Cameron wrote:
> This allows the ACPI SRAT Generic Port Affinity Structure
> creation to be independent of PCI internals. Note that
> the UID is currently the PCI bus number.
>
> Suggested-by: Igor Mammedov
> Signed-off-by
On Thu, 20 Jun 2024 17:03:13 +0100
Jonathan Cameron wrote:
> Using a property allows us to hide the internal details of the PCI device
> from the code to build a SRAT Generic Initiator Affinity Structure with
> PCI Device Handle.
>
> Suggested-by: Igor Mammedov
> Signe
On Thu, 20 Jun 2024 17:03:12 +0100
Jonathan Cameron wrote:
> Igor noted that this function only builds one instance, so was rather
> misleadingly named. Fix that.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
>
>
On Thu, 20 Jun 2024 17:03:17 +0100
Jonathan Cameron wrote:
> The test to be added exercises many corners of the SRAT and HMAT table
did you mean 'corner cases"?
> generation.
>
> Signed-off-by: Jonathan Cameron
> ---
> v3: No change
> ---
> tests/qtes
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