Re: [PATCH v5 11/13] hw/riscv/riscv-iommu: Add another irq for mrif notifications

Hi Daniel, On 2024/7/9 上午 01:34, Daniel Henrique Barboza wrote: From: Andrew Jones And add mrif notification trace. Signed-off-by: Andrew Jones Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- hw/riscv/riscv-iommu-pci.c | 2 +- hw/riscv/riscv-iommu.c | 1 +

[PATCH] target/riscv: Add a property to set vl to ceil(AVL/2)

RVV spec allows implementations to set vl with values within [ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). This behavior helps identify compiler issues and bugs. Signed-off-by: Jason Chien --- ta

Re: [PATCH v5 05/13] hw/riscv: add riscv-iommu-pci reference device

Hi Daniel, On 2024/7/9 上午 01:34, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU can be modelled as a PCIe device following the guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU as a PCIe device". Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel

Re: [PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation

Hi Danial, On 2024/6/25 上午 04:18, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at:

Re: [PATCH v4 01/14] exec/memtxattr: add process identifier to the transaction attributes

Reviewed-by: Jason Chien On 2024/6/25 上午 04:18, Daniel Henrique Barboza wrote: From: Tomasz Jeznach Extend memory transaction attributes with process identifier to allow per-request address translation logic to use requester_id / process_id to identify memory mapping (e.g. enabling IOMMU w

Re: [PATCH v2 0/6] target/riscv: Add support for Control Transfer Records Ext.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: This series enables Control Transfer Records extension support on riscv platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and the latest release can be found here [0] CTR extension

Re: [PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: The Control Transfer Records (CTR) extension provides a method to record a limited branch history in register-accessible internal chip storage. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable

Re: [PATCH v2 4/6] target/riscv: Add support to record CTR entries.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and

Re: [PATCH v2 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: CTR entries are accessed using ctrsource, ctrtarget and ctrdata registers using smcsrind/sscsrind extension. This commits extends the csrind extension to support CTR registers. ctrsource is accessible through xireg CSR, ctrtarget is

Re: [PATCH v2 5/6] target/riscv: Add CTR sctrclr instruction.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 7

Re: [PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 128

Re: [PATCH v2 1/6] target/riscv: Remove obsolete sfence.vm instruction

Reviewed-by: Jason Chien On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 - 2 files changed, 6 deletions(-) diff

Re: [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation

On 2024/6/18 下午 06:06, Jason Chien wrote: Hi Daniel, On 2024/5/24 上午 01:39, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv

Re: [PATCH v3 09/13] hw/riscv/riscv-iommu: add s-stage and g-stage support

Hi Daniel, On 2024/5/24 上午 01:39, Daniel Henrique Barboza wrote: From: Tomasz Jeznach Add support for s-stage (sv32, sv39, sv48, sv57 caps) and g-stage (sv32x4, sv39x4, sv48x4, sv57x4 caps). Most of the work is done in the riscv_iommu_spa_fetch() function that now has to consider how many

Re: [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation

Hi Daniel, On 2024/5/24 上午 01:39, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at:

Re: [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

It makes sense. Thank you for the explanation. Rajnesh Kanwal 於 2024年6月10日 週一 下午10:12寫道： > > Thanks Jason for your review. > > On Tue, Jun 4, 2024 at 11:14 AM Jason Chien > wrote: > > > > > > Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: > > > > Th

Re: [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation

Hi Daniel, On 2024/5/24 上午 01:39, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at:

Re: [PATCH RFC 4/8] target/riscv: Support generic CSR indirect access

The predicate functions should contain the access control by the state-enable CSRs, which is not presented in this patch. Do you mind that I take over the indirect CSR access control part? The Signed-off-by will be kept. Atish Patra 於 2024/2/17 上午 08:01 寫道: From: Kaiwen Xue This adds the

Re: [PATCH RFC 2/8] target/riscv: Decouple AIA processing from xiselect and xireg

Atish Patra 於 2024/2/17 上午 08:01 寫道: From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/csr.c | 147

Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.

I correct? Thanks in advance. Beeman Strong 於 2024/6/5 上午 02:46 寫道: On Tue, Jun 4, 2024 at 10:19 AM Jason Chien wrote: Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: > CTR extension adds a new instruction sctrclr to quickly > clear the recorded entries buffer. > &g

Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.

depend upon implementation of S-mode. Beeman Strong 於 2024/6/5 上午 06:32 寫道: There is no dependency on Smcsrind, only Sscsrind. On Tue, Jun 4, 2024 at 12:29 AM Jason Chien wrote: Smctr depends on the Smcsrind extension, Ssctr depends on the Sscsrind extension, and both Smctr

Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.

Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 7 +++

Re: [PATCH 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: CTR entries are accessed using ctrsource, ctrtarget and ctrdata registers using smcsrind/sscsrind extension. This commits extends the csrind extension to support CTR registers. ctrsource is accessible through xireg CSR, ctrtarget is accessible through

Re: [PATCH 4/6] target/riscv: Add support to record CTR entries.

This commit is missing CTR for cm.jalt, cm.jt, cm.popret, cm.popretz. Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke

Re: [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 159

Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.

Smctr depends on the Smcsrind extension, Ssctr depends on the Sscsrind extension, and both Smctr and Ssctr depend upon implementation of S-mode. There should be a dependency check in riscv_cpu_validate_set_extensions(). Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: This series enables Control

Re: [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation

Daniel Henrique Barboza 於 2024/3/8 上午 12:03 寫道: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf Add

Re: [PATCH v3 3/3] target/riscv: Relax vector register check in RISCV gdbstub

Ping. Jason Chien 於 2024年3月28日 週四 上午10:24寫道： > In current implementation, the gdbstub allows reading vector registers > only if V extension is supported. However, all vector extensions and > vector crypto extensions have the vector registers and they all depend > on Zve32x. The gd

Re: [PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions

Ping. Jason Chien 於 2024年3月28日 週四 上午10:23寫道： > This patch series adds the support for Zve32x and Zvx64x and makes vector > registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled. > > v2: > Rebase onto riscv-to-apply.next (commit 385e575). > v3: &g

[PATCH v3 1/3] target/riscv: Add support for Zve32x extension

Add support for Zve32x extension and replace some checks for Zve32f with Zve32x, since Zve32f depends on Zve32x. Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 2 ++ target/riscv

[PATCH v3 2/3] target/riscv: Add support for Zve64x extension

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and enabling Zve64x enables Zve32x according to their dependency. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107 Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou Reviewed-by: Daniel Henrique

[PATCH v3 3/3] target/riscv: Relax vector register check in RISCV gdbstub

In current implementation, the gdbstub allows reading vector registers only if V extension is supported. However, all vector extensions and vector crypto extensions have the vector registers and they all depend on Zve32x. The gdbstub should check for Zve32x instead. Signed-off-by: Jason Chien

[PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions

This patch series adds the support for Zve32x and Zvx64x and makes vector registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled. v2: Rebase onto riscv-to-apply.next (commit 385e575). v3: Spuash patch 2 into patch 1. Spuash patch 4 into patch 3. Jason Chien (3

[PATCH v2 1/5] target/riscv: Add support for Zve32x extension

Add support for Zve32x extension and replace some checks for Zve32f with Zve32x, since Zve32f depends on Zve32x. Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target

[PATCH v2 4/5] target/riscv: Expose Zve64x extension to users

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107 Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f6287bf892..18e1ae66f4 100644

[PATCH v2 2/5] target/riscv: Expose Zve32x extension to users

Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 851ac7372c..6bd8798bb5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1473,6 +1473,7

[PATCH v2 5/5] target/riscv: Relax vector register check in RISCV gdbstub

In current implementation, the gdbstub allows reading vector registers only if V extension is supported. However, all vector extensions and vector crypto extensions have the vector registers and they all depend on Zve32x. The gdbstub should check for Zve32x instead. Signed-off-by: Jason Chien

[PATCH v2 3/5] target/riscv: Add support for Zve64x extension

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and enabling Zve64x enables Zve32x according to their dependency. Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv

[PATCH v2 0/5] target/riscv: Support Zve32x and Zve64x extensions

This patch series adds the support for Zve32x and Zvx64x and makes vector registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled. v2: Rebase onto riscv-to-apply.next (commit 385e575). Jason Chien (5): target/riscv: Add support for Zve32x extension target/riscv: Expose

Re: [PATCH 1/5] target/riscv: Add support for Zve32x extension

I will re-send shortly. Thanks. Daniel Henrique Barboza 於 2024年3月20日 週三 上午5:19寫道： > Hi Jason, > > Care to re-send please? The patches don't apply to neither > riscv-to-apply.next > nor master. > > > Thanks, > > Daniel > > On 3/19/24 13:23, Jason Chie

Re: [PATCH 1/5] target/riscv: Add support for Zve32x extension

Ping. Can anyone review the patches please? Jason Chien 於 2024年3月7日 週四 上午1:09寫道： > Add support for Zve32x extension and replace some checks for Zve32f with > Zve32x, since Zve32f depends on Zve32x. > > Signed-off-by: Jason Chien > Reviewed-by: Frank Chang > Rev

Re: [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions

Ping. Can anyone review the patches please? Jason Chien 於 2024年3月7日 週四 上午1:09寫道： > This patch series adds the support for Zve32x and Zvx64x and makes vector > registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled. > > Jason Chien (5): > target/riscv: Add sup

[PATCH 3/5] target/riscv: Add support for Zve64x extension

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and enabling Zve64x enables Zve32x according to their dependency. Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv

[PATCH 1/5] target/riscv: Add support for Zve32x extension

Add support for Zve32x extension and replace some checks for Zve32f with Zve32x, since Zve32f depends on Zve32x. Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target

[PATCH 2/5] target/riscv: Expose Zve32x extension to users

Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 10ccae3323..37e4557b47 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1469,6 +1469,7

[PATCH 4/5] target/riscv: Expose Zve64x extension to users

Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8b5d1eb6a8..58b2a94694 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1473,6 +1473,7

[PATCH 5/5] target/riscv: Relax vector register check in RISCV gdbstub

In current implementation, the gdbstub allows reading vector registers only if V extension is supported. However, all vector extensions and vector crypto extensions have the vector registers and they all depend on Zve32x. The gdbstub should check for Zve32x instead. Signed-off-by: Jason Chien

[PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions

This patch series adds the support for Zve32x and Zvx64x and makes vector registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled. Jason Chien (5): target/riscv: Add support for Zve32x extension target/riscv: Expose Zve32x extension to users target/riscv: Add support

[PATCH v2] target/riscv: Update $ra with current $pc in trans_cm_jalt()

currently executing, which results in an infinite loop. This commit stores the jump address in a temporary, updates $ra with the current $pc, and copies the temporary to $pc. Signed-off-by: Jason Chien Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvzce.c.inc | 6 +- 1 file

Re: [PATCH] target/riscv: Update $pc after linking to $ra in trans_cm_jalt()

You are right. I'll send patch v2 shortly. Thank you for the reply. Richard Henderson 於 2024年2月7日 週三 上午4:24寫道： > On 2/6/24 23:18, Jason Chien wrote: > > The original implementation sets $pc to the address read from the jump > > vector table first and links $ra with the addr

[PATCH] target/riscv: Update $pc after linking to $ra in trans_cm_jalt()

currently executing, which results in an infinite loop. This commit reverses the two action. Firstly, $ra is updated with the address of the next instruction after $pc, and sets $pc to the address read from the jump vector table. Signed-off-by: Jason Chien --- target/riscv/insn_trans

Re: [PATCH 2/2] hw/intc: Make rtc variable names consistent

Thanks for the update. On Tue, Aug 22, 2023 at 1:53 AM Alistair Francis wrote: > On Mon, Aug 21, 2023 at 12:15 PM Jason Chien > wrote: > > > > Ping. > > This has been applied to the RISC-V tree. It will go in after the QEMU > release freeze is over (probably a

Re: [PATCH 2/2] hw/intc: Make rtc variable names consistent

Ping. On Fri, Aug 11, 2023 at 2:25 AM Alistair Francis wrote: > On Fri, Jul 28, 2023 at 4:57 AM Jason Chien > wrote: > > > > The variables whose values are given by cpu_riscv_read_rtc() should be > named > > "rtc". The variables whose value are given b

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

This bug was also in 8.0. Jason On Fri, Aug 11, 2023 at 10:07 PM Peter Maydell wrote: > On Fri, 11 Aug 2023 at 10:55, Peter Maydell > wrote: > > > > On Thu, 10 Aug 2023 at 18:51, Michael S. Tsirkin wrote: > > > > > > On Wed, Aug 09, 2023 at

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

the patch <https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg02162.html> link: https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg02162.html On Fri, Aug 11, 2023 at 1:44 AM Michael S. Tsirkin wrote: > On Fri, Aug 11, 2023 at 01:22:08AM +0800, Jason Chien wrote: > > A

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

tml/qemu-devel/2021-11/msg02162.html> that solves the same bus issue. Do you have any suggestions on the order of realization? Thanks! On Thu, Aug 10, 2023 at 5:24 AM Michael S. Tsirkin wrote: > On Wed, Aug 09, 2023 at 10:22:50AM +, Jason Chien wrote: > > In pcie_bus_realize(), a r

[PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

ce is not accessible on "dw-pcie". The issue can be resolved by adding the PCI_BUS_EXTENDED_CONFIG_SPACE flag to "pcie" before "dw-pcie" is realized. Signed-off-by: Jason Chien --- hw/pci-host/designware.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/pci-

Re: [RESEND PATCH v3 1/1] target/riscv: Add Zihintntl extension ISA string to DTS

Ping This patch seems to be ignored. patch link: https://lore.kernel.org/qemu-devel/20230726074049.19505-2-jason.ch...@sifive.com/ On Wed, Jul 26, 2023 at 3:41 PM Jason Chien wrote: > RVA23 Profiles states: > The RVA23 profiles are intended to be used for 64-bit application > p

Re: [PATCH 1/2] hw/intc: Fix upper/lower mtime write calculation

Hi, The patch seems to be ignored. I am not sure who to ping. Could someone please review this patch? Thank you! patch link: https://lore.kernel.org/qemu-devel/20230728082502.26439-1-jason.ch...@sifive.com/ On Fri, Jul 28, 2023 at 4:25 PM Jason Chien wrote: > When writing the upper mtime,

Re: [PATCH 2/2] hw/intc: Make rtc variable names consistent

Hi, The patch seems to be ignored. I am not sure who to ping. Could someone please review this patch? Thank you! patch link: https://lore.kernel.org/qemu-devel/20230728082502.26439-2-jason.ch...@sifive.com/ Jason On Fri, Jul 28, 2023 at 4:25 PM Jason Chien wrote: > The variables whose val

[PATCH 1/2] hw/intc: Fix upper/lower mtime write calculation

When writing the upper mtime, we should keep the original lower mtime whose value is given by cpu_riscv_read_rtc() instead of cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime. Signed-off-by: Jason Chien --- hw/intc/riscv_aclint.c | 5 +++-- 1 file changed, 3 insertions

[PATCH 2/2] hw/intc: Make rtc variable names consistent

The variables whose values are given by cpu_riscv_read_rtc() should be named "rtc". The variables whose value are given by cpu_riscv_read_rtc_raw() should be named "rtc_r". Signed-off-by: Jason Chien --- hw/intc/riscv_aclint.c | 6 +++--- 1 file changed, 3 insertions(+),

[RESEND PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS

In v2, I rebased the patch on https://github.com/alistair23/qemu/tree/riscv-to-apply.next However, I forgot to add "Reviewed-by" in v2, so I add them in v3. Jason Chien (1): target/riscv: Add Zihintntl extension ISA string to DTS target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.

[RESEND PATCH v3 1/1] target/riscv: Add Zihintntl extension ISA string to DTS

-used opcode, e.g. ADD x0, x0, x2, which QEMU already supports, and QEMU does not emulate cache. Therefore these instructions can be considered as a no-op, and we only need to add a new property for the Zihintntl extension. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jason

[PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS

In v2, I rebased the patch on https://github.com/alistair23/qemu/tree/riscv-to-apply.next However, I forgot to add "Reviewed-by" in v2, so I add them in v3. Jason Chien (1): target/riscv: Add Zihintntl extension ISA string to DTS target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.

[PATCH v3 1/1] target/riscv: Add Zihintntl extension ISA string to DTS

opcode, e.g. ADD x0, x0, x2, which QEMU already supports, and QEMU does not emulate cache. Therefore these instructions can be considered as a no-op, and we only need to add a new property for the Zihintntl extension. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jason Chien

Re: [PATCH v2] target/riscv: Add Zihintntl extension ISA string to DTS

Hi all, I am sorry that I forgot to add "Reviewed-by". I will add "Reviewed-by" and send v3 shortly. Jason Chien On Tue, Jul 11, 2023 at 1:47 PM Jason Chien wrote: > RVA23 Profiles states: > The RVA23 profiles are intended to be used for 64-bit application > pro

[PATCH v2] target/riscv: Add Zihintntl extension ISA string to DTS

opcode, e.g. ADD x0, x0, x2, which QEMU already supports, and QEMU does not emulate cache. Therefore these instructions can be considered as a no-op, and we only need to add a new property for the Zihintntl extension. Signed-off-by: Jason Chien --- target/riscv/cpu.c | 2 ++ target/riscv

[PATCH] target/riscv: Add Zihintntl extension ISA string to DTS

opcode, e.g. ADD x0, x0, x2, which QEMU already supports, and QEMU does not emulate cache. Therefore these instructions can be considered as a no-op, and we only need to add a new property for the Zihintntl extension. Signed-off-by: Jason Chien --- target/riscv/cpu.c | 2 ++ target/riscv

[RFC PATCH] target/riscv: Add Zihintntl extension ISA string to DTS

cache, therefore we just need to add a new property for the extension. Signed-off-by: Jason Chien --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 881bddf393..aa99781f17 100644

[PATCH] target/riscv: Set the correct exception for implict G-stage translation fail

c. Signed-off-by: Jason Chien --- target/riscv/cpu_helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a944f25694..ff2a1469dc 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1277,7 +1277