Re: [Qemu-devel] [PATCH] tcg: Fix helper function vs host abi for float16

d-off-by: Richard Henderson <richard.hender...@linaro.org> Some AArch64 tests I had that previously failed on a x86-64 host now pass. Tested-by: Laurent Desnogues <laurent.desnog...@gmail.com> Perhaps the two occurrences of the following comment in target/arm/translate-a64.c could be rem

Re: [Qemu-devel] [PATCH 13/16] translate-all: protect TB jumps with a per-destination-TB lock

On Tue, Feb 27, 2018 at 12:33 PM, Paolo Bonzini wrote: > On 27/02/2018 06:39, Emilio G. Cota wrote: >> Using a hash table or a binary tree to keep track of the jumps >> doesn't really pay off, not only due to the increased memory usage, >> but also because most TBs have only

Re: [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission

On Mon, Feb 26, 2018 at 1:32 PM, Peter Maydell wrote: > Paragraph (3) isn't saying "BSD license is special", > it's saying "the TCG codegen code is special" -- it's a theoretically > well-defined reusable subset of code that has its own tighter standards > for what

Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support

On Wed, Feb 7, 2018 at 12:53 PM, Ard Biesheuvel wrote: > On 7 February 2018 at 11:49, Alex Bennée wrote: >> >> Ard Biesheuvel writes: >> >>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to

Re: [Qemu-devel] [PATCH 1/2] tcg: Allow constant pool entries in the prologue

t. > > Reported-by: Laurent Desnogues <laurent.desnog...@gmail.com> > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Laurent Desnogues <laurent.desnog...@gmail.com> on an AArch64 host and with running qemu on qemu. Thanks for taking care of th

Re: [Qemu-devel] [PULL 28/32] target/arm: [tcg] Port to generic translation framework

Hello, On Wed, Sep 6, 2017 at 6:06 PM, Richard Henderson wrote: > From: Lluís Vilanova > > Tested-by: Emilio G. Cota > Reviewed-by: Emilio G. Cota > Signed-off-by: Lluís Vilanova >

Re: [Qemu-devel] [PATCH v8 7/7] trace: [trivial] Statically enable all guest events

On Mon, Jun 26, 2017 at 11:18 AM, Lluís Vilanova wrote: > Daniel P Berrange writes: > >> On Thu, Jun 08, 2017 at 10:25:22PM -0400, Emilio G. Cota wrote: >>> From: Lluís Vilanova >>> >>> The optimizations of this series makes it feasible to have them >>>

Re: [Qemu-devel] [PATCH v2 0/6] tcg: move the tcg files into tcg/ subdirectory.

Hello, On Wed, May 31, 2017 at 2:54 PM, Paolo Bonzini wrote: > > > On 31/05/2017 08:28, Yang Zhong wrote: >> Move the tcg related files into tcg/ subdirectory, which will make >> the code more clean in qemu. Next step, we will base on those changes >> to disable tcg. > > You

Re: [Qemu-devel] [RFC PATCH] ui/console: ensure graphic updates don't race with TCG vCPUs

On Wed, Mar 22, 2017 at 5:28 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Laurent Desnogues <laurent.desnog...@gmail.com> writes: > >> Hi Alex, >> >> this patch breaks: >> >> http://wiki.qemu.org/download/arm-test-0.2.tar.gz >

Re: [Qemu-devel] [RFC PATCH] ui/console: ensure graphic updates don't race with TCG vCPUs

Hi Alex, this patch breaks: http://wiki.qemu.org/download/arm-test-0.2.tar.gz qemu-system-arm -kernel zImage.integrator -initrd arm_root.img -append "console=ttyAMA0" -machine integratorcp -serial stdio -icount 0 Uncompressing

Re: [Qemu-devel] [PULL 08/24] tcg: drop global lock during TCG code execution

Hello, On Fri, Feb 24, 2017 at 12:20 PM, Alex Bennée wrote: > From: Jan Kiszka > > This finally allows TCG to benefit from the iothread introduction: Drop > the global mutex while running pure TCG CPU code. Reacquire the lock > when entering MMIO

Re: [Qemu-devel] [PATCH 0/3] target-arm: cache tbflags in CPUARMState

On Mon, Sep 26, 2016 at 12:04 PM, Laurent Desnogues <laurent.desnog...@gmail.com> wrote: > Hello, > > On Wed, Sep 14, 2016 at 11:56 AM, Paolo Bonzini <pbonz...@redhat.com> wrote: >> Computing TranslationBlock flags is pretty expensive on ARM, especially >> 32-b

Re: [Qemu-devel] [PATCH 0/3] target-arm: cache tbflags in CPUARMState

t code. I like that patch! I quickly tested with some softmmu images on both AArch32 and AArch64 and I can confirm the speedup. As far as your patch goes: Tested-by: Laurent Desnogues <laurent.desnog...@gmail.com> Reviewed-by: Laurent Desnogues <laurent.desnog...@gmail.com> Thanks,

Re: [Qemu-devel] [PATCH] tcg: increase MAX_OP_PER_INSTR to 395

Hello, On Fri, Sep 23, 2016 at 1:53 AM, Joseph Myers wrote: > MAX_OP_PER_INSTR is currently 266, reported in commit > 14dcdac82f398cbac874c8579b9583fab31c67bf to be the worst case for the > ARM A64 decoder. > > Whether or not it was in fact the worst case at that time in

Re: [Qemu-devel] [PATCH] target-arm/arm-semi.c: In SYS_HEAPINFO use correct type for 'limit'

On Mon, Jul 4, 2016 at 6:49 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > In commit f5666418c4 most of the SYS_HEAPINFO implementation was > fixed to use target_ulong rather than uint32_t, but the 'limit' > variable was not changed. > > Reported-by: Laurent Desn

Re: [Qemu-devel] [PATCH 2/2] target-arm/arm-semi.c: Fix SYS_HEAPINFO for 64-bit guests

On Fri, Jun 24, 2016 at 5:49 PM, Peter Maydell wrote: > SYS_HEAPINFO is one of the few semihosting calls which has to write > values back into a parameter block in memory. When we added > support for 64-bit semihosting we updated the code which reads from > the

Re: [Qemu-devel] [PATCH 1/2] linux-user: Make semihosting heap/stack fields abi_ulongs

g > rather than uint32_t. (This only in practice affects ARM AArch64 > since all the other semihosting implementations are 32-bit.) > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnog...@gmail.com> Thanks, Laurent > ---

Re: [Qemu-devel] [PATCH 07/10] tb hash: hash phys_pc, pc, and flags with xxhash

On Wed, Apr 6, 2016 at 7:42 PM, Richard Henderson <r...@twiddle.net> wrote: > On 04/06/2016 10:32 AM, Emilio G. Cota wrote: >> On Wed, Apr 06, 2016 at 08:06:57 +0200, Laurent Desnogues wrote: >>> On Tue, Apr 5, 2016 at 7:19 PM, Richard Henderson <r...@twiddle.net> w

Re: [Qemu-devel] [PATCH 02/10] compiler.h: add QEMU_CACHELINE + QEMU_ALIGN() + QEMU_CACHELINE_ALIGNED

On Wed, Apr 6, 2016 at 1:44 PM, Paolo Bonzini wrote: > > > On 05/04/2016 22:09, Lluís Vilanova wrote: >> Ah. That's just an example. For cross-compilation you would use a different >> march argument (or none to use the default target sub-arch) and get the >> parameter for the

Re: [Qemu-devel] [PATCH 07/10] tb hash: hash phys_pc, pc, and flags with xxhash

On Tue, Apr 5, 2016 at 7:19 PM, Richard Henderson <r...@twiddle.net> wrote: > On 04/05/2016 09:33 AM, Laurent Desnogues wrote: >> The 'flags' field is 64-bit. You're thinking of cflags, I guess. > > Well that's silly. Since it's filled in via > > static inlin

Re: [Qemu-devel] [PATCH 07/10] tb hash: hash phys_pc, pc, and flags with xxhash

On Tue, Apr 5, 2016 at 5:41 PM, Richard Henderson wrote: > On 04/04/2016 10:30 PM, Emilio G. Cota wrote: >> >> Tests show that the other element checked for in tb_find_physical, >> cs_base, is always a match when tb_phys+pc+flags are a match, >> so hashing cs_base is wasteful.

Re: [Qemu-devel] [PATCH 1/4] target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs

eal reset value, move the regdef > into the same place that we define the 32-bit SCTLR. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnog...@gmail.com> Thanks, Laurent > --- > target-arm/helper.c | 23 ++

Re: [Qemu-devel] tcg: improve MAX_CODE_GEN_BUFFER_SIZE for arm

Hello, On Tue, Dec 8, 2015 at 11:39 AM, Aurelien Jarno wrote: [...] > I already posted a patch a long time ago to remove the 16MB limit on ARM > hosts: > > http://lists.gnu.org/archive/html/qemu-devel/2012-10/msg01684.html > > However as you can see in the thread, it has

Re: [Qemu-devel] [PATCH] target-arm: raise exception on misaligned LDREX operands

On Thu, Dec 3, 2015 at 3:36 PM, Peter Maydell wrote: > On 30 November 2015 at 22:23, Andrew Baumann > wrote: >> Qemu does not generally perform alignment checks. However, the ARM ARM >> requires implementation of alignment exceptions for a

Re: [Qemu-devel] [PATCH v2 for-2.5] target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

and load-acquire/store-release) were not correct. This > error meant that in turn we ended up with code attempting to handle > the non-existent case of "non-exclusive load-acquire/store-release > pair". Delete that broken and now unreachable code. > > Reported-by: Laure

Re: [Qemu-devel] [PATCH v2 for-2.5] target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

andle > the non-existent case of "non-exclusive load-acquire/store-release > pair". Delete that broken and now unreachable code. > > Reported-by: Laurent Desnogues <laurent.desnog...@gmail.com> > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewe

Re: [Qemu-devel] [PATCH for-2.5] target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8

Hello, On Fri, Nov 20, 2015 at 3:32 PM, Peter Maydell wrote: > In an LPAE format descriptor in ARMv8 the address field extends > up to bit 47, not just bit 39. Correct the masking so we don't > give incorrect results if the output address size is greater > than 40 bits,

Re: [Qemu-devel] [PATCH for-2.5] target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8

On Fri, Nov 20, 2015 at 4:20 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 20 November 2015 at 15:18, Laurent Desnogues > <laurent.desnog...@gmail.com> wrote: >> Hello, >> >> On Fri, Nov 20, 2015 at 3:32 PM, Peter Maydell <peter.mayd...@linar

Re: [Qemu-devel] [PATCH for-2.5] default-configs/aarch64-linux-user.mak: Remove unused define

sed in the mail with > the patches adding aarch64 support). Remove the stray define. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnog...@gmail.com> Thanks, Laurent > --- > Harmless, but we might as well drop this patch into

Re: [Qemu-devel] [PULL 21/38] vhost: use a function for each call

Hello, There are some errors with gcc 4.4.7 due to the use of an anonymous union in VhostUserMsg in declarations with initialization. Please see below. Thanks. On Wed, Oct 21, 2015 at 12:27 PM, Michael S. Tsirkin wrote: > From: Marc-André Lureau >

Re: [Qemu-devel] [PULL] vhost-user: fix up rhel6 build

on field. This fixes the issue I previously reported. > Signed-off-by: Michael S. Tsirkin <m...@redhat.com> Tested-by: Laurent Desnogues <laurent.desnog...@gmail.com> Thanks, Laurent > --- > hw/virtio/vhost-user.c | 48 > 1

Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2

On Thu, Oct 8, 2015 at 10:24 AM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Laurent Desnogues <laurent.desnog...@gmail.com> writes: > >> Hello, >> >> On Sun, Oct 4, 2015 at 12:38 AM, Edgar E. Iglesias >> <edgar.igles...@gmail.com>

Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2

Hello, On Sun, Oct 4, 2015 at 12:38 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Signed-off-by: Edgar E. Iglesias > --- > target-arm/cpu.h| 1 + > target-arm/helper.c | 12 > 2

Re: [Qemu-devel] [PATCH] target-arm/translate.c: Handle non-executable page-straddling Thumb insns

*/ > +end_of_page = (dc->pc >= next_page_start) || > +((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc)); > + > } while (!dc->is_jmp && !tcg_op_buf_full() && > !cs->singlestep_enabled && > !singlestep && > !dc->ss_active && > - dc->pc < next_page_start && > + !end_of_page && > num_insns < max_insns); > > if (tb->cflags & CF_LAST_IO) { Except for the two comments and the question, this looks good to me. Reviewed-by: Laurent Desnogues <laurent.desnog...@gmail.com> Laurent

Re: [Qemu-devel] [PATCH] qapi: Fix cgen() for Python older than 2.7

On Mon, Sep 7, 2015 at 5:45 PM, Markus Armbruster <arm...@redhat.com> wrote: > A feature new in Python 2.7 crept into commit 77e703b: re.subn()'s > fifth argument. Avoid that, use re.compile(). > > Reported-by: Laurent Desnogues <laurent.desnog...@gmail.com> > Signe

Re: [Qemu-devel] [PULL 02/33] qapi: Clean up cgen() and mcgen()

Hello Markus, I found some Python issue with this commit. On Fri, Sep 4, 2015 at 4:21 PM, Markus Armbruster wrote: > Commit 05dfb26 added eatspace stripping to mcgen(). Move it to > cgen(), just in case somebody gets tempted to use cgen() directly > instead of via mcgen(). >

Re: [Qemu-devel] [PATCH] machine: Drop use of DEFAULT_RAM_SIZE in help text

, so we can't tell the user the default RAM size in the help text anymore now. Thus I don't see an easy way to expose the default ram size to the user in the help text. The easiest option IMHO is to just drop this piece of information. It's unfortunate, but I agree. Acked-by: Laurent Desnogues

Re: [Qemu-devel] [PULL 34/40] machine: add default_ram_size to machine class

Hello, On Wed, Jun 3, 2015 at 11:45 PM, Alexander Graf ag...@suse.de wrote: From: Nikunj A Dadhania nik...@linux.vnet.ibm.com Machines types can have different requirement for default ram size. Introduce a member in the machine class and set the current default_ram_size to 128MB. For

Re: [Qemu-devel] [PATCH] glib-compat.h: change assert to g_assert

compilation breakage after 28507a415a9b1e. Reported-by: Laurent Desnogues laurent.desnog...@gmail.com Signed-off-by: Michael Tokarev m...@tls.msk.ru Tested-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent --- include/glib-compat.h | 6 +++--- 1 file changed, 3 insertions(+), 3

Re: [Qemu-devel] [PATCH v2] libcacard: stop including qemu-common.h

Hello, On Mon, Apr 27, 2015 at 3:27 PM, Michael Tokarev m...@tls.msk.ru wrote: From: Paolo Bonzini pbonz...@redhat.com This is a small step towards making libcacard standalone. on my system the removal of qemu-common.h inclusion broke compilation due to assert being used in glib-compat.h. A

Re: [Qemu-devel] [PATCH v2] libcacard: stop including qemu-common.h

On Wed, May 6, 2015 at 12:05 PM, Michael Tokarev m...@tls.msk.ru wrote: 06.05.2015 12:23, Laurent Desnogues wrote: Hello, On Mon, Apr 27, 2015 at 3:27 PM, Michael Tokarev m...@tls.msk.ru wrote: From: Paolo Bonzini pbonz...@redhat.com This is a small step towards making libcacard standalone

Re: [Qemu-devel] [PATCH] tcg: optimise memory layout of TCGTemp

Hello, On Fri, Mar 27, 2015 at 10:09 PM, Emilio G. Cota c...@braap.org wrote: On Fri, Mar 27, 2015 at 09:55:03 +, Alex Bennée wrote: Have you been able to measure any performance improvement with these new structures? In theory, if aligned with cache lines, performance should improve but

Re: [Qemu-devel] [PATCH] tcg: Complete handling of ALWAYS and NEVER

Hi Richard, On Fri, Feb 20, 2015 at 8:19 PM, Richard Henderson r...@twiddle.net wrote: Missing from movcond, and brcondi_i32 (but not brcondi_i64). Signed-off-by: Richard Henderson r...@twiddle.net Tested-by: Laurent Desnogues laurent.desnog...@gmail.com --- tcg/tcg-op.c | 22

Re: [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments

Hi Richard, On Thu, Feb 19, 2015 at 10:14 PM, Richard Henderson r...@twiddle.net wrote: While doing the mechanics of a previous patch set converting translators to use to TCGLabel pointers, I was reminded of several outstanding OPTME comments in the aarch64 translator. I had started with the

Re: [Qemu-devel] [PATCH 10/11] target-arm: Implement fccmp branchless

Hi Richard, On Fri, Feb 20, 2015 at 4:53 PM, Richard Henderson r...@twiddle.net wrote: On 02/20/2015 05:57 AM, Laurent Desnogues wrote: The problem with this approach is that you'll always call the FP compare which might result in FP flags corruption. The ARMv8 manual clearly states

Re: [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments

On Fri, Feb 20, 2015 at 11:00 AM, Laurent Desnogues laurent.desnog...@gmail.com wrote: On Thu, Feb 19, 2015 at 10:14 PM, Richard Henderson r...@twiddle.net wrote: While doing the mechanics of a previous patch set converting translators to use to TCGLabel pointers, I was reminded of several

Re: [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments

On Thu, Feb 19, 2015 at 10:14 PM, Richard Henderson r...@twiddle.net wrote: While doing the mechanics of a previous patch set converting translators to use to TCGLabel pointers, I was reminded of several outstanding OPTME comments in the aarch64 translator. I had started with the csel change,

Re: [Qemu-devel] [PATCH 10/11] target-arm: Implement fccmp branchless

Hi Richard, On Thu, Feb 19, 2015 at 10:14 PM, Richard Henderson r...@twiddle.net wrote: Signed-off-by: Richard Henderson r...@twiddle.net --- target-arm/translate-a64.c | 50 +++--- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git

Re: [Qemu-devel] [PATCH] target-arm: Squash input denormals in FRECPS and FRSQRTS

bit is set to enable squashing of input denormals. Signed-off-by: Peter Maydell peter.mayd...@linaro.org Tested-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent --- A quick eyeball of helper-a64.c suggests that these are the only other insns we needed to fix, and a risu

Re: [Qemu-devel] QEMU: DBT vs. Interpretation

On Wed, Jan 28, 2015 at 4:39 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 28 January 2015 at 15:10, Laurent Desnogues laurent.desnog...@gmail.com wrote: - environment variables which are parsed by the runtime at process start; to get around that issue you'll have to reintroduce

Re: [Qemu-devel] QEMU: DBT vs. Interpretation

On Mon, Jan 26, 2015 at 9:54 PM, Javier Picorel javier.pico...@epfl.ch wrote: Hi, We are trying to make QEMU deterministic for architectural simulation. In the absence of I/O, let’s say only executing user code or exceptions, is there any source of indeterminism (e.g., non deterministic

Re: [Qemu-devel] [PATCH 0/2] cpu-exception_index fixes

Hello, On Fri, Dec 19, 2014 at 12:53 PM, Paolo Bonzini pbonz...@redhat.com wrote: Two fixes for cpu-exception_index: - breakage of linux-user from commit e511b4d Tested-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent - wrong subsection definition in 2.2 (see patch 2

Re: [Qemu-devel] [PATCH] arm: fix TB alignment check

Hello, On Tue, Oct 21, 2014 at 2:14 PM, Pavel Dovgalyuk pavel.dovga...@ispras.ru wrote: Sometimes page faults happen during the translation of the target instructions. To avoid the faults in the middle of the TB we have to stop translation at the end of the page. Current implementation of

Re: [Qemu-devel] [PATCH] target-arm: A64: remove redundant store

On Tue, Oct 14, 2014 at 3:08 PM, Alex Bennée alex.ben...@linaro.org wrote: There is not much point storing the same value twice in a row. Reported-by: Laurent Desnogues laurent.desnog...@gmail.com Signed-off-by: Alex Bennée alex.ben...@linaro.org Reviewed-by: Laurent Desnogues laurent.desnog

Re: [Qemu-devel] [PATCH] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0

code path. Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent --- target-arm/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target-arm/translate.c b/target-arm/translate.c index 8a2994f

Re: [Qemu-devel] [PATCH] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type any

-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent --- target-arm/cpu64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index c30f47e..4807ce1 100644 --- a/target-arm

[Qemu-devel] AArch64: ld/st exclusive pair bug

Hello, there's a bug in target-arm/translate-a64.c:disas_ldst_excl. The line: TCGv_i64 tcg_rt2 = cpu_reg(s, rt); is accessing the wrong register. Thanks, Laurent

[Qemu-devel] AArch64: duplicate store in do_fp_st

Hello, in target-arm/translate-a64.c:do_fp_st, it looks like there's an extraneous store: TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ); tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s)); The second one can safely

Re: [Qemu-devel] The master branch qemu compiles failed.

On Tue, Jul 1, 2014 at 10:17 AM, Paolo Bonzini pbonz...@redhat.com wrote: Il 01/07/2014 10:00, ChenLiang ha scritto: ./configure --enable-debug --target-list=x86_64-softmmu make -j net/l2tpv3.c: In function ‘net_l2tpv3_process_queue’: net/l2tpv3.c:368: error: invalid use of undefined type

[Qemu-devel] AArch64 linux-user: SA_ONSTACK usage in get_sigframe

Hello, in linux-user/signal.c the code for AArch64 get_sigframe reads like this: if ((ka-sa_flags SA_ONSTACK) !sas_ss_flags(sp)) { Shouldn't that be TARGET_SA_ONSTACK? The same question applies to Microblaze and OpenRISC. Thanks, Laurent

Re: [Qemu-devel] [PATCH] [v2 PATCH] qemu-img: sort block formats in help message

Hi, just noticed the use of some too recent glib features: g_strcmp0 and GSequence related ones. Thanks, Laurent On Mon, May 5, 2014 at 6:53 PM, Mike Day ncm...@ncultra.org wrote: The help message for qemu-img lists the supported block formats, of which there are 27 as of version 2.0.50. The

Re: [Qemu-devel] [PATCH] target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchanged

values just 3 times. Skip flushing the TLB if the SCTLR value isn't actually being changed; this speeds up my sample boot by 3-5%. Reported-by: Laurent Desnogues laurent.desnog...@gmail.com Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Laurent Desnogues laurent.desnog

Re: [Qemu-devel] [PULL 28/31] curl: Remove unnecessary explicit calls to internal event handler

Hello, sorry for another late detection of the use of too recent features. On Wed, Apr 30, 2014 at 8:24 PM, Kevin Wolf kw...@redhat.com wrote: From: Matthew Booth mbo...@redhat.com Remove calls to curl_multi_do where the relevant handles are already registered to the event loop. Ensure

Re: [Qemu-devel] [Qemu-ppc] [RFC 00/12] target-ppc: Decimal Floating Point

Hi, sorry for being late into the discussion. Couldn't Intel Decimal Floating-Point Math Library be used? It seems to be using a BSD license. http://www.netlib.org/misc/intel/ Laurent

Re: [Qemu-devel] [PULL for-2.0 2/2] cpu: Avoid QOM casts for CPU()

-by: Laurent Desnogues laurent.desnog...@gmail.com Suggested-by: Paolo Bonzini pbonz...@redhat.com Signed-off-by: Andreas Färber afaer...@suse.de It works fine here. Tested-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent --- include/qom/cpu.h | 7 ++- 1 file changed, 6

Re: [Qemu-devel] [PULL for-2.0 2/2] cpu: Avoid QOM casts for CPU()

+strong 16.7 old+strong+disable 15.9 old+noprot 16.6 old+noprot+disable 16.0 strong 15.8 strong+disable 15.7 noprot 15.6 noprot+disable 15.5 Thanks, Laurent Compare commit 6e42be7cd10260fd3a006d94f6c870692bf7a2c0. Reported-by: Laurent Desnogues

Re: [Qemu-devel] [PATCH for-2.0] cpu: do not use QOM casts in ENV_GET_CPU

, the movement of fields from CPU_COMMON to CPUState was completed. Reported-by: Laurent Desnogues laurent.desnog...@gmail.com Cc: Andreas Faerber afaer...@suse.de Signed-off-by: Paolo Bonzini pbonz...@redhat.com Andreas pointed out on IRC that this is just the tip of the iceberg, due to code

Re: [Qemu-devel] [PATCH for-2.0] cpu: do not use QOM casts in ENV_GET_CPU

was completed. I tested the ARM part of the patch; on my test (kernel boot + run of Sunspider with Google V8), I get the following user time results: (average of 5 runs): - before: 17.8s - with your patch: 17s configure was run with no option. Tested-by: Laurent Desnogues laurent.desnog

Re: [Qemu-devel] [PATCH v3] configure: add option to disable -fstack-protector flags

Hello, On Mon, Jan 13, 2014 at 9:36 PM, Steven Noonan ste...@uplinklabs.net wrote: The -fstack-protector flag family is useful for ensuring safety and for debugging, but has a performance impact. Here are some boot time comparisons of the various versions of -fstack-protector using

Re: [Qemu-devel] [PATCH for-2.0] configure: add option to disable -fstack-protector flags

-protector-strong, -fstack-protector-all, no stack protector. Signed-off-by: Steven Noonan snoo...@amazon.com Cc: Anthony Liguori aligu...@amazon.com Reviewed-by: Stefan Weil s...@weilnetz.de [Prefer -fstack-protector-all to -fstack-protector, suggested by Laurent Desnogues. - Paolo] Signed-off

[Qemu-devel] Aarch64 MLS bug

Hello, the code that implements Aarch64 AdvSIMD MLS instruction looks like this: if (opcode == 0xf || opcode == 0x12) { /* SABA, UABA, MLA, MLS: accumulating ops */ static NeonGenTwoOpFn * const fns[3][2] = { {

Re: [Qemu-devel] [PATCH for-2.0] target-arm: Fix A64 Neon MLS

than a subtraction. Reported-by: Laurent Desnogues laurent.desnog...@gmail.com Signed-off-by: Peter Maydell peter.mayd...@linaro.org Tested-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent --- Bit embarrassing, not sure how this slipped through the testing process

[Qemu-devel] QOM cast debug

Hello, while looking at some perf results, I saw object_dynamic_cast_assert taking more than 3% of the run time. After some digging I found out that this time can be cut by passing --disable-qom-cast-debug to configure. This was added by Paolo: commit 3556c233d931ad5ffa46a35cb25cfc057732ebb8

Re: [Qemu-devel] QOM cast debug

On Thu, Mar 20, 2014 at 1:45 PM, Paolo Bonzini pbonz...@redhat.com wrote: Il 20/03/2014 11:52, Laurent Desnogues ha scritto: Hello, while looking at some perf results, I saw object_dynamic_cast_assert taking more than 3% of the run time. After some digging I found out that this time can

Re: [Qemu-devel] [PULL for-2.0 7/7] linux-user: Implement capget, capset

Hello, On Wed, Mar 19, 2014 at 3:03 PM, riku.voi...@linaro.org wrote: From: Peter Maydell peter.mayd...@linaro.org Implement the capget and capset syscalls. This is useful because simple programs like 'ls' try to use it in AArch64, and otherwise we emit a lot of noise about it being

Re: [Qemu-devel] [PATCH buildfix for-2.0] linux-user: Fix build if headers don't define _LINUX_CAPABILITY_VERSION_1

...@linaro.org Reported-by: Laurent Desnogues laurent.desnog...@gmail.com I'm not sure I should send Reviewed-by for issues I reported, but here it is. Reviewed-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent --- linux-user/syscall.c | 2 +- 1 file changed, 1 insertion

Re: [Qemu-devel] [PATCH] target-arm: Add ARM_CP_IO notation to PMCR reginfo

On Sat, Mar 15, 2014 at 7:31 PM, Peter Maydell peter.mayd...@linaro.org wrote: Now that the PMCR writefn makes timer accesses, its reginfo needs the ARM_CP_IO flag, so that icount mode works correctly. (Fixes the bug accidentally introduced in commit 7c2cb42b). Reported-by: Laurent Desnogues

Re: [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn

-by: Laurent Desnogues laurent.desnog...@gmail.com Signed-off-by: Alex Bennée alex.ben...@linaro.org Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent --- target-arm/translate-a64.c | 3 +-- 1 file changed, 1

[Qemu-devel] [Aarch64] Bug in add/sub extended reg

Hello, there's a bug in SP handling in disas_add_sub_ext_reg: /* non-flag setting ops may use SP */ if (!setflags) { tcg_rn = read_cpu_reg_sp(s, rn, sf); tcg_rd = cpu_reg_sp(s, rd); } else { tcg_rn = read_cpu_reg(s, rn, sf); tcg_rd = cpu_reg(s, rd);

Re: [Qemu-devel] [PATCH v2 0/5] disas: add libvixl to support A64 disassembly

On Wed, Jan 29, 2014 at 9:51 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 29 January 2014 20:01, Laurent Desnogues laurent.desnog...@gmail.com wrote: On Tue, Jan 28, 2014 at 12:45 PM, Peter Maydell peter.mayd...@linaro.org wrote: Ping for review/testing/comments on this version

Re: [Qemu-devel] [PATCH v2 0/5] disas: add libvixl to support A64 disassembly

On Tue, Jan 28, 2014 at 12:45 PM, Peter Maydell peter.mayd...@linaro.org wrote: Ping for review/testing/comments on this version, please? I still dislike the idea of importing so much code in particular for something that is incomplete: as far as I can see, AdvSIMD instructions are not

Re: [Qemu-devel] save compiled qemu traces.

On Thu, Dec 12, 2013 at 5:07 AM, Xin Tong trent.t...@gmail.com wrote: see questions below. On Tue, Dec 10, 2013 at 12:25 AM, Alex Bennée alex.ben...@linaro.org wrote: trent.t...@gmail.com writes: Does anyone have profiles on how much time QEMU spends in translating instructions. QEMU does

Re: [Qemu-devel] usecase for QEMU

On Thu, Nov 28, 2013 at 3:27 AM, Xin Tong trent.t...@gmail.com wrote: I am wondering what are some of the use cases for QEMU as an instruction set emulator(not KVM). I know QEMU is used for the android emulator and QEMU is used to host a few cycle accurate simulators ? what else ? QEMU can

Re: [Qemu-devel] [PATCH 29/60] AArch64: Add orri instruction emulation

On Tue, Nov 26, 2013 at 12:56 PM, Claudio Fontana claudio.font...@linaro.org wrote: On 09/27/2013 09:42 PM, Richard Henderson wrote: On 09/26/2013 05:48 PM, Alexander Graf wrote: +if (setflags) { +tcg_dst = cpu_reg(dest); +} else { +tcg_dst = cpu_reg_sp(dest); +}

Re: [Qemu-devel] [PATCH 14/60] AArch64: Add orr instruction emulation

On Mon, Nov 18, 2013 at 11:15 AM, Claudio Fontana claudio.font...@linaro.org wrote: Hello, On 09/27/2013 08:25 PM, Richard Henderson wrote: On 09/26/2013 05:48 PM, Alexander Graf wrote: This patch adds emulation support for the orr instruction. Signed-off-by: Alexander Graf ag...@suse.de

Re: [Qemu-devel] [RFC v2] target-arm: provide skeleton for a64 insn decoding

claudio.font...@linaro.org Signed-off-by: Alex Bennée a...@bennee.com Reviewed-by: Alex Bennée a...@bennee.com Reviewed-by: Laurent Desnogues laurent.desnog...@arm.com Except for a few minor comments below (which probably don't require a new patch). By the way it might be nice to add some bit

Re: [Qemu-devel] [RFC 0/4] ARM aarch64 disas output libvixl support

On Sun, Sep 15, 2013 at 7:27 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 15 September 2013 17:41, Rob Landley r...@landley.net wrote: Wait, incorporating C++ code into qemu was considered the _good_ solution? What was the bad solution? Not supporting disassembly at all, and/or

Re: [Qemu-devel] [PATCH v3 00/29] tcg-aarch64 improvements

On Tue, Sep 3, 2013 at 9:37 AM, Richard W.M. Jones rjo...@redhat.com wrote: On Mon, Sep 02, 2013 at 10:54:34AM -0700, Richard Henderson wrote: I'm not sure if I posted v2 or not, but my branch is named -3, therefore this is v3. ;-) The jumbo fixme patch from v1 has been split up. This has

Re: [Qemu-devel] [PATCH 0/4] target-arm: Implement support for generic timers

tested this patch series with a 3.9 kernel for Vexpress with Cortex-A15. It works fine with the generic timer correctly detected and used. Note the 4th patch doesn't apply as is any more. Tested-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent

Re: [Qemu-devel] [PATCH] target-arm: Avoid g_hash_table_get_keys()

the list of keys. Signed-off-by: Peter Maydell peter.mayd...@linaro.org Tested-by: Laurent Desnogues laurent.desnog...@gmail.com Thanks, Laurent --- target-arm/helper.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c

Re: [Qemu-devel] [PATCH] linux-user: Fix sys_utimensat (would not compile on old glibc)

*at() functions). Fix this by correctly cleaning up the sys_utimensat() implementation and #defines, so that we always provide the syscall if needed whether we're doing it via glibc or not. Signed-off-by: Peter Maydell peter.mayd...@linaro.org Tested-by: Laurent Desnogues laurent.desnog

Re: [Qemu-devel] [PATCH 1/4] include/elf.h: add aarch64 ELF machine and relocs

Hello, On Thu, May 23, 2013 at 10:14 AM, Claudio Fontana claudio.font...@huawei.com wrote: we will use the 26bit relative relocs in the aarch64 tcg target. Is there really any point in adding all of the relocation types? i386 doesn't, mips doesn't, x86_64 doesn't. I didn't check the others.

Re: [Qemu-devel] [PATCH 3/3] tcg/aarch64: implement new TCG target for aarch64

On Tue, May 28, 2013 at 3:01 PM, Claudio Fontana claudio.font...@huawei.com wrote: On 27.05.2013 23:14, Laurent Desnogues wrote: On Monday, May 27, 2013, Richard Henderson r...@twiddle.net mailto:r...@twiddle.net wrote: On 2013-05-27 04:43, Claudio Fontana wrote: Hmm, true. Although I'd

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

Hi Claudio, here are some minor tweaks and comments. You work is very interesting and will form a good basis for further improvements. Thanks! diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c new file mode 100644 index 000..da859c7 --- /dev/null +++

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

Hi, basically pointing out what I pointed for v1. On Thu, May 23, 2013 at 10:18 AM, Claudio Fontana claudio.font...@huawei.com wrote: add preliminary support for TCG target aarch64. Signed-off-by: Claudio Fontana claudio.font...@huawei.com --- include/exec/exec-all.h |5 +-

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

On Mon, May 27, 2013 at 12:13 PM, Claudio Fontana claudio.font...@huawei.com wrote: Hello, On 27.05.2013 11:47, Laurent Desnogues wrote: Hi, basically pointing out what I pointed for v1. On Thu, May 23, 2013 at 10:18 AM, Claudio Fontana claudio.font...@huawei.com wrote: add preliminary

Re: [Qemu-devel] [PATCH 3/3] tcg/aarch64: implement new TCG target for aarch64

On Monday, May 27, 2013, Richard Henderson r...@twiddle.net wrote: On 2013-05-27 04:43, Claudio Fontana wrote: Hmm, true. Although I'd been thinking more along the lines of arranging the code such that we'd use movz to set the zero. I think we need to keep treating zero specially if we want

Re: [Qemu-devel] [PATCH 3/3] tcg/aarch64: implement new TCG target for aarch64

On Tue, May 14, 2013 at 2:01 PM, Claudio Fontana claudio.font...@huawei.com wrote: [...] +static void tcg_target_qemu_prologue(TCGContext *s) +{ +int r; +int frame_size; /* number of 16 byte items */ + +/* we need to save (FP, LR) and X19 to X28 */ +frame_size = (1) +

Re: [Qemu-devel] [PATCH v3 11/28] libcacard: teach vscclient to use GMainLoop for portability

Hi, it looks like some new glib functions are used here which are not available in older glib. On Mon, Apr 22, 2013 at 5:04 PM, Alon Levy al...@redhat.com wrote: From: Marc-André Lureau marcandre.lur...@gmail.com This version handles non-blocking sending and receiving from the socket.

Re: [Qemu-devel] [PATCH v3 07/28] build-sys: must link with -fstack-protector

Hi, Another issue on my old distro. On Mon, Apr 22, 2013 at 5:04 PM, Alon Levy al...@redhat.com wrote: From: Marc-André Lureau marcandre.lur...@gmail.com It is needed to give that flag to the linker as well, but latest libtool 2.4.2 still swallows that argument, so let's pass it with

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