ng __thread variables in linux-user when apps are compiled
> with -mtp=cp15 possible. legal cp15 register to acces from linux-user are
> already checked in cp15_user_ok.
>
> While at it, make the cp15.c13 Thread ID registers available only on
> ARMv6K and newer.
>
> Sign
On Tue, Jan 26, 2010 at 5:00 PM, Riku Voipio wrote:
> From: Riku Voipio
>
> Change the system-emulation code also to only support accessing
> the cp15.c13 Thread ID registers on ARMv6K and newer.
>
> Signed-off-by: Riku Voipio
> ---
> target-arm/helper.c | 12
> 1 files changed,
On Tue, Jan 26, 2010 at 5:00 PM, Riku Voipio wrote:
> From: Riku Voipio
>
> If you compile applications with gcc -mtp=cp15, __thread
> access's will generate an abort. Implement accessing allowed
> cp15.c13 registers on ARMv6K+ in linux-user.
>
> Signed-off-by: Riku Voipio
> ---
> target-arm/he
On Wed, Jan 20, 2010 at 9:14 PM, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> ---
> linux-user/mmap.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/linux-user/mmap.c b/linux-user/mmap.c
> index c1c7e48..25fc0b2 100644
> --- a/linux-user/mmap.c
> +++ b/li
t64_round_to_int uses special assembler code for arm
> and has no explicit return value.
>
> As there is no obvious reason why arm should need special
> code, all fpu related conditionals were removed.
> The remaining code is standard (C99) and compiles for arm,
> too.
>
>
Since you wanted a "no, because..." there's at least
one :-)
On Tue, Dec 1, 2009 at 9:41 PM, Filip Navara wrote:
> While most of the ARMv5 instructions are backward compatible with ARMv4, there
> are few important differences. Most notably the stack pop and load
> instructions
> ignore the lowes
On Sun, Jan 10, 2010 at 9:46 PM, Blue Swirl wrote:
> On Sun, Jan 10, 2010 at 8:20 PM, Palle Lyckegaard wrote:
>> Hi,
>>
>> The tcg mulu2 operation is apparently missing for the sparc target
>> (tcg/sparc/tcg-target.c function tcg_out_op())
>>
>> Is anyone else working on implementing the missing
On Wed, Dec 30, 2009 at 6:23 PM, Daniel Jacobowitz wrote:
> From: Daniel Jacobowitz
>
> This patch improves ARM semihosting to the point where qemu-system-arm
> can simulate cc1 from GCC. It can't simulate GCC itself, which
> requires POSIXy bits like execve, but the backend works, including the
On Sun, Dec 27, 2009 at 12:37 PM, Michael S. Tsirkin wrote:
[...]
> 2. When a change is committed to the tree, often no notification is sent
> to the author.
> Why is it a good idea to ask everyone to subscribe to qemu commits
> list as well? Can 'applied thanks' mail be sent to patch author
On Wed, Dec 23, 2009 at 11:44 AM, Nigel Horne wrote:
> Laurent Desnogues wrote:
>>
>> On Wed, Dec 23, 2009 at 11:04 AM, Nigel Horne wrote:
>>
>>>
>>> I get this error on my Debian box:
>>>
>>> ...
>>> CC alpha-linux-use
On Wed, Dec 23, 2009 at 11:04 AM, Nigel Horne wrote:
> I get this error on my Debian box:
>
> ...
> CC alpha-linux-user/fpu/softfloat.o
> In file included from /home/njh/src/qemu/fpu/softfloat.h:523,
> from /home/njh/src/qemu/fpu/softfloat.c:35:
> ...
> /home/njh/src/qemu/fpu/softfloat-specialize.
On Tue, Dec 22, 2009 at 3:46 PM, Laurent Desnogues
wrote:
> On Tue, Dec 22, 2009 at 1:02 AM, Richard Henderson wrote:
>> On 12/21/2009 03:08 PM, Laurent Desnogues wrote:
>>>
>>> If you wanted to use movcond, you'd have to make
>>> cond + move a special c
On Tue, Dec 22, 2009 at 1:02 AM, Richard Henderson wrote:
> On 12/21/2009 03:08 PM, Laurent Desnogues wrote:
>>
>> If you wanted to use movcond, you'd have to make
>> cond + move a special case...
>
> You'd certainly want the ARM front-end to use movcond
On Sun, Dec 20, 2009 at 12:11 AM, Aurelien Jarno wrote:
> On Sat, Dec 19, 2009 at 10:46:38AM -0800, Richard Henderson wrote:
>> Signed-off-by: Richard Henderson
>
> This looks ok, though I would appreciate someone else to review it in
> details.
It looks good to me too (though I didn't test it e
On Sat, Dec 19, 2009 at 7:01 PM, Richard Henderson wrote:
> Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/README | 20 +++-
> tcg/tcg-op.h | 47 +++
> tcg/tcg-opc.h
On Mon, Dec 21, 2009 at 11:50 PM, Richard Henderson wrote:
[...]
>> Even if movcond was quick to generate
>> host code, for instance for ARM, you'd have to explicitly detect
>> conditional moves
>
> One of us is confused. Why would I have to explicitly detect conditional
> moves?
Most ARM instru
On Mon, Dec 21, 2009 at 9:28 PM, Richard Henderson wrote:
> On 12/21/2009 01:13 AM, Laurent Desnogues wrote:
>>
>> The question for the generalized movcond is how useful is it?
>> Which front-ends would need it and would the cost to generate
>> code for it on some (mo
On Mon, Dec 21, 2009 at 10:47 AM, Paolo Bonzini wrote:
> On 12/21/2009 10:13 AM, Laurent Desnogues wrote:
>>
>> Which front-ends would need it and would the cost to generate
>> code for it on some (most?) back-ends be amortized?
>
> The ARM front-end could definitely us
On Mon, Dec 21, 2009 at 3:00 AM, Richard Henderson wrote:
[...]
> I *am* convinced that to remove either VTRUE or VFALSE as arguments to the
> movcond primitive (implementing dest = (cond ? vtrue : dest) would do too
> much violence to both the liveness analysis and the register allocator
> within
On Sat, Dec 19, 2009 at 7:44 PM, Richard Henderson wrote:
> There are places, like brcond2, where we know that the destination
> of a forward branch will be within 127 bytes.
>
> Add the R_386_PC8 relocation type to support this. Add a flag to
> tcg_out_jxx and tcg_out_brcond* to enable it. Set
On Fri, Dec 18, 2009 at 10:38 PM, Richard Henderson wrote:
> On 12/18/2009 03:37 AM, Laurent Desnogues wrote:
>>>
>>> tcg: Generic support for conditional set and conditional move.
>>
>> Needs cosmetics changes.
>
> Fixed, attachment 1.
>
>
On Fri, Dec 18, 2009 at 6:11 PM, Richard Henderson wrote:
>> Also note that tcg_out_modrm will generate an unneeded prefix
>> for some registers. cf. the patch I sent to the list months ago.
>
> Huh. Didn't notice since the disassembler printed what I expected to see.
> Is fixing this at the sam
On Thu, Dec 17, 2009 at 6:55 PM, Richard Henderson wrote:
> There are places, like brcond2, where we know that the destination
> of a forward branch will be within 127 bytes. Add the R_386_PC8
> relocation type to support this, and add a flag to tcg_out_jxx to
> generate it. Set the flag in the
On Thu, Dec 17, 2009 at 7:38 PM, Richard Henderson wrote:
> Split out tcg_out_cond from tcg_out_brcond. Add "small" arguments
> to all branch functions for completeness. Unify all the calls to
> generate branches within brcond2 and pass on the small flag.
>
> Signed-off-by: Richard Henderson
>
On Thu, Dec 17, 2009 at 6:32 PM, Richard Henderson wrote:
> Implement conditional moves in the x86_64 backend.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/x86_64/tcg-target.c | 65 --
> 1 files changed, 62 insertions(+), 3 deletions(-)
>
> diff
On Thu, Dec 17, 2009 at 6:28 PM, Richard Henderson wrote:
> It is very handy to have a reliable mapping of a condition to its inverse.
> This will be used in several patches to follow.
>
> Signed-off-by: Richard Henderson
Acked-by: Laurent Desnogues
Laurent
> ---
>
On Thu, Dec 17, 2009 at 6:27 PM, Richard Henderson wrote:
> Defines setcond and movcond for implementing conditional moves at
> the tcg opcode level. 64-bit-on-32-bit is expanded via a setcond2
> primitive plus other operations.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/README | 26
On Thu, Dec 17, 2009 at 8:32 PM, Richard Henderson wrote:
>> funny how you seem to follow the same paths I did months ago :-)
>
> Heh. They are the obvious points for improvement in the emulation.
> Hopefully we can get them finished this time, so that some third
> person doesn't go through the s
On Thu, Dec 17, 2009 at 4:32 PM, malc wrote:
[...]
>
> Some:
> a. It breaks tcg on PPC[1]:
>
> ...qemu/tcg/tcg.c:1378: tcg fatal error
What a surprise :-)
I can provide a similar patch for ARM (I already have one
for my own implementation of setcond), but I'll wait for this
patch series to s
on helps the compiler to do its jobs.
>
> gcc-4.4 does not need this, but is still not standard on all platforms.
>
> Signed-off-by: Stefan Weil
Acked-by: Laurent Desnogues
> ---
> target-alpha/helper.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
>
On Tue, Dec 15, 2009 at 4:50 AM, Richard Henderson wrote:
> On 12/14/2009 04:31 PM, Richard Henderson wrote:
>>
>> On 12/14/2009 12:11 PM, Laurent Desnogues wrote:
>>>
>>> I'll take a closer look at your patch tomorrow.
>>
>> For the record,
On Mon, Dec 14, 2009 at 7:02 PM, Richard Henderson wrote:
> One of the other folks here (I'm sorry, I've forgotten who as I misplaced
> the mail) passed me a preliminary patch to tackle the missing fp rounding
> mode support. That patch added helpers to change the rounding mode, and
> injected th
On Mon, Dec 14, 2009 at 1:07 PM, Paul Brook wrote:
>> - uint32_t VF; /* V is the bit 31. All other bits are undefined */
>> + uint32_t VF; /* V is the bit 28. */
>
> No. The original comment is correct.
And so that the answer is at least a bit useful: these fields
are not directly mapped t
On Fri, Dec 11, 2009 at 7:33 PM, Aurelien Jarno wrote:
> On Fri, Dec 11, 2009 at 05:54:06PM +0900, Jun Koi wrote:
>> Hi,
>>
>> Thanks to everybody helping me to have more understanding on QEmu
>> internals. This community is great!
>>
>> This trivial patch removes some unused params in tcg_out_st(
On Fri, Dec 11, 2009 at 4:18 AM, Jun Koi wrote:
>
> Another question: I look at tcg_gen_callN() to see how the helper is
> executed. We put the helper opcode into the TCG code buffer, and put
> helper's params into gen_opparam_buf.
>
> However, then when TCG generates code to actually call the hel
On Thu, Dec 10, 2009 at 1:05 AM, Richard Henderson wrote:
>
> The following patch series results in an emulator that's good enough
> to run a good bit of the GCC testsuite, dynamic linking and all.
> There are more failures than native hardware. At first glance they
> appear to be fpu related, bu
On Sat, Dec 5, 2009 at 6:44 PM, Avi Kivity wrote:
[...]
>
>> I think Laurent's proposal would work. We even could go so far as
>> rename the current function as qemu_malloc_possibly_broken (and adjust
>> callers mechanically) and introduce two new versions, which handle the
>> zero case in clearly
Hello,
probably a stupid remark, but I'll do it anyway :-)
Let's assume there are some contexts where doing a memory
allocation with a size of 0 is invalid while in some other contexts
it is valid. Wouldn't it make sense in that case to have two
functions that do memory allocation?
Of course su
On Tue, Nov 24, 2009 at 7:51 PM, wrote:
>
> I am working on a project that extends qemu to track the memory accesses.
> All the functions in target-i386/ops_mem.h are instrumented.
> Logging the reads work fine, the writes give are troublesome.
> The code that I am tracking contains a lot of xor
On Wed, Nov 11, 2009 at 8:51 AM, Chad wrote:
> (this is mostly to get some ideas going rather than trying to get anything
> upstream... yet!)
>
> This version of tcg_out_mov for i386's tcg-target.c filters out the
>
> mov %ebx, %edx
> mov %ebx, [some index]
> mov %edx, %ebx
The question is: what
On Mon, Nov 9, 2009 at 3:39 PM, jamesmikedup...@googlemail.com
wrote:
[...]
> ./i386-softmmu/qemu -L / /bin/ls
> qemu: could not load PC BIOS 'bios.bin'
>
> Does not work.
Do you know what softmmu means? You should read QEMU
user manual.
[...]
> ./x86_64-softmmu/qemu-system-x86_64 -L / /bin/ls
2009/11/9 yuanzhu86 :
> Hi everyone:
> as I want to analysis the source code of qemu now, and there is a litte
> trouble at this fuction:
> in the file--Translate.c(target-i386)
>
> Line 6113 :
> case 0xea: /* ljmp im */
> {
> unsigned int selector, offset;
> if (COD
On Sun, Nov 8, 2009 at 6:47 PM, Chad wrote:
> Running qemu[-i386] with -d out_asm and looking at qemu.out shows this
> test/j**/jmp pattern repeatedly:
>
> 0xb1aa40f6: test %ecx,%ecx
> 0xb1aa40f8: jne 0xb1aa4115
> 0xb1aa40fe: jmp 0xb1aa4103
> 0xb1aa4103: mov $0xc0bf,%eax
>
> Therefo
On Sat, Nov 7, 2009 at 5:11 PM, Blue Swirl wrote:
[...]
>> Unless I missed something you didn't commit Glauber's patch.
>
> What's c169998802505c244b8bcad562633f29de7d74a4 then?
My bad, I updated and didn't notice you had applied further
modifications. I seriously lack the commit mail notificati
On Sat, Nov 7, 2009 at 9:40 AM, Blue Swirl wrote:
[...]
> Thanks, applied. While testing I noticed that the poor x86 emulator
> does not survive even five system_resets until BIOS refuses to boot.
> This happens without your patch. In comparison, I see no problems
> resetting Sparc32, Sparc64 or P
On Tue, Nov 3, 2009 at 8:50 PM, Glauber Costa wrote:
> There is absolutely no need to call reset functions when initializing
> devices. Since we are already registering them, calling qemu_system_reset()
> should suffice. Actually, it is what happens when we reboot the machine,
> and using the same
On Tue, Nov 3, 2009 at 9:16 PM, Glauber Costa wrote:
> On Tue, Nov 03, 2009 at 09:12:41PM +0100, Laurent Desnogues wrote:
>> On Tue, Nov 3, 2009 at 8:50 PM, Glauber Costa wrote:
>> > There is absolutely no need to call reset functions when initializing
>> > de
On Mon, Nov 2, 2009 at 7:42 PM, Aurelien Jarno wrote:
> On Mon, Nov 02, 2009 at 05:16:44PM +0200, Ulrich Hecht wrote:
>> On Thursday 22 October 2009, Aurelien Jarno wrote:
>> > Probably the second. Changing the instruction pointer in the helper
>> > instead of using the proper goto_tb TCG op preve
On Thu, Oct 29, 2009 at 3:01 PM, wrote:
> From: Juha Riihimäki
>
> TCG temporary variable handling in target-arm/translate.c is currently
> somewhat inconsistent; some functions allocate new temporaries that the
> calling function is expected to free and some other functions free
> temporaries t
On Thu, Oct 29, 2009 at 7:22 PM, Stuart Brady wrote:
> On Thu, Oct 29, 2009 at 04:01:15PM +0200, juha.riihim...@nokia.com wrote:
>>
>> -static inline TCGv gen_ld8s(TCGv addr, int index)
>> +static inline void gen_ld8s(TCGv ret, TCGv addr, int index)
>> {
>> - TCGv tmp = new_tmp();
>> - tcg_
On Thu, Oct 29, 2009 at 2:45 PM, wrote:
[...]
>
> Alrighty then, I did the patch against the latest git and it's rather
> large... but seems to have broken nothing at least in my testing. The
> patch will remove all implicit tcg temp variable allocation and
> deallocation in target-arm/translate.
On Thu, Oct 29, 2009 at 12:04 PM, Alexander Graf wrote:
[...]
>> More on (2): if there is no OS, then I think a small application like
>> bootloader should probably be present to launch the cross-compiled
>> executable on to Qemu. Any further suggestions on how to make (2) possible?
>> All the pr
On Thu, Oct 29, 2009 at 10:44 AM, malc wrote:
> On Thu, 29 Oct 2009, Laurent Desnogues wrote:
>
>> On Thu, Oct 29, 2009 at 9:14 AM, malc wrote:
>> > On Thu, 29 Oct 2009, Roy Tam wrote:
>> >
>> >> Version 0.37a of fmopl.c/h is relicensed to LGPL by Tats
On Thu, Oct 29, 2009 at 9:14 AM, malc wrote:
> On Thu, 29 Oct 2009, Roy Tam wrote:
>
>> Version 0.37a of fmopl.c/h is relicensed to LGPL by Tatsuyuki
>> Satoh(original fmopl developer).
>> other versions are not. Especially newer versions by Jarek Burczynski
>> as he refused to relicense new fmopl
his patch, casting all comparisons with the sizeof operator to
> signed ssize_t type to force comparisons to be between signed integral
> types.
>
> Signed-off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
Laurent
> ---
> target-arm/neon_helper.c | 26 +
Riihimäki
Acked-by: Laurent Desnogues
Laurent
> ---
> target-arm/translate.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 9d13d42..1988cc6 100644
> --- a/target-arm/translate.c
> +++
On Thu, Oct 22, 2009 at 1:17 PM, wrote:
> From: Juha Riihimäki
>
> Revised patch for getting rid of tcg temporary variable leaks in
> target-arm/translate.c. This version also includes the leak patch for
> gen_set_cpsr macro, now converted as a static inline function, which I
> sent earlier as a
as been revised to include the same behavior change in
> the gdb register write function.
>
> Signed-off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
Laurent
> ---
> target-arm/helper.c | 2 +-
> target-arm/translate.c | 3 +++
> 2 files changed, 4 insertions(+
On Mon, Oct 26, 2009 at 8:46 AM, wrote:
>
> On Oct 25, 2009, at 16:01, ext Laurent Desnogues wrote:
>
>> I don't really like the idea of having tcg_qemu_ld/st not factored
>> in some place, as it makes memory access tracing extensions
>> more intrusive.
>>
On Mon, Oct 26, 2009 at 8:32 AM, wrote:
[...]
>>
>> Shouldn't writes to FPEXC from gdb be protected in the same
>> way? Except for that I agree with your patch.
>
> Please correct me if I'm wrong but it seems to me that the code in
> gdbstub.c never writes anything to the VFP registers, at least
2009/10/25 Jan-Simon Möller :
> Hi !
>
> We encontered problems with the low default value for the stacksize in
> usermode (ok, whats "low").
> For environments like scratchbox, its hard to use "-s" as qemu is called by
> binfmt mechanism.
> The attached patch makes this configurable at compile-t
On Sat, Oct 24, 2009 at 1:19 PM, wrote:
> From: Juha Riihimäki
>
> Reduce the amount of TCG ops generated from NEON vld/vst instructions
> by simplifying the code generation.
>
> Signed-off-by: Juha Riihimäki
> ---
> target-arm/translate.c | 67 ---
On Sat, Oct 24, 2009 at 1:19 PM, wrote:
> From: Juha Riihimäki
>
> All other bits except for the EN in the VFP FPEXC register are defined
> as subarchitecture specific and real functionality for any of the
> other bits has not been implemented in QEMU. However, current code
> allows modifying al
On Sat, Oct 24, 2009 at 1:19 PM, wrote:
> From: Juha Riihimäki
>
> Current code is broken at least on gcc 4.2, the result of a comparison
> "-1 >= sizeof(type) * 8" results true and causes wrong code path to
> be taken. The fix has been revised to use a type cast instead of
> abs() function and
/vst4 instructions.
>
> Signed-off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
Laurent
> ---
> target-arm/translate.c | 133
> +---
> 1 files changed, 81 insertions(+), 52 deletions(-)
>
> diff --git a/target-arm/translate.
use a temporary to hold the intermediate value thus leaving the
> shift value in the temporary variable intact. This is a new patch
> in this version of the patch series.
>
> Signed-off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
Laurent
> ---
> target-arm/translate.c | 1
ase where the code would previously try to shift an integer value
> over 31 bits left/right.
>
> Signed-off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
Laurent
> ---
> target-arm/translate.c | 32 ++--
> 1 files changed, 18 insertions(+), 14
off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
Laurent
> ---
> target-arm/translate.c | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 8cb1c0f..38fb833 100644
> --- a/target-arm/translate
> offset value to a temporary variable on each loop iteration. This
> causes less TCG ops to be generated for a Thumb push/pop instruction
> if there are more than one register accessed, otherwise the amount of
> generated TCG ops is the same.
>
> Signed-off-by: Juha Riihim
gt; Signed-off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
Laurent
> ---
> target-arm/translate.c | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 9e924d4..353f638 100644
> --- a
a temporary variable on each loop
> iteration. This causes less TCG ops to be generated for a ARM load/
> store multiple instruction.
>
> Signed-off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
> ---
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> inde
ses:
>
> commit 04df13497befdb79c778d82d0901d290d164d250
> Author: Aurelien Jarno
> Date: Thu Oct 15 16:45:14 2009 +0200
>
> target-arm: use native tcg-ops for ror/bic/vorn
>
> Signed-off-by: Aurelien Jarno
Acked-by: Laurent Desnogues
> diff --git a/target-arm/helpers.h b/target-arm
On Fri, Oct 23, 2009 at 1:18 PM, Christoph Egger
wrote:
> On Friday 23 October 2009 13:03:54 Alexander Graf wrote:
>> On 23.10.2009, at 12:50, Boyapati, Anitha wrote:
>> > Hello,
>> >
>> > We have a proposal to add support for AVR32 target emulation in
>> > Qemu. So far, we are able to build qemu
t; sent earlier as a separate patch on top of this patch.
>
> Signed-off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
> ---
> target-arm/translate.c | 116 ---
> 1 files changed, 89 insertions(+), 27 deletions(-)
>
> diff --gi
On Wed, Oct 21, 2009 at 12:17 PM, wrote:
> Add support for neon vld1.64 instruction.
>
> From: Riku Voipio
> Signed-off-by: Juha Riihimäki
> ---
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 3ea9d51..d027572 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/trans
On Wed, Oct 21, 2009 at 1:01 PM, wrote:
> Current code is broken at least on gcc 4.2, the result of a comparison
> "-1 >= sizeof(type) * 8" results true and causes wrong code path to be
> taken. The fix utilizes abs() function where applicable and otherwise
> adds a test to ensure both arguments
On Thu, Oct 22, 2009 at 9:33 AM, wrote:
>
> On Oct 22, 2009, at 10:18, ext Laurent Desnogues wrote:
>
>> On Thu, Oct 22, 2009 at 8:49 AM, wrote:
>>>
>>> On Oct 21, 2009, at 13:46, ext Laurent Desnogues wrote:
>>>
>>>>> @@ -462
On Thu, Oct 22, 2009 at 8:49 AM, wrote:
>
> On Oct 21, 2009, at 13:46, ext Laurent Desnogues wrote:
>
>>> @@ -4624,31 +4624,31 @@ static int disas_neon_data_insn(CPUState *
>>> env, DisasContext *s, uint32_t insn)
>>>
On Mon, Oct 19, 2009 at 1:44 PM, wrote:
> Current ARM translator code has several places where it leaves
> temporary TCG variables alive. This patch removes all such instances I
> have found so far. Sorry for the mangled inlined patch, the mailserver
> I use doesn't like patches so I've also incl
On Wed, Oct 21, 2009 at 12:18 PM, wrote:
> Use native rotation if possible instead of a simulated one.
>
> From: Filip Navara
> Signed-off-by: Juha Riihimäki
Acked-by: Laurent Desnogues
> ---
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 99
On Wed, Oct 21, 2009 at 12:17 PM, wrote:
> Current implementation of the gen_set_cpsr macro creates a new
> temporary tcg variable through the tcg_const_i32 call but never marks
> it dead.
>
> Signed-off-by: Juha Riihimäki
> ---
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> in
On Wed, Oct 21, 2009 at 12:17 PM, wrote:
> Shift immediate value is incorrectly overwritten by a temporary
> variable in the processing of NEON vsri, vshl and vsli instructions.
>
> Signed-off-by: Juha Riihimäki
> ---
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 59bf7bc
On Wed, Oct 21, 2009 at 12:17 PM, wrote:
> Current implementation of thumb mul instruction is implemented as a
> 32x32->64 multiply which then uses only 32 least significant bits of
> the result. Replace that with a simple 32x32->32 multiply.
>
> Signed-off-by: Juha Riihimäk
On Mon, Oct 19, 2009 at 8:23 AM, wrote:
>
> I think I have a couple of other fixes and patches on top of that as
> well, but I'd rather wait until you get this bunch committed and then
> format the patches against the new mainline so that they apply.
It's already been committed (the commit notif
On Thu, Oct 15, 2009 at 11:51 PM, Aurelien Jarno wrote:
> Signed-off-by: Aurelien Jarno
> ---
> target-arm/translate.c | 4
> 1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 0c10ac2..bb0f8ef 100644
> --- a/target-a
t32_t num, int32_t den)
> {
> if (den == 0)
> return 0;
> + if (num == INT_MIN && den == -1)
> + return INT_MIN;
> return num / den;
> }
>
> --
> 1.6.1.3
Acked-by: Laurent Desnogues
That is provided we accept the behaviour for divis
{ 0x1031, 0x11, 0x400, 0, 0x3113, 0x2000, 0x01202000, 0x11 };
> @@ -394,10 +395,7 @@ uint32_t HELPER(uxtb16)(uint32_t x)
>
> uint32_t HELPER(clz)(uint32_t x)
> {
> - int count;
> - for (count = 32; x; count--)
> - x >>= 1;
> - return count;
> + return clz32(x);
> }
>
> int32_t HELPER(sdiv)(int32_t num, int32_t den)
> --
> 1.6.1.3
Acked-by: Laurent Desnogues
On Sun, Oct 18, 2009 at 5:09 AM, Jamie Lokier wrote:
[...]
>
> Please don't do that. Some code traces instructions through the
> vsyscall/vdso page, and will be surprised if a syscall instruction
> does not do what's expected based on the registers at that point.
>
> Also I don't know if anyone's
On Sun, Oct 18, 2009 at 4:47 AM, Jamie Lokier wrote:
> Laurent Desnogues wrote:
>> A recent compiler (gcc 4.4.0) produces this code for a statically
>> compiled program:
>>
>> 005779e0 :
>> 5779e0: 48 83 ec 08 sub $0x8,%rsp
>>
Hi Edgar,
On Sat, Oct 17, 2009 at 9:57 PM, Edgar E. Iglesias
wrote:
>
> It feels a bit strange to have the CPU model know about linux vsyscalls.
> Did you consider having the linux-user loader pass a qemu version of the
> x86_64 vdso to the guest through the auxvector? That version could probably
On Sat, Jul 11, 2009 at 5:14 PM, Laurent Desnogues
wrote:
> Hello,
>
> the attached patch implements two of the three x86_64 vsyscall's.
> Also attached is a test that demonstrates the issue and hopefully
> the fix.
>
> Note there is a trick in there: since vsys
On 2/24/08, claude vittoria <[EMAIL PROTECTED]> wrote:
> So in qemu I don't get the same comportement. The add of lr = pc + 4
> gives lr = pc + 8 into qemu.
> I think that s->pc += 4 at start of disas_arm_insn alters the result.
> Could you confirm ?
>
> 0x7caddlr, pc, #4
> 0x80ld
On 2/21/08, Andrew Warkentin <[EMAIL PROTECTED]> wrote:
> Why does it matter if it is 64-bit or not? Most programs at the moment
> don't benefit from being compiled 64-bit. I don't get the obsession with
> 64-bitness that most Linux and BSD people seem to have.
I have programs that run signific
On Jan 16, 2008 4:05 AM, Mulyadi Santosa <[EMAIL PROTECTED]> wrote:
> Hi...
>
> On Jan 16, 2008 4:34 AM, Jeremy C. Reed <[EMAIL PROTECTED]> wrote:
> > Any way to startup qemu with my own desired speed?
> Check http://www.miroslavnovak.com/qemu-brake_en.php
This can't be used to set the emulated p
On Jan 15, 2008 10:34 PM, Jeremy C. Reed <[EMAIL PROTECTED]> wrote:
> Any way to startup qemu with my own desired speed?
You can't as qemu emulated target speed is not constant.
qemu generates code on-the-fly and uses optimizations
that result in big variations.
Add to that there's no cycle accur
On Jan 3, 2008 11:11 PM, Clemens Kolbitsch <[EMAIL PROTECTED]> wrote:
>
> Well, the measuring I had in mind partly concentrats on TLB misses, page
> faults, etc. (in addition to the cycle measuring). guess i'll have to
> implement something for myself in qemu :-/
There's something not clear here:
Aurelien Jarno a écrit :
Maybe. The CPU probes for cacheline size, checks for errata #42 vs
#45, reads debug registers, attempts to identify the bus speed by
comparing I/O access times, tries to verify the system using a TPM and
fails all cases. What can you do?
Emulate a simpler architecture l
> The target doesn't really
> matter, I'm just interested in the process of building a linux sytem for
> arm and emulate it with Qemu.
You can perhaps look here:
http://www.linux-arm.org/LinuxDevTools/ScratchBoxQEMU
I have not tested it myself.
Laurent
Paul Brook a écrit :
I suggest you check again. I'm fairly sure the arm926 implements the Base
Restored abort model.
Yes, but arm7 is Based Updated IIRC. What particular implementation
does Qemu target?
There are so many IMPLEMENTATION DEFINED and UNPREDICTABLE in the
architecture (that are
This looks real and funny :)
http://www.ps3scene.com/news/static/WindowsXPonPS3viaQemuonLinux-1164389620.php
Laurent
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