://lore.kernel.org/qemu-devel/CAFEAcA-H=n-3mhc+el6yjfl1m+x+b+fk3mkgzbn74wnxiff...@mail.gmail.com/
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3-internal.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 0ebf2eebcf
er wrote:
> > >> Hi Peter, Richard,
> > >>
> > >> On 7/17/24 17:09, Jean-Philippe Brucker wrote:
> > >>> On Mon, Jul 15, 2024 at 08:45:00AM +, Mostafa Saleh wrote:
> > >>>> Currently, QEMU supports emulating either stage-1 o
Hi Peter,
On Sat, Jul 20, 2024 at 04:05:40PM +0100, Peter Maydell wrote:
> On Thu, 18 Jul 2024 at 14:20, Peter Maydell wrote:
> >
> > From: Mostafa Saleh
> >
> > SMMUv3 OAS is currently hardcoded in the code to 44 bits, for nested
> > configurations that c
-by: Mostafa Saleh
---
hw/arm/smmuv3-internal.h | 6 ++
hw/arm/smmuv3.c | 8 +++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index e4dd11e1e6..0f3ecec804 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3
IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2
SMMU instances we consider the input address as the IOVA, but when
nesting is used, we can't mix stage-1 and stage-2 addresses, so for
nesting only stage-1 is considered the IOVA and would be notified.
Signed-off-by: Mostafa Saleh
behaviour.
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 20 +---
hw/arm/smmuv3.c | 2 +-
hw/arm/trace-events | 2 +-
include/hw/arm/smmu-common.h | 2 +-
4 files changed, 16
Everything is in place, consolidate parsing of STE cfg and setting
translation stage.
Advertise nesting if stage requested is "nested".
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 35 ++---
48bits.
- Remove unused functions/macros: pa_range/MAX_PA.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 7 ---
hw/arm/smmuv3-internal.h | 13 -
hw/arm/smmuv3.c | 35 ---
3 files changed, 32 insertions
ASIDs.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 47
hw/arm/smmuv3.c | 23 --
hw/arm/trace-events | 2 +-
include/hw/arm/smmu-common.h | 3 ++-
4 files changed, 66
for stage-1 only (ASID >= 0)
Also, rework trace events to reflect the new implementation.
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 16
hw/arm/smmuv3.c |
mented in the PTW logic, so no extra handling
required.
As in CD and TTBx translation context, the iova is not known, setting
the InputAddr was removed from "smmuv3_do_translate" and set after
from "smmuv3_translate" with the new function "smmuv3_fixup_event"
Sig
of the translation, as faults from translating stage-1
tables are considered as CLASS_TT and not CLASS_IN, a new member
"is_ipa_descriptor" added to "SMMUPTWEventInfo" to differ faults
from walking stage 1 translation table and faults from translating
an IPA for a transaction.
Signed-o
Cap the OAS to 48 bits as PTW doesn’t support 52 bits.
- Fix ASID/VMID representation in some contexts as 16 bits while
they can be -1
- Increase visibility in trace points
Mostafa Saleh (18):
hw/arm/smmu-common: Add missing size check for stage-1
hw/arm/smmu: Fix IPA for stage-2 events
and BIT(1) is
stage-2 and both is nested.
- Tracing, as stage is printed as int.
Reviewed-by: Eric Auger
Reviewed-by: Alex Bennée
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 14 +++---
hw/arm/smmuv3.c | 17 +
include/hw/arm/smmu-common.h
, as ptw_info is initialised by zero in
smmuv3_translate().
Fixes: e703f7076a “hw/arm/smmuv3: Add page table walk for stage-2”
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 10 ++
hw/arm/smmuv3.c | 4
2 files
, the combination logic
chooses:
- tg and level from the entry which has the smallest addr_mask.
- Based on that the iova that would be cached is recalculated.
- Translated_addr is chosen from stage-2.
Reviewed-by: Eric Auger
Reviewed-by: Jean-Philippe Brucker
Signed-off-by: Mostafa Saleh
---
hw
a similar check for stage-2 against effective PA.
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 1ce706bf94
the correct stage set from the page table walk.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 84cd314b33..d052a2ba24 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
in case of errors.
- smmuv3_translate(), now calls smmuv3_do_translate() for
translation while the rest is the same.
Also, add stage in trace_smmuv3_translate_success()
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 59 +++
hw/arm/smmuv3.c
to avoid over-aligning in case the iova
is cached with a smaller granule, the TLB lookup will align the iova
anyway for each granule and level, and the page table walker doesn't
consider the page offset bits.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 64
Soon, smmuv3_do_translate() will be used to translate the CD and the
TTBx, instead of re-writting the same logic to convert the returned
cached entry to an address, add a new macro CACHED_ENTRY_TO_ADDR.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 3
-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 10 +-
hw/arm/smmuv3.c | 4 ++--
hw/arm/trace-events | 18 +-
include/hw/arm/smmu-common.h | 14 +++---
4 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/hw/arm/smmu
Hi Jean,
On Tue, Jul 09, 2024 at 02:00:04PM +0100, Jean-Philippe Brucker wrote:
> Hi Mostafa,
>
> On Tue, Jul 09, 2024 at 07:12:59AM +, Mostafa Saleh wrote:
> > > In this case I think we're reporting InputAddr as the CD address, but it
> > > should be the IOVA
Hi Jean,
On Tue, Jul 09, 2024 at 06:13:45PM +0100, Jean-Philippe Brucker wrote:
> On Tue, Jul 09, 2024 at 07:14:19AM +0000, Mostafa Saleh wrote:
> > Hi Jean,
> >
> > On Thu, Jul 04, 2024 at 07:12:35PM +0100, Jean-Philippe Brucker wrote:
> > > On Mon, Jul 01, 202
Hi Eric,
On Mon, Jul 08, 2024 at 07:09:02PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 7/4/24 20:36, Jean-Philippe Brucker wrote:
> > On Mon, Jul 01, 2024 at 11:02:40AM +, Mostafa Saleh wrote:
> >> QEMU doesn's support memory attributes, so FWB is NOP, this
> &g
Hi Jean,
On Thu, Jul 04, 2024 at 07:36:58PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:40AM +0000, Mostafa Saleh wrote:
> > QEMU doesn's support memory attributes, so FWB is NOP, this
> > might change in the future if memory attributre would be supported.
Hi Jean,
On Thu, Jul 04, 2024 at 07:35:03PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:37AM +0000, Mostafa Saleh wrote:
> > IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2
> > SMMU instances we consider the input address as the IOVA, but w
Hi Jean,
On Thu, Jul 04, 2024 at 07:32:36PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:34AM +0000, Mostafa Saleh wrote:
> > With nesting, we would need to invalidate IPAs without
> > over-invalidating stage-1 IOVAs. This can be done by
> > distinguis
Hi Eric,
On Mon, Jul 08, 2024 at 05:19:59PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 7/1/24 13:02, Mostafa Saleh wrote:
> > When nested translation is requested, do the following:
> >
> > - Translate stage-1 table address IPA into PA through stage-2.
> &g
Hi Jean,
On Thu, Jul 04, 2024 at 07:31:10PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:33AM +0000, Mostafa Saleh wrote:
> > When nested translation is requested, do the following:
> >
> > - Translate stage-1 table address IPA into PA through sta
Hi Jean,
On Thu, Jul 04, 2024 at 07:12:35PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:31AM +0000, Mostafa Saleh wrote:
> > In the next patch, combine_tlb() will be added which combines 2 TLB
> > entries into one for nested translations, which choo
Hi Jean,
On Thu, Jul 04, 2024 at 07:08:43PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:30AM +0000, Mostafa Saleh wrote:
> > According to ARM SMMU architecture specification (ARM IHI 0070 F.b),
> > In "5.2 Stream Table Entry":
> > [51:6
Hi Jean,
On Thu, Jul 04, 2024 at 07:02:00PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:25AM +0000, Mostafa Saleh wrote:
> > The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the
> > class of events faults as:
> >
> > CLASS:
Hi Eric,
On Mon, Jul 08, 2024 at 07:30:34PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 7/1/24 13:02, Mostafa Saleh wrote:
> > Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
> > but not nested instances.
> > This patch series adds support for n
for stage-1 only (ASID >= 0)
Also, rework trace events to reflect the new implementation.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 16
hw/arm/smmuv3.c | 28 ++--
hw/arm/trace-events | 6 --
include/hw/
ad.
- F_ACCESS: Same as an address translation.
- F_TRANSLATION: Same as an address translation.
- F_WALK_EABT: Same as an address translation.
These are already implemented in the PTW logic, so no extra handling
required.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
--
QEMU doesn's support memory attributes, so FWB is NOP, this
might change in the future if memory attributre would be supported.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 807f26f2da
Everything is in place, consolidate parsing of STE cfg and setting
translation stage.
Advertise nesting if stage requested is "nested".
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 35 ++-
1 file changed, 26 insertions(+), 9 deletions(-)
diff
the correct stage set from the page table walk.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 36eb6f514a..6c18dc0acf 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
, the combination logic
chooses:
- tg and level from the entry which has the smallest addr_mask.
- Based on that the iova that would be cached is recalculated.
- Translated_addr is chosen from stage-2.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 37
behaviour.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 20 +---
hw/arm/smmuv3.c | 2 +-
include/hw/arm/smmu-common.h | 2 +-
3 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index
IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2
SMMU instances we consider the input address as the IOVA, but when
nesting is used, we can't mix stage-1 and stage-2 addresses, so for
nesting only stage-1 is considered the IOVA and would be notified.
Signed-off-by: Mostafa Saleh
in case of errors.
- smmuv3_translate(), now calls smmuv3_do_translate() for
translation while the rest is the same.
Also, add stage in trace_smmuv3_translate_success()
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 59 +++
hw/arm/smmuv3.c
, as ptw_info is initialised by zero in
smmuv3_translate().
Fixes: e703f7076a “hw/arm/smmuv3: Add page table walk for stage-2”
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 10 ++
hw/arm/smmuv3.c | 4
2 files changed, 10 insertions(+), 4 deletions
-1 table address can be cached in there.
Also in smmu_ptw() a separate path used for nesting to simplify the
code, although some logic can be combined.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 72 +++-
include/hw/arm/smmu-common.h | 2 +-
2
, currently, the lookup for an IOVA is done with input stage
granule, which is stage-1 for nested configuration, which will not
work with the above logic.
This patch reworks lookup in that case, so it falls back to stage-2
granule if no entry is found using stage-1 granule.
Signed-off-by: Mostafa Saleh
ASIDs.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 47
hw/arm/smmuv3.c | 23 --
hw/arm/trace-events | 2 +-
include/hw/arm/smmu-common.h | 3 ++-
4 files changed, 66
-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 10 +-
hw/arm/smmuv3.c | 4 ++--
hw/arm/trace-events | 18 +-
include/hw/arm/smmu-common.h | 14 +++---
4 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/hw/arm/smmu
Soon, smmuv3_do_translate() will be used to translate the CD and the
TTBx, instead of re-writting the same logic to convert the returned
cached entry to an address, add a new macro CACHED_ENTRY_TO_ADDR.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 3 +--
include/hw/arm/smmu
48bits.
- Remove unused functions/macros: pa_range/MAX_PA.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 7 ---
hw/arm/smmuv3-internal.h | 13 -
hw/arm/smmuv3.c | 35 ---
3 files changed, 32 insertions
means CD and not
IN (0b10).
While at it, add an enum for class as it would be used for nesting.
However, at the moment stage-1 and stage-2 use the same class values.
Fixes: 9bde7f0674 “hw/arm/smmuv3: Implement translate callback”
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm
and BIT(1) is
stage-2 and both is nested.
- Tracing, as stage is printed as int.
Reviewed-by: Eric Auger
Reviewed-by: Alex Bennée
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 14 +++---
hw/arm/smmuv3.c | 15 ---
include/hw/arm/smmu-common.h | 11
a similar check for stage-2 against effective PA.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 1ce706bf94..eb2356bc35 100644
--- a/hw/arm/smmu-common.c
- Fixed TLB issue with large stage-1 reported by Julian.
- Cap the OAS to 48 bits as PTW doesn’t support 52 bits.
- Fix ASID/VMID representation in some contexts as 16 bits while
they can be -1
- Increase visibility in trace points
Mostafa Saleh (19):
hw/arm/smmu-common: Add missing size chec
Hi Eric,
On Tue, May 21, 2024 at 11:32:48AM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:24, Mostafa Saleh wrote:
> > Add property that sets the OAS of the SMMU, this in not used in this
> > patch.
> >
> > Signed-off-by: Mostafa Saleh
> >
Hi Julien,
On Fri, May 24, 2024 at 06:22:12PM +0100, Julien Grall wrote:
> Hi Mostafa,
>
> On 29/04/2024 04:24, Mostafa Saleh wrote:
> > Use the new SMMU property to make the SMMU OAS match the CPU PARANGE.
> > That's according to SMMU manual ARM IHI 0070F.b: > 6
Hi Eric,
On Mon, May 20, 2024 at 03:30:58PM +0200, Eric Auger wrote:
>
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > QEMU doesn's support memory attributes, so FWB is NOP, this
> > might change in the future if memory attributre would be supported.
> if mem
Hi Eric,
On Mon, May 20, 2024 at 03:16:40PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > Everything is in place, add the last missing bits:
> > - Handle fault checking according to the actual PTW event and not the
> > the t
Hi Eric,
On Mon, May 20, 2024 at 12:37:55PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > IOMMUTLBEvent only understands IOVA, for stage-2 only SMMUs keep
> > the implementation, while only notify for stage-1 invalidation
&
Hi Eric,
On Mon, May 20, 2024 at 12:24:22PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > Some commands need rework for nesting, as they used to assume S1
> > and S2 are mutually exclusive:
> >
> > - CMD_TLBI_NH_ASID: Cons
Hi Eric,
On Mon, May 20, 2024 at 11:48:18AM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > When nested translation is requested, do the following:
> >
> > - Translate stage-1 IPA using stage-2 to a physical address.
> sta
On Wed, May 22, 2024 at 1:44 PM Mostafa Saleh wrote:
>
> Hi Eric,
>
> On Mon, May 20, 2024 at 10:20:43AM +0200, Eric Auger wrote:
> > Hi Mostafa,
> > On 5/16/24 17:20, Mostafa Saleh wrote:
> > > Hi Eric,
> > >
> > > On Wed, May 15, 2024 at 03
Hi Eric,
Sorry no updates for a while, I have been away for some time,
but I am now back to working on this.
On Wed, May 15, 2024 at 02:41:42PM +0200, Eric Auger wrote:
> Hi Mostafa,
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > ASID and VMID used to be uint16_t in the translation con
Hi Eric,
On Tue, May 21, 2024 at 10:47 AM Eric Auger wrote:
>
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
> > but not nested instances.
> > This patch series adds support fo
Hi Eric,
On Mon, May 20, 2024 at 10:27:50AM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > In the previous patch, comine_tlb() was added which combines 2 TLB
> > entries into one, which chooses the granule and level from t
Hi Eric,
On Mon, May 20, 2024 at 10:20:43AM +0200, Eric Auger wrote:
> Hi Mostafa,
> On 5/16/24 17:20, Mostafa Saleh wrote:
> > Hi Eric,
> >
> > On Wed, May 15, 2024 at 03:48:05PM +0200, Eric Auger wrote:
> >> Hi Mostafa,
> >>
> >> On 4/29/2
Hi Eric,
On Wed, May 15, 2024 at 03:15:02PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > According to ARM SMMU architecture specification (ARM IHI 0070 F.b),
> > In "5.2 Stream Table Entry":
> > [51:6] S1ContextPtr
&g
Hi Eric,
On Wed, May 15, 2024 at 03:54:36PM +0200, Eric Auger wrote:
>
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > In the previous patch, comine_tlb() was added which combines 2 TLB
> combine
Will do.
> > entries into one, which chooses the granule and level fro
Hi Eric,
On Wed, May 15, 2024 at 03:48:05PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > This patch adds support for nested(combined) TLB entries.
> space between nested and (.
Will do.
> > The main function combine_tlb() is not u
Hi Eric,
On Wed, May 15, 2024 at 02:27:45PM +0200, Eric Auger wrote:
> Hi Mostafa,
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the
> > class of events faults as:
> >
> > CLASS: The class of the o
Hi Eric,
On Mon, May 13, 2024 at 01:47:44PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > For the following events (ARM IHI 0070 F.b - 7.3 Event records):
> > - F_TRANSLATION
> > - F_ACCESS
> > - F_PERMISSION
> >
new macro is introduced CACHED_ENTRY_TO_ADDR.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 76 ++--
include/hw/arm/smmu-common.h | 3 ++
2 files changed, 66 insertions(+), 13 deletions(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index cc6170
a similar check for stage-2 against effective PA.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 1ce706bf94..eb2356bc35 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu
as (65536),
this was not an issue as nesting was not supported and no
commands/lookup targets both.
With nesting, it’s critical to get this right as translation must be
tagged correctly with ASID/VMID, and with ASID=-1 meaning stage-2.
Represent ASID/VMID everywhere as int.
Signed-off-by: Mostafa Saleh
for stage-1 only (ASID >= 0)
Also, rework trace events to reflect the new implementation.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 36 +---
hw/arm/smmuv3.c | 31 +--
hw/arm/trace-events |
change the SMMU OAS, but refactors the code to
make it easier to do that:
- Rely everywhere on IDR5 for reading OAS instead of using the macro so
it is easier just change IDR5 and it propagages correctly.
- Remove unused functions/macros: pa_range/MAX_PA
Signed-off-by: Mostafa Saleh
---
hw/arm
Add property that sets the OAS of the SMMU, this in not used in this
patch.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3-internal.h | 3 ++-
hw/arm/smmuv3.c | 29 -
include/hw/arm/smmuv3.h | 1 +
3 files changed, 31 insertions(+), 2 deletions(-)
diff
and BIT(1) is
stage-2 and both is nested.
- Tracing, as stage is printed as int.
Signed-off-by: Mostafa Saleh
Reviewed-by: Eric Auger
---
hw/arm/smmu-common.c | 14 +++---
hw/arm/smmuv3.c | 15 ---
include/hw/arm/smmu-common.h | 11 +--
3 files
Everything is in place, add the last missing bits:
- Handle fault checking according to the actual PTW event and not the
the translation stage.
- Consolidate parsing of STE cfg and setting translation stage.
Advertise nesting if stage requested is "nested".
Signed-off-by: Mos
ASIDs.
Signed-off-by: Mostafa Saleh
Reviewed-by: Eric Auger
---
hw/arm/smmu-common.c | 47
hw/arm/smmuv3.c | 23 --
hw/arm/trace-events | 2 +-
include/hw/arm/smmu-common.h | 3 ++-
4 files changed, 66
in there.
Also in smmu_ptw() a separate path used for nesting to simplify the
code, although some logic can be combined.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 67 ++--
include/hw/arm/smmu-common.h | 2 +-
2 files changed, 58 insertions
IOMMUTLBEvent only understands IOVA, for stage-2 only SMMUs keep
the implementation, while only notify for stage-1 invalidation
in case of nesting.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 23 +++
hw/arm/trace-events | 2 +-
2 files changed, 16 insertions
configuration is done with
stage-1 granule, this patch reworks lookup in that case, so it falls
back to stage-2 granule if no entry is found using stage-1 granule.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions
QEMU doesn's support memory attributes, so FWB is NOP, this
might change in the future if memory attributre would be supported.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 88f6473d33
means CD and not
IN (0b10).
While at it, add an enum for class as it would be used for nesting.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3-internal.h | 6 ++
hw/arm/smmuv3.c | 6 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw
in case of errors.
- smmuv3_translate(), now calls smmuv3_do_translate() for
translation while the rest is the same.
Also, add stage in trace_smmuv3_translate_success()
Signed-off-by: Mostafa Saleh
Reviewed-by: Eric Auger
---
hw/arm/smmu-common.c | 59 +++
hw/arm/smmuv3.c
Use the new SMMU property to make the SMMU OAS match the CPU PARANGE.
That's according to SMMU manual ARM IHI 0070F.b:
6.3.6 SMMU_IDR5, OAS must match the system physical address size.
Signed-off-by: Mostafa Saleh
---
hw/arm/virt.c | 14 --
target/arm/cpu.h | 2
-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 10 ++
hw/arm/smmuv3.c | 4
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index eb2356bc35..8a8c718e6b 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -448,7
VMID/ASID instead of an extra key.
- Fixed TLB issue with large stage-1 reported by Julian.
- Cap the OAS to 48 bits as PTW doesn’t support 52 bits.
- Fix ASID/VMID representation in some contexts as 16 bits while
they can be -1
- Increase visibility in trace points
Mostafa Saleh (18):
hw/arm/smmu-common
is used, the combination logic
chooses:
- tg and level from the entry which has the smallest addr_mask.
- Based on that the iova that would be cached is recalculated.
- Translated_addr is chosen from stage-2.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 32
Hi Eric,
On Thu, Apr 18, 2024 at 04:48:39PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/8/24 16:08, Mostafa Saleh wrote:
> > Some commands need rework for nesting, as they used to assume S1
> > and S2 are mutually exclusive:
> >
> > - CMD_TLBI_NH_ASID: Cons
Hi Eric,
On Thu, Apr 18, 2024 at 03:54:01PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/8/24 16:08, Mostafa Saleh wrote:
> > When nested translation is requested, do the following:
> >
> > - Translate stage-1 IPA using stage-2 to a physical address.
> > -
Hi Eric,
On Thu, Apr 18, 2024 at 02:51:59PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/8/24 16:08, Mostafa Saleh wrote:
> > According to the user manual (ARM IHI 0070 F.b),
> s/user manual/ARM SMMU architecture specification
> > In "5.2 Stream Table Ent
Hi Eric,
On Thu, Apr 18, 2024 at 08:11:06PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/8/24 16:08, Mostafa Saleh wrote:
> > Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
> > but not nested instances.
> > This patch series adds support for n
ASIDs.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 47
hw/arm/smmuv3.c | 23 --
hw/arm/trace-events | 2 +-
include/hw/arm/smmu-common.h | 3 ++-
4 files changed, 66 insertions(+), 9 deletions
Everything is in place, add the last missing bits:
- Handle fault checking according to the actual PTW event and not the
the translation stage.
- Consolidate parsing of STE cfg and setting translation stage.
Advertise nesting if stage requested is "nested".
Signed-off-by: Mos
change the SMMU OAS, but refactors the code to
make it easier to do that:
- Rely everywhere on IDR5 for reading OAS instead of using the macro so
it is easier just change IDR5 and it propagages correctly.
- Remove unused functions/macros: pa_range/MAX_PA
Signed-off-by: Mostafa Saleh
---
hw/arm
Add property that sets the OAS of the SMMU, this in not used in this
patch.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3-internal.h | 3 ++-
hw/arm/smmuv3.c | 29 -
include/hw/arm/smmuv3.h | 1 +
3 files changed, 31 insertions(+), 2 deletions(-)
diff
for stage-1 only (ASID >= 0)
Also, rework trace events to reflect the new implementation.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 36 +---
hw/arm/smmuv3.c | 31 +--
hw/arm/trace-events |
IOMMUTLBEvent only understands IOVA, for stage-2 only SMMUs keep
the implementation, while only notify for stage-1 invalidation
in case of nesting.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 23 +++
hw/arm/trace-events | 2 +-
2 files changed, 16 insertions
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