From: Harsh Prateek Bora
spapr_exit_nested and spapr_get_pate_nested_hv contains code which
is specific to nested-hv API. Isolating code flows based on API
helps extending it to be used with different API as well.
Suggested-by: Nicholas Piggin
Reviewed-by: Nicholas Piggin
Signed-off-by: Harsh
routines for state
exchange of each of the nested guest state elements for which get/set state
should be supported by the API.
[amachhiw: set the PCR whenever logical PVR is set]
Reviewed-by: Nicholas Piggin
Signed-off-by: Michael Neuling
Signed-off-by: Shivaprasad G Bhat
Signed-off-by: Amit
From: Harsh Prateek Bora
Adding initial documentation about Nested PAPR API to describe the set
of APIs and its usage. Also talks about the Guest State Buffer elements
and it's format which is used between L0/L1 to communicate L2 state.
Reviewed-by: Nicholas Piggin
Signed-off-by: Michael
From: BALATON Zoltan
Remove check for !defined(CONFIG_USER_ONLY) as this is already within
an #ifndef CONFIG_USER_ONLY block.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 4 ++--
1 file changed, 2 insertions
-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 118 +--
1 file changed, 63 insertions(+), 55 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 98952de267..56a5fe7f3b 100644
--- a/target/ppc
.
[amachhiw: support for p9 compat mode and return register bug fixes]
Reviewed-by: Nicholas Piggin
Signed-off-by: Michael Neuling
Signed-off-by: Amit Machhiwal
Signed-off-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_nested.c | 115
From: Harsh Prateek Bora
For nested PAPR API, we use SpaprMachineStateNestedGuest struct to store
partition table info, use the same in spapr_get_pate_nested() via
helper.
Reviewed-by: Nicholas Piggin
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
Signed-off-by: Nicholas
Prevent guest state modifying the MSR[ME] bit. Per ISA:
An attempt to modify MSR[ME] in privileged but non-hypervisor state
is ignored (i.e., the bit is not changed).
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 5 +
1 file changed, 5
of these wrappers. This avoids one indirection and entirely
compiles out the switch without TARGET_PPC64.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 67 +---
1 file changed, 28
Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 67 --
hw/ppc/spapr.c | 1 +
2 files changed, 66 insertions(+), 2 deletions
Reviewed-by: Bernhard Beschow
Reviewed-by: Nicholas Piggin
Co-authored-by: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
MAINTAINERS | 1 +
docs/system/ppc/amigang.rst | 161
From: BALATON Zoltan
Use #ifdef, #ifndef for brevity and add comments to #endif that are
more than a few lines apart for clarity.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 49
-by: Nicholas Piggin
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_nested.c | 8
include/hw/ppc/spapr.h| 3 ++-
include/hw/ppc/spapr_nested.h | 5 +
3 files changed, 11 insertions(+), 5 deletions
From: BALATON Zoltan
Improve readability by shortening some long comments, removing
comments that state the obvious and dropping some empty lines so they
don't distract when reading the code.
Acked-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target
From: Harsh Prateek Bora
Most of the nested code has already been moved to spapr_nested.c
This logic inside spapr_get_pate is related to nested guests and
better suited for spapr_nested.c, hence moving there.
Reviewed-by: Nicholas Piggin
Signed-off-by: Harsh Prateek Bora
Signed-off
From: BALATON Zoltan
Concatenate #if blocks that are ending then beginning on the next line
again.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 15 ++-
1 file changed, 2 insertions(+), 13 deletions
The initial MSR state for the OpenFirmware binding specifies
MSR[ME] and MSR[FP] are set.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc
This allows different pa-features for powernv8/9/10.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index aa9786e970
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 2 --
target/ppc/cpu-models.c | 4
target/ppc/cpu_init.c | 7 ++-
target/ppc/kvm.c
From: Caleb Schlossin
Big (SMT8) cores have a complicated function to map the core, thread ID
to pervasive topology (PIR). Fix this for power8, power9, and power10.
Reviewed-by: Cédric Le Goater
Signed-off-by: Caleb Schlossin
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 71
TCG does not support copy/paste instructions. Remove it from
ibm,pa-features. This has never been implemented under TCG or
practically usable under KVM, so it won't be missed.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 8 ++--
1 file changed, 6
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/insn32.decode | 26
target/ppc/translate.c | 136 -
target/ppc/translate/fixedpoint-impl.c.inc | 70 +++
3 files
"MMR" and "SPR SO" are not implemented in POWER9, so clear those bits.
HTM is not set by default, and only later if the cap is set, so remove
the comment that suggests otherwise.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 10 +-
Fix an off by one bug.
Fixes: 1b53948ff8f70 ("target/ppc: Use GDBFeature for dynamic XML")
Reviewed-by: Akihiko Odaki
Signed-off-by: Nicholas Piggin
---
target/ppc/gdbstub.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/ppc/gdbstub.c b/target/ppc
declared in byte 72,
bit 0 (BE).
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Benjamin Gray
[npiggin: reword title and changelog, adjust a few bits]
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw
cated").
Take to opportunity to also deprecate the 2.12 machines.
Acked-by: Nicholas Piggin
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
docs/about/deprecated.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/about/deprecated.rst b/
hcall.
spapr: nested: Introduce cap-nested-papr for Nested PAPR API
Madhavan Srinivasan (1):
target/ppc: Add power10 pmu SPRs
Nicholas Piggin (10):
target/ppc: Fix GDB SPR regnum indexing
target/ppc: Prevent supervisor from modifying MSR[ME]
spapr: set MSR[ME
POWER10 hardware implements a degenerate transactional memory facility
in POWER8/9 PCR compatibility modes to permit migration from older
CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model
should not support it.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
On Wed Feb 28, 2024 at 1:08 AM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back
On Tue Mar 12, 2024 at 8:36 PM AEST, Nicholas Piggin wrote:
> On Tue Mar 12, 2024 at 7:28 PM AEST, Bernhard Beschow wrote:
> >
> >
> > Am 9. März 2024 11:34:56 UTC schrieb BALATON Zoltan :
> > >On Thu, 29 Feb 2024, BALATON Zoltan wrote:
> > >>
On Wed Mar 13, 2024 at 12:01 AM AEST, Richard Henderson wrote:
> On 3/11/24 23:36, Nicholas Piggin wrote:
[snip]
> >
> > #define FPU_HELPER(name, op, flags_handler) \
> > float64 helper_##name(CPUPPCState *env, float
On Tue Mar 12, 2024 at 10:39 PM AEST, Marc-André Lureau wrote:
> Hi
>
> On Mon, Mar 11, 2024 at 9:44 PM Nicholas Piggin wrote:
> >
> > chardev events to a muxed device don't get recorded because e.g.,
> > qemu_chr_be_write() checks whether the base device
On Tue Mar 12, 2024 at 11:33 PM AEST, Alex Bennée wrote:
> Nicholas Piggin writes:
>
> > This reverts commit 1f881ea4a444ef36a8b6907b0b82be4b3af253a2.
> >
> > That commit causes reverse_debugging.py test failures, and does
> > not seem to solve the root cause of the
On Tue Mar 12, 2024 at 11:24 PM AEST, Alex Bennée wrote:
> Nicholas Piggin writes:
>
> > (H)DEC and PURR get reset before icount does, which causes them to be
> > skewed and not match the init state. This can cause replay to not
> > match the recorded trace e
On Tue Feb 20, 2024 at 6:09 PM AEST, Cédric Le Goater wrote:
> PPC maintainership has been a side activity for the last 2 years and
> it is time to let go some of it now that Nick has taken over.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Cédric Le Goater
> ---
> MAINTA
Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 67 --
hw/ppc/spapr.c | 1 +
2 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 2 --
target/ppc/cpu-models.c | 4
target/ppc/cpu_init.c | 7 ++-
target/ppc/kvm.c
This allows different pa-features for powernv8/9/10.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index aa9786e970..52d964f77a 100644
--- a/hw/ppc/pnv.c
The initial MSR state for the OpenFirmware binding specifies
MSR[ME] and MSR[FP] are set.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc
declared in byte 72,
bit 0 (BE).
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Benjamin Gray
[npiggin: reword title and changelog, adjust a few bits]
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw
TCG does not support copy/paste instructions. Remove it from
ibm,pa-features. This has never been implemented under TCG or
practically usable under KVM, so it won't be missed.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 8 ++--
1 file changed, 6
"MMR" and "SPR SO" are not implemented in POWER9, so clear those bits.
HTM is not set by default, and only later if the cap is set, so remove
the comment that suggests otherwise.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 10 +-
This accounts for comments from v1, and drops the attn and
checkstop patches. Will try again next release for those since
they probably fell off peoples' radar this time.
Thanks,
Nick
Benjamin Gray (1):
ppc/spapr: Add pa-features for POWER10 machines
Nicholas Piggin (9):
ppc: Drop support
Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 2 +-
hw/ppc/spapr.c | 14 ++
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0b47b92baa..aa9786e970 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -150,7 +150,7 @@ static void
Prevent guest state modifying the MSR[ME] bit. Per ISA:
An attempt to modify MSR[ME] in privileged but non-hypervisor state
is ignored (i.e., the bit is not changed).
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 5 +
1 file changed, 5
POWER10 hardware implements a degenerate transactional memory facility
in POWER8/9 PCR compatibility modes to permit migration from older
CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model
should not support it.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
On Tue Mar 12, 2024 at 10:11 PM AEST, Harsh Prateek Bora wrote:
> Hi Nick,
>
> On 3/12/24 17:21, Nicholas Piggin wrote:
> > On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
> >> Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
> >>
ets nip back but correctly set nip to
> pc_next so we don't have to patch this in the exception handlers.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/excp_helper.c | 43 ++--
> target/ppc/translate.c |
> to use it.
>
> The gen_exception() and gen_exception_nip() functions are similar so
> remove code duplication from those too while at it.
>
> Suggested-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
Thanks for doing this one
Reviewed-by: Nicholas Piggin
> -
t; This is becuase, no read/write call-backs are registered for
> these SPRs. Add support to register generic read/write
> functions to these power10 pmu sprs to fix it.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Madhavan Srinivasan
> ---
> target/ppc/cpu.h | 6
return;
> +} else {
> +spapr->nested.api = NESTED_API_PAPR;
> +}
> +
> +} else if (kvm_enabled()) {
> + /*
> + * this gets executed in L1 qemu when L2 is launched,
> + * needs kvm-hv support in L1 kernel.
> + */
>
On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
> Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
> API for nested guests. This new API is to enable support for KVM on PowerVM
> and the support in Linux kernel has already merged upstream.
>
> Signed-off-by:
>
> Signed-off-by: Michael Neuling
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/cpu.h | 2 +
> hw/ppc/ppc.c | 10 ++
> hw/ppc/spapr_nested.c | 334 ++
> 3 files changed
hineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState
> *spapr,
> + target_ulong lpid);
Why is this made non-static? Doesn't seem to be needed in later patches
either? Other than that,
Reviewed-by: Nicholas Piggin
> #end
> Signed-off-by: Shivaprasad G Bhat
> Signed-off-by: Amit Machhiwal
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr_nested.h | 312 ++
> hw/ppc/spapr_nested.c | 486 +-
&g
; Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr.h| 3 +
> include/hw/ppc/spapr_nested.h | 23 +++
> hw/ppc/spapr_nested.c | 268 ++
> 3 files changed, 294 insertions(+)
>
> d
PAPR API.
>
> Signed-off-by: Harsh Prateek Bora
> Suggested-by: Nicholas Piggin
I still have concerns with exactly how registers are saved and restored,
but it's not necessarily a new problem with v2, and not so much
fundamental design flow more of verifying details so I'm inclined to
for a guest gets deallocated on guest delete.
>
> Signed-off-by: Michael Neuling
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr.h| 2 ++
> include/hw/ppc/spapr_nested.h | 8 +
> h
capabilities that the Host Partition supports and may use.
>
> [amachhiw: support for p9 compat mode and return register bug fixes]
>
> Signed-off-by: Michael Neuling
> Signed-off-by: Amit Machhiwal
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
he nested guest being deleted. It also supports deleting all nested
> guests at once using a deleteAll flag.
>
> Signed-off-by: Michael Neuling
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr.h| 4 +-
> include/hw/pp
sh Prateek Bora
> Suggested-by: Nicholas Piggin
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr_nested.h | 3 +++
> hw/ppc/spapr.c| 6 +-
> hw/ppc/spapr_nested.c | 25 ++---
> 3 files changed, 30 insertions(+), 4 deletio
> Signed-off-by: Michael Neuling
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> docs/devel/nested-papr.txt | 119 +
> 1 file changed, 119 insertions(+)
> create mode 100644 docs/devel/nested-papr.txt
>
> diff
as being incompatible with rr?
Thanks,
Nick
>
> On 11.03.2024 20:40, Nicholas Piggin wrote:
> > Using virtual time for announce ensures that guest visible effects
> > are deterministic and don't break replay.
> >
> > Signed-off-by: Nicholas Piggin
> > ---
> &
On Tue Mar 12, 2024 at 7:00 PM AEST, Pavel Dovgalyuk wrote:
> On 11.03.2024 20:40, Nicholas Piggin wrote:
> > record makes an initial snapshot when the machine is created, to enable
> > reverse-debugging. Often the issue being debugged appears near the end of
> > the trac
On Tue Mar 12, 2024 at 6:56 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 14:18, Nicholas Piggin wrote:
> > On Tue Mar 12, 2024 at 4:38 PM AEST, Harsh Prateek Bora wrote:
> >> Hi Nick,
> >>
> >> One minor comment below:
> &g
helpful.
Thanks,
Nick
>
> >
> >> Regards,
> >> BALATON Zoltan
> >>
> >>> Co-authored-by: Bernhard Beschow
> >>> Signed-off-by: BALATON Zoltan
> >>> Reviewed-by: Nicholas Piggin
> >>> Tested-by: Bernhard Besc
On Tue Mar 12, 2024 at 7:34 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > From: Benjamin Gray
> >
> > Add POWER10 pa-features entry.
> >
> > Notably DEXCR and and [P]HASHST/[P]HASHCHK instruction support is
>
&g
On Tue Mar 12, 2024 at 8:03 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
> >
> > Signed-off-by: Nicholas Piggin
>
> It would be good to mention PAPR se
On Tue Mar 12, 2024 at 7:59 PM AEST, BALATON Zoltan wrote:
> On Tue, 12 Mar 2024, Nicholas Piggin wrote:
> > On Tue Mar 12, 2024 at 7:07 AM AEST, BALATON Zoltan wrote:
> >> On Mon, 11 Mar 2024, Philippe Mathieu-Daudé wrote:
> >>> On 11/3/24 19:51, Nicholas Piggin wro
On Tue Mar 12, 2024 at 8:27 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > Prevent guest state modifying the MSR[ME] bit. Per ISA:
> >
> >An attempt to modify MSRME in privileged but non-hypervisor state is
>
&g
;frc);
> +get_fpr(t2, a->frb);
> +helper(t3, tcg_env, t0, t1, t2);
> +set_fpr(a->frt, t3);
> +gen_compute_fprf_float64(t3);
> +if (unlikely(a->rc != false)) {
This reads better without the double negative. I.e., just
if (unlikely(a->rc
On Thu Mar 7, 2024 at 9:03 PM AEST, Chinmay Rath wrote:
> This patch moves the below instructions to decodetree specification :
>
> f{add, sub, mul, div, re, rsqrte, madd, msub, nmadd, nmsub}[s][.] : A-form
> ft{div, sqrt} : X-form
>
>
On Tue Mar 12, 2024 at 2:55 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 10:20, Harsh Prateek Bora wrote:
> >
> >
> > On 3/12/24 00:21, Nicholas Piggin wrote:
> >> The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
> >> a
On Tue Mar 12, 2024 at 6:10 PM AEST, Harsh Prateek Bora wrote:
> Hi Nick,
>
> One query/comment below:
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > POWER10 hardware implements a degenerate transactional memory facility
> > in POWER8/9 PCR compatibility modes to
On Tue Mar 12, 2024 at 6:06 PM AEST, Cédric Le Goater wrote:
> On 3/11/24 19:51, Nicholas Piggin wrote:
> > Copy the pa-features arrays from spapr, adjusting slightly as
> > described in comments.
> >
> > Cc: "Cédric Le Goater"
> > Cc: "Fréd
On Tue Mar 12, 2024 at 4:38 PM AEST, Harsh Prateek Bora wrote:
> Hi Nick,
>
> One minor comment below:
>
> On 2/24/24 13:03, Nicholas Piggin wrote:
> > PPC_VIRTUAL_HYPERVISOR_GET_CLASS is used in critical operations like
> > interrupts and TLB misses and is quite costl
On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
> There is an existing Nested-HV API to enable nested guests on powernv
> machines. However, that is not supported on pseries/PowerVM LPARs.
> This patch series implements required hcall interfaces to enable nested
> guests with KVM on
bool pre_3_0_migration; /* older
> machine don't know about SpaprCpuState */
Acked-by: Nicholas Piggin
I can merge this via the PPC tree.
Thanks,
Nick
> ---
> docs/about/deprecated.rst | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/docs/abo
On Tue Mar 12, 2024 at 4:56 AM AEST, Daniel P. Berrangé wrote:
> On Mon, Mar 11, 2024 at 06:46:53PM +0100, Philippe Mathieu-Daudé wrote:
> > Hi,
> >
> > On 14/12/23 19:17, Cédric Le Goater wrote:
> > > pseries machines before version 2.11 have undergone many changes to
> > > correct issues,
On Tue Mar 12, 2024 at 7:07 AM AEST, BALATON Zoltan wrote:
> On Mon, 11 Mar 2024, Philippe Mathieu-Daudé wrote:
> > On 11/3/24 19:51, Nicholas Piggin wrote:
> >> From: Benjamin Gray
> >>
> >> Add POWER10 pa-features entry.
> >>
> >> Notably
On Tue Mar 12, 2024 at 6:05 AM AEST, Philippe Mathieu-Daudé wrote:
> On 11/3/24 19:51, Nicholas Piggin wrote:
> > From: Benjamin Gray
> >
> > Add POWER10 pa-features entry.
> >
> > Notably DEXCR and and [P]HASHST/[P]HASHCHK instruction support is
> > adv
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
any use in QEMU. Remove them.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 2 --
target/ppc/cpu-models.c | 4
target/ppc/cpu_init.c | 7 ++-
target/ppc/kvm.c| 11 ---
4 files
is separately declared in byte 72,
bit 0 (BE).
Signed-off-by: Benjamin Gray
[npiggin: reword title and changelog, adjust a few bits]
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 50523ead25..f3b01b0801 100644
--- a/hw/ppc
TCG does not support copy/paste instructions. Remove it from
ibm,pa-features. This has never been implemented under TCG or
practically usable under KVM, so it won't be missed.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff
SAO is a page table attribute that strengthens the memory ordering of
accesses. QEMU with MTTCG does not implement this, so clear it in
ibm,pa-features. This is an obscure feature that has been removed from
POWER10 ISA v3.1, there isn't much concern with removing it.
Signed-off-by: Nicholas
This allows different pa-features for powernv8/9/10.
Cc: "Cédric Le Goater"
Cc: "Frédéric Barrat"
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c
Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.
Cc: "Cédric Le Goater"
Cc: "Frédéric Barrat"
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 67 --
hw/ppc/spapr.c | 1 +
2 files ch
, which should be good
enough for QEMU debugging.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 16 +++-
target/ppc/helper.h | 4 ++
target/ppc/cpu_init.c| 82 +---
target/ppc/excp_helper.c | 59
Change the logging not to print to stderr as well, because a
checkstop is a guest error (or perhaps a simulated machine error)
rather than a QEMU error, so send it to the log.
Update the checkstop message, and log CPU registers too.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c
Benjamin Gray (1):
ppc/spapr: Add pa-features for POWER10 machines
Nicholas Piggin (12):
ppc: Drop support for POWER9 and POWER10 DD1 chips
target/ppc: POWER10 does not have transactional memory
ppc/spapr|pnv: Remove SAO from pa-features
ppc/spapr: Remove copy-paste from pa-features
ppc
"MMR" and "SPR SO" are not implemented in POWER9, so clear those bits.
HTM is not set by default, and only later if the cap is set, so remove
the comment that suggests otherwise.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 10 +-
1 file changed, 5 insert
POWER10 hardware implements a degenerate transactional memory facility
in POWER8/9 PCR compatibility modes to permit migration from older
CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model
should not support it.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 4
checkstop state does not halt the system, interrupts continue to be
serviced, and other CPUs run. Make it stop the machine with
qemu_system_guest_panicked.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff
Prevent guest state modifying the MSR[ME] bit. Per ISA:
An attempt to modify MSRME in privileged but non-hypervisor state is
ignored (i.e., the bit is not changed).
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target
Fix an off by one bug.
Cc: Akihiko Odaki
Cc: Alex Bennée
Fixes: 1b53948ff8f70 ("target/ppc: Use GDBFeature for dynamic XML")
Signed-off-by: Nicholas Piggin
---
target/ppc/gdbstub.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/ppc/gdbstub.c b/
, and it adds a replay test that runs to the end of the
trace, steps back then forward and verifies the pc.
Signed-off-by: Nicholas Piggin
---
tests/avocado/reverse_debugging.py | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/tests/avocado
Add a ppc64 pseries test. IO in SLOF is very slow when running in
record-replay modes, so this this uses guestfish to extract the
kernel and initrd and boot them directly.
Cc: qemu-...@nongnu.org
Signed-off-by: Nicholas Piggin
---
The test takes about double the length of time of aarch64 and
x86
is that related events will not get consumed at the
same points (e.g., reading the clock).
A hang with zero icount always seems to be a symptom of an earlier
problem that has caused the recording to become out of synch with
the execution and consumption of events by replay.
Signed-off-by: Nicholas
Using virtual time for announce ensures that guest visible effects
are deterministic and don't break replay.
Signed-off-by: Nicholas Piggin
---
net/announce.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/announce.c b/net/announce.c
index 9e99044422..70b5d5e822 100644
501 - 600 of 1603 matches
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