On Thu, 17 Dec 2020 14:35:10 PST (-0800), Atish Patra wrote:
On Thu, 2020-12-17 at 14:31 -0800, Palmer Dabbelt wrote:
On Thu, 17 Dec 2020 13:48:26 PST (-0800), Atish Patra wrote:
> Currently, we place the DTB at 2MB from 4GB or end of DRAM which
> ever is
> lesser. However, Linux k
On Thu, 17 Dec 2020 13:48:26 PST (-0800), Atish Patra wrote:
Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
lesser. However, Linux kernel can address only 1GB of memory for RV32.
Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address).
As a
On Thu, 17 Dec 2020 05:58:11 PST (-0800), richard.hender...@linaro.org wrote:
On 12/17/20 12:44 AM, Bin Meng wrote:
What happens if something like ARM big.LITTLE needs to be supported on RISC-V?
I'd say it's the board's job to pass the boot heart.
(Though even big.LITTLE doesn't mix 64 and
was hoping to have some time to sort out :). I just
gave it a quick look, but
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
as it certainly seems better than before.
On Thu, 22 Oct 2020 17:56:38 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Oct 22, 2020 at 4:58 PM Moises Arreola wrote:
Hello everyone, my name is Moses and I'm trying to set up a VM for a risc-v
processor, I'm using the Risc-V Getting Started Guide and on the final step I'm
getting an
On Tue, 20 Oct 2020 08:46:45 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Oct 19, 2020 at 4:17 PM Palmer Dabbelt wrote:
On Tue, 13 Oct 2020 17:17:33 PDT (-0700), Alistair Francis wrote:
> Instead of loading the kernel at a hardcoded start address, let's load
> the kernel at th
ad_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr,
Reviewed-by: Palmer Dabbelt
cpus), "cpu-type", s->cpu_type);
+qdev_prop_set_uint64(DEVICE(>u_cpus), "resetvec", 0x1004);
+
sysbus_realize(SYS_BUS_DEVICE(>e_cpus), _abort);
sysbus_realize(SYS_BUS_DEVICE(>u_cpus), _abort);
/*
@@ -792,6 +799,7 @@ static void sifive_u_soc_realize(Devic
firmware_load_addr, ram_size, NULL);
+
+if (firmware_size > 0) {
+return firmware_load_addr + firmware_size;
}
error_report("could not load firmware '%s'", firmware_filename);
Reviewed-by: Palmer Dabbelt
in specs (or event
meant to be in specs) that have stuck around for quite a while.
Reviewed-by: Palmer Dabbelt
On Wed, 09 Sep 2020 12:00:07 PDT (-0700), Peter Maydell wrote:
On Wed, 9 Sep 2020 at 19:00, Alistair Francis wrote:
On Tue, Sep 8, 2020 at 7:52 AM Peter Maydell wrote:
> ...shouldn't the riscv64-softmmu config have CONFIG_OPENTITAN too?
> The usual principle is that the 64-bit executable can
On Fri, 04 Sep 2020 10:52:06 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Sep 2, 2020 at 12:48 PM Philippe Mathieu-Daudé wrote:
On 9/2/20 8:18 PM, Peter Maydell wrote:
> On Wed, 2 Sep 2020 at 18:03, Philippe Mathieu-Daudé wrote:
>>
>> On 9/2/20 6:49 PM, Peter Maydell wrote:
>>> On Wed, 2
On Wed, 22 Jul 2020 02:15:24 PDT (-0700), frank.ch...@sifive.com wrote:
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 24 ++--
target/riscv/cpu.h | 2 --
2 files changed, 6 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu.c
On Thu, 09 Jul 2020 15:09:18 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Jul 9, 2020 at 3:07 AM Bin Meng wrote:
From: Bin Meng
The reset vector codes are subject to change, e.g.: with recent
fw_dynamic type image support, it breaks oreboot again.
This is a recurring problem, I have
On Thu, 18 Jun 2020 16:18:20 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Jun 18, 2020 at 3:42 PM Palmer Dabbelt wrote:
On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistai...@gmail.com wrote:
> On Thu, May 28, 2020 at 11:13 AM Alistair Francis
wrote:
>>
>> On Thu, May 21,
On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistai...@gmail.com wrote:
On Thu, May 28, 2020 at 11:13 AM Alistair Francis wrote:
On Thu, May 21, 2020 at 8:57 AM Alistair Francis wrote:
>
> On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt wrote:
> >
> > On Thu, 14 May 2020 1
On Fri, 15 May 2020 23:37:44 PDT (-0700), Anup Patel wrote:
We extend RISC-V spike machine to allow creating a multi-socket machine.
Each RISC-V spike machine socket is a set of HARTs and a CLINT instance.
Other peripherals are shared between all RISC-V spike machine sockets.
We also update
On Fri, 15 May 2020 23:37:46 PDT (-0700), Anup Patel wrote:
We extend RISC-V virt machine to allow creating a multi-socket machine.
Each RISC-V virt machine socket is a set of HARTs, a CLINT instance,
and a PLIC instance. Other peripherals are shared between all RISC-V
virt machine sockets. We
uint32_t sip_base;
uint32_t timecmp_base;
@@ -40,9 +41,9 @@ typedef struct SiFiveCLINTState {
uint32_t aperture_size;
} SiFiveCLINTState;
-DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
- uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
-bool provide_rdtime);
+DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
+uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
+uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
enum {
SIFIVE_SIP_BASE = 0x0,
Reviewed-by: Palmer Dabbelt
);
+uint32_t hartid_base, uint32_t num_sources,
+uint32_t num_priorities, uint32_t priority_base,
+uint32_t pending_base, uint32_t enable_base,
+uint32_t enable_stride, uint32_t context_base,
+uint32_t context_stride, uint32_t aperture_size);
#endif
Reviewed-by: Palmer Dabbelt
_E_MACHINE(obj) \
+OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
+
enum {
SIFIVE_E_DEBUG,
SIFIVE_E_MROM,
Reviewed-by: Palmer Dabbelt
On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_e.c | 35 +++
include/hw/riscv/sifive_e.h | 1 +
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_e.c
On Tue, 21 Apr 2020 12:27:50 PDT (-0700), Peter Maydell wrote:
On Tue, 21 Apr 2020 at 20:19, Palmer Dabbelt wrote:
RISC-V Patches for 5.0-rc4
This contains handful of patches that I'd like to target for 5.0. I know it's
a bit
From: Alistair Francis
Split the file into clear machine and SoC sections.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 109 ++--
1 file changed, 55 insertions(+), 54 deletions(-)
diff
From: Alistair Francis
Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 8 +++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index d0ea6803db..
From: Alistair Francis
When doing the fist of a two stage lookup (Hypervisor extensions) don't
set the current protection flags from the second stage lookup of the
base address PTE.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv
The following changes since commit 20038cd7a8412feeb49c01f6ede89e36c8995472:
Update version for v5.0.0-rc3 release (2020-04-15 20:51:54 +0100)
are available in the Git repository at:
g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-rc4
for you to fetch changes up to
(VU) becoming corrupted. This appears to be because it
ends up with write permission in the second stage translation in cases
where we aren't doing a store.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 6 ++
1 file changed
and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
Reviewed-by
On Tue, 21 Apr 2020 10:40:05 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Apr 20, 2020 at 7:17 PM Bin Meng wrote:
On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis wrote:
>
> On Wed, Apr 1, 2020 at 10:39 PM Bin Meng wrote:
> >
> > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng wrote:
> > >
>
On Mon, 23 Mar 2020 19:08:19 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
wrote:
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to
On Thu, 26 Mar 2020 15:44:04 PDT (-0700), Alistair Francis wrote:
This series fixes two bugs in the RISC-V two stage lookup
implementation. This fixes the Hypervisor userspace failing to start.
Alistair Francis (2):
riscv: Don't use stage-2 PTE lookup protection flags
riscv: AND stage-1 and
On Tue, 03 Mar 2020 17:16:59 PST (-0800), Alistair Francis wrote:
The RISC-V spec specifies that when a write happens and the D bit is
clear the implementation will set the bit in the PTE. It does not
describe that the PTE being dirty means that we should provide write
access. This patch removes
Signed-off-by: Palmer Dabbelt
---
.gitlab-ci-opensbi.yml | 63 +
.gitlab-ci.d/opensbi/Dockerfile | 33 +
.gitlab-ci.yml | 1 +
3 files changed, 97 insertions(+)
create mode 100644 .gitlab-ci-opensbi.yml
create mode 100644
for sifive_u machine. A pre-built
OpenSBI v0.6 image has been added as the default bios for 32-bit
sifive_u machine.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
Makefile | 2 +-
pc-bios/opensbi-riscv32-sifive_u
e for-loop in sbi_ipi_send_many()
ac5e821 include: Bump-up version to 0.6
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 40984 -> 41280 bytes
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 49160 -> 5376
From: Bin Meng
Update BIOS_FILENAME to consider 32-bit bios image file name.
Tested booting Linux v5.5 32-bit image (built from rv32_defconfig
plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
the interrupt, the VS mode forwarding check does not work
as intended and interrupt is actually forwarded to hypervisor. This
patch fixes this issue.
Signed-off-by: Rajnesh Kanwal
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 9 -
1 file changed, 8
From: Alistair Francis
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.
This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set
The following changes since commit a98135f727595382e200d04c2996e868b7925a01:
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request'
into staging (2020-03-16 14:55:59 +)
are available in the Git repository at:
g...@github.com:palmer-dabbelt/qemu.git
On Wed, 26 Feb 2020 09:55:34 PST (-0800), alistai...@gmail.com wrote:
On Wed, Feb 26, 2020 at 12:54 AM Rajnesh Kanwal
wrote:
Here is the link to the patch
https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html
Ah, it doesn't look like it made it to the QEMU-devel list. Can
On Mon, 24 Feb 2020 05:39:40 PST (-0800), bmeng...@gmail.com wrote:
This series advances the roms/opensbi submodule to the v0.6 release,
and builds and captures platform firmware binaries from that release.
A 32-bit sifive_u bios image has also been added, so that we can have
32-bit test
On Mon, 24 Feb 2020 05:39:44 PST (-0800), bmeng...@gmail.com wrote:
Add two GitLab jobs to build the OpenSBI firmware binaries.
The first job builds a Docker image with the packages requisite
to build OpenSBI, and stores this image in the GitLab registry.
The second job pulls the image from the
privledge level.
This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.
Signed-off-by: Alistair Francis
@Palmer Dabbelt Ping!
Sorry, I must have missed this. It's in the queue (with the reviews as
collected by patchwork).
Thanks
On Thu, 05 Mar 2020 09:20:31 PST (-0800), phi...@redhat.com wrote:
Cc'ing qemu-trivial@ in case there is a pending PR in progress, it
might get merged quicker.
On Thu, Mar 5, 2020 at 6:19 PM Philippe Mathieu-Daudé wrote:
On 3/5/20 5:48 PM, Palmer Dabbelt wrote:
> THis would almost certai
pport for the new execption numbers")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c47d10b739..c0b7023100 100644
--- a/target/riscv/c
y Coverity.
--------
Palmer Dabbelt (1):
RISC-V: Add a missing "," in riscv_excp_names
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
On Thu, 05 Mar 2020 08:44:20 PST (-0800), Peter Maydell wrote:
On Tue, 3 Mar 2020 at 00:49, Palmer Dabbelt wrote:
From: Alistair Francis
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off
THis would almost certainly cause the exception names to be reported
incorrectly. Covarity found the issue (CID 1420223). As per Peter's
suggestion, I've also added a comma at the end of the list to avoid the issue
reappearing in the future.
Signed-off-by: Palmer Dabbelt
---
target/riscv
t;, );
sysbus_mmio_map(SYS_BUS_DEVICE(>otp), 0, memmap[SIFIVE_U_OTP].base);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 82667b5..7cf742e 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -59,6 +59,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+uint32_t serial;
} SiFiveUState;
enum {
Reviewed-by: Palmer Dabbelt
Thanks. This is in the queue for the soft freeze.
). If rdtime callback is not
available then the monitor (i.e. OpenSBI) will trap-n-emulate
TIME CSRs in software.
We see 25+% performance improvement in hackbench numbers when
TIME CSRs are not trap-n-emulated.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
From: Alistair Francis
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 11
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu.h| 10 ++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 17 +
target
From: Anup Patel
This patch extends CLINT emulation to provide rdtime callback for
TCG. This rdtime callback will be called wheneven TIME CSRs are
read in privileged modes.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_clint.c
-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3ce86adb89..b51ab92068 100644
--- a/target/riscv/translate.c
+++ b/target
PCI device 8086:100e
...
BAR1: I/O at 0x [0x003e].
...
It turns out we should set pci_allow_0_address to true to allow 0
PCI address, otherwise pci_bar_address() treats such address as
PCI_BAR_UNMAPPED.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
Signed-off-
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 5 +
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b27066f6a7..c47d10b739
From: Alistair Francis
The hret instruction does not exist in the new spec versions, so remove
it from QEMU.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9e28b19c29..d3b764e694
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 193 ++
2 files changed, 175 insertions(+), 19 deletions(-)
diff --git
From: Alistair Francis
Mark both sstatus and vsstatus as dirty (3).
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/translate.c b/target
From: Alistair Francis
When the Hypervisor extension is in use we only enable floating point
support when both status and vsstatus have enabled floating point
support.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 3
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c0e942684d
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode| 23 ++-
.../riscv/insn_trans/trans_privileged.inc.c | 40 +++
2 files changed, 54 insertions(+), 9
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 37 -
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 69 +--
1 file changed, 59 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e87c9115bc
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5b889a0065..aa04e5cca7 100644
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 33 -
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 62 +---
1 file changed, 52 insertions(+), 10 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f7333286bd..c0e942684d 100644
--- a/target/riscv/csr.c
From: Alistair Francis
To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 11 +++
target/riscv/cpu_bits.h | 7 +
target/riscv/cpu_helper.c | 61 +++
3 files changed, 79
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 918678789a..2e6700bbeb
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 +++---
target/riscv/cpu_bits.h | 12 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 116 +
1 file changed, 116 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3fa8d2cfda..f7333286bd 100644
From: Alistair Francis
Dump the Hypervisor registers and the current Hypervisor state.
While we are editing this code let's also dump stvec and scause.
Signed-off-by: Alistair Francis
Signed-off-by: Atish Patra
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv
-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_bits.h | 6 ++
target/riscv/cpu_helper.c | 18 ++
3 files changed, 26 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Alistair Francis
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 21
From: Alistair Francis
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 4
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 18 ++
3 files changed, 25 insertions(+)
diff --git
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 136 -
1 file changed, 134 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 95de9e58a2..010125efd6 100644
From: Alistair Francis
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 8
target/riscv/cpu_bits.h | 35
From: Alistair Francis
The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 2
The following changes since commit 8b6b68e05b43f976714ca1d2afe01a64e1d82cba:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2020-02-27 19:15:15 +)
are available in the Git repository at:
g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf3
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d5de7f468a..eff064dc44 100644
On Sun, 02 Feb 2020 05:42:15 PST (-0800), Anup Patel wrote:
This series adds emulation of TIME CSRs for privileged mode. With
this series, we see approximately 25+% improvement in hackbench
numbers for non-virtualized (or Host) Linux and 40+% improvement
in hackbench numbers for Guest/VM Linux.
On Sun, 02 Feb 2020 07:41:25 PST (-0800), bmeng...@gmail.com wrote:
Hi Palmer,
On Sat, Nov 23, 2019 at 6:41 AM Palmer Dabbelt wrote:
On Fri, 22 Nov 2019 07:27:52 PST (-0800), bmeng...@gmail.com wrote:
> When testing e1000 with the virt machine, e1000's I/O space cannot
> be ac
On Fri, 31 Jan 2020 17:01:35 PST (-0800), Alistair Francis wrote:
This patch series adds the RISC-V Hypervisor extension v0.5. This is the
latest draft spec of the Hypervisor extension.
The Hypervisor extension is disabled by default, so this series should
result in no changes to anyone using
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
+#ifdef TARGET_RISCV32
+env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0);
+#else
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
+#endif
env->mstatus = mstatus;
riscv_cpu_set_mode(env, prev_priv);
Reviewed-by: Palmer Dabbelt
de */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
Reviewed-by: Palmer Dabbelt
riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (env->mstatus & MSTATUS_FS) {
+if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
+return false;
+}
return true;
}
Reviewed-by: Palmer Dabbelt
(env, 0);
+if (riscv_cpu_fp_enabled(env)) {
+*flags |= env->mstatus & MSTATUS_FS;
+}
#endif
}
Reviewed-by: Palmer Dabbelt
riscv_cpu_force_hs_excep_enabled(env));
+
+/* Trapping to M mode, virt is disabled */
+riscv_cpu_set_virt_enabled(env, 0);
+riscv_cpu_set_force_hs_excep(env, 0);
+}
+
+s = env->mstatus;
s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE <<
env->priv));
s = set_field(s, MSTATUS_MPP, env->priv);
Reviewed-by: Palmer Dabbelt
From: Anup Patel
Add myself as Goldfish RTC maintainer until someone else is
willing to maintain it.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
From: Anup Patel
We extend QEMU RISC-V virt machine by adding Goldfish RTC device
to it. This will allow Guest Linux to sync it's local date/time
with Host date/time via RTC device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
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