On Tue, Jun 18, 2024 at 1:37 PM Philippe Mathieu-Daudé
wrote:
> Hi Paul,
>
> On 18/6/24 20:58, Paul Zimmerman wrote:
> > On Tue, Jun 18, 2024 at 6:56 AM Zheyu Ma > <mailto:zheyum...@gmail.com>> wrote:
> > >
> > > This commit modifies the dwc2_hsot
gt; 2,
val, size);
> break;
> default:
> -g_assert_not_reached();
> +qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset
0x%"HWADDR_PRIx"\n",
> + __func__, addr);
> +break;
> }
> }
>
> --
> 2.34.1
Looks good to me.
Reviewed-by: Paul Zimmerman
On Sat, Jun 26, 2021 at 10:21 PM Qiang Liu wrote:
>
> Hi folks,
>
> I found this bug by my dwc2 fuzzer.
> It seems that
> * https://bugs.launchpad.net/qemu/+bug/1907042
> * https://bugs.launchpad.net/qemu/+bug/1525123
> or
> * https://gitlab.com/qemu-project/qemu/-/issues/119
> *
On Sat, Jun 12, 2021 at 12:10 PM Paul Zimmerman wrote:
>
> On Sat, Jun 12, 2021 at 12:40 AM Philippe Mathieu-Daudé
> wrote:
> >
> > On 6/11/21 9:48 PM, Paul Zimmerman wrote:
> > > I will take a look. Might take me a couple of days to get to it though.
> >
&
On Sat, Jun 12, 2021 at 12:40 AM Philippe Mathieu-Daudé wrote:
>
> On 6/11/21 9:48 PM, Paul Zimmerman wrote:
> > I will take a look. Might take me a couple of days to get to it though.
>
> Thanks!
>
> Odd, your comment appears as posted by myself on GitLab:
> https://g
I will take a look. Might take me a couple of days to get to it though.
On Fri, Jun 11, 2021 at 4:10 AM Philippe Mathieu-Daudé wrote:
>
> Cc'ing Paul Zimmerman for the hcd-dwc2 model.
>
> On Thu, Jun 10, 2021 at 2:10 PM programmingkidx (@programmingkidx) wrote:
> > 虎游 commented
On Wed, Oct 14, 2020 at 12:55 PM Mauro Matteo Cascella
wrote:
>
> On Tue, Oct 13, 2020 at 10:41 AM Gerd Hoffmann wrote:
> >
> > > > Also: What would be the effect of simply returning here? Would dwc2
> > > > emulation simply stop processing queues? Should we maybe raise an
> > > > error IRQ?
> >
Hi Gerd,
On Tue, Oct 13, 2020 at 12:04 AM Gerd Hoffmann wrote:
>
> > > +if (mps == 0) {
> > > +qemu_log_mask(LOG_GUEST_ERROR,
> > > +"%s: Bad HCCHAR_MPS set to zero\n", __func__);
> > > +return;
> > > +}
>
> > I think it would be better
gt;mps', and who knows what mischief an
invalid value there might cause.
After that, you can add my
Reviewed-by: Paul Zimmerman
Thanks,
Paul
area of investigation for someone motivated
enough :)
- Paul
On Thu, Oct 8, 2020 at 2:07 PM Paul Zimmerman wrote:
>
> Hi Thomas,
>
> What does 'top' say while the emulation is running? I have an 8 cpu-thread
> system, yet 'top' never shows more than about 300% cpu. I would have
>
Hi Thomas,
What does 'top' say while the emulation is running? I have an 8 cpu-thread
system, yet 'top' never shows more than about 300% cpu. I would have
thought it would get closer to 800% cpu. And running qemu as root with
nice -20 doesn't seem to make much difference.
- Paul
On Thu, Oct 8,
On Tue, Oct 6, 2020 at 11:28 PM Thomas <74cmo...@gmail.com> wrote:
>
> Hello!
>
> Many thanks for your support.
>
> I managed to get emulated RPi starting.
>
> However there's one question I want to ask:
> How can I accelerate the startup sequence?
> I mean booting the emulated RPi takes more than
Here is that command line again, hopefully readable this time:
qemu-system-arm -M raspi2 \
-drive file=2019-09-26-raspbian-buster.img,format=raw,if=sd \
-dtb bcm2709-rpi-2-b.dtb \
-kernel kernel7.img \
-append 'rw earlycon=pl011,0x3f201000 console=ttyAMA0 \
loglevel=8
You need to use -M raspi2 (or -M raspi3 for 64-bit kernels) to enable
the Raspberry Pi emulation. And you need version 5.1 or newer of Qemu to
get the dwc2 USB emulation. I don't think any Linux distributions
provide that new of a Qemu, so you might have to build it yourself.
Here is the command
set dev br0 up
sudo ip address delete 192.168.0.54/24 dev eth0
sudo ip address add 192.168.0.54/24 dev br0
sudo ip route add default via 192.168.0.1 dev br0
- Paul
>
> Am 06.10.2020 um 00:08 schrieb Paul Zimmerman:
> > If you can upgrade to Qemu 5.1 or newer, you shoul
I misspoke in my last comment, that first bullet should have said
- If you are running a Raspbian image, you must add "dwc_otg.fiq_fsm_enable=0"
to the '-append' command-line parameters.
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If you can upgrade to Qemu 5.1 or newer, you should be able to use the
builtin raspi2 or raspi3 emulation directly. Version 5.1 adds support for the
USB controller on the Pi.
There is no limitation on the amount of memory you can use with this
method, and the networking should work.
Here is the
As of version 5.1, Qemu now supports USB on Raspberry PI 2 and 3. There
are a few caveats:
- If you are running a Raspbian image, you must add "dwc_otg.fiq_fsm_enable=0"
to the '-kernel' command-line parameters.
- Raspbian images 2016-05-27-raspbian-jessie and earlier don't work, see
Bug
gt; Cc: David Carlier
> Cc: Finn Thain
> Cc: Guenter Roeck
> Cc: Helge Deller
> Cc: Hervé Poussineau
> Cc: James Hogan
> Cc: Jean-Christophe Dubois
> Cc: Kővágó Zoltán
> Cc: Laurent Vivier
> Cc: Michael Rolnik
> Cc: Niek Linnenbank
> Cc: Paul Burton
>
So I dug into this a little more, and it looks like this issue has
nothing to do with hcd-dwc2, other than it served as a canary because of
the assert that fired. With hcd-dwc2 removed from the build, the
2016-05-27 Raspbian image still doesn't work, it hangs shortly after the
login prompt appears
Change several assert()s to qemu_log_mask(LOG_GUEST_ERROR...),
to prevent the guest from causing Qemu to assert. Also fix up
several existing qemu_log_mask()s to include the function name in
the message.
Suggested-by: Peter Maydell
Signed-off-by: Paul Zimmerman
---
Hi Gerd,
This was prompted
I also tried
http://downloads.raspberrypi.org/raspbian/images/raspbian-2016-09-28/2016-09-23
-raspbian-jessie.zip, which is the next Raspbian release after the
cursed one, and it works OK too. So I assume any release after that will
also work OK. Just in case anyone wants to use the older releases
The URL to the image I used is
http://downloads.raspberrypi.org/raspbian/images/raspbian-2019-09-30/2019-09-26
-raspbian-buster.zip
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https://bugs.launchpad.net/bugs/1892604
Title:
Something very strange is going on with the dwc_otg driver in
2016-05-27-raspbian-jessie.img. Something is reading and writing incrementally
throughout the register space of the hcd-dwc2 host.
And adding the "dwc_otg.fiq_fsm_enable=0" kernel option does not fix it.
Brendan, Petunia, is there a
Hmm, that's odd. I will try to reproduce this.
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https://bugs.launchpad.net/bugs/1892604
Title:
qemu-system-arm: ../hw/usb/hcd-dwc2.c:666: dwc2_glbreg_read: Assertion
`addr <=
Are you able to modify the -append string to add
"dwc_otg.fiq_fsm_enable=0", and if so does it fix the problem?
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https://bugs.launchpad.net/bugs/1892604
Title:
qemu-system-arm:
Could this be related to bug 1892604? Although I don't know how Laurent would
not be seeing the
problem.
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https://bugs.launchpad.net/bugs/1895053
Title:
Cannot nspawn raspbian 10
Hmm, yes agreed. I started a 2-week holiday on Monday, I can work on
this after I get back on Sept. 7
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https://bugs.launchpad.net/bugs/1892604
Title:
qemu-system-arm:
What happens if you add "dwc_otg.fiq_fsm_enable=0" to the kernel command
line? This is noted as a requirement in the changelog at
https://wiki.qemu.org/ChangeLog/5.1
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Gerd, it's OK by me if you take Thomas's patch instead, I agree the
changelog is better. It also has a fixes tag.
Reviewed-by: Paul Zimmerman
On Wed, Jul 22, 2020 at 9:29 PM Thomas Huth wrote:
> On 22/07/2020 19.23, Philippe Mathieu-Daudé wrote:
> > On 7/22/20 5:47 PM, Thomas H
The hcd-dwc2 host controller is currently built for all targets.
Since for now hcd-dwc2 is only implemented on RASPI, restrict its
build to that target only.
Signed-off-by: Paul Zimmerman
---
Hi Gerd,
Do we want to apply this before the 5.1.0 release? It seems a waste
to build this code
On Thu, Jul 9, 2020 at 12:57 AM Gerd Hoffmann wrote:
> > Starting at line 1746 is the first CBW, it's for an Inquiry command.
> >
> > Starting at line 1759 is the response, notice at line 1761 the MSD debug
> > says "Data in 64/36", which is strange.
>
> Not really. First is the packet size,
On Wed, Jul 8, 2020 at 3:30 AM Gerd Hoffmann wrote:
> Hi,
>
> > IIRC, without the dev-storage patch, the very first SCSI command
> > would get stuck waiting for the CSW, because the CSW is not a
> > multiple of MPS. I will have to work on getting a debug trace for
> > you, I'll get back to you
On Wed, Jul 8, 2020 at 12:29 AM Gerd Hoffmann wrote:
> Hi,
>
> > > Why does 7ad3d51ebb8a522ffcad391c4bef281245739dde look at short-not-ok?
> >
> > Because the patch changes dev-storage to terminate the transfer if a
> > short packet is received, so I figured 'short-not-ok' should affect
> >
On Tue, Jul 7, 2020 at 12:57 AM Gerd Hoffmann wrote:
> Hi,
> >
> > Gerd, do you know the purpose of the 'short_not_ok' parameter to
> > usb_packet_setup()?
>
> Well, some usb host controllers have a flag in the transfer control
> blocks to indicate the host controller should stop processing
gt; #include "qapi/error.h"
> -#include "hw/usb/dwc2-regs.h"
> #include "hw/usb/hcd-dwc2.h"
> #include "hw/irq.h"
> #include "sysemu/dma.h"
> @@ -43,6 +42,7 @@
> #include "qemu/timer.h"
> #include "qemu/log.h"
> #include "hw/qdev-properties.h"
> +#include "dwc2-regs.h"
>
> #define USB_HZ_FS 1200
> #define USB_HZ_HS 9600
> --
> 2.21.3
>
>
Reviewed-by: Paul Zimmerman
> -#include "qemu/error-report.h"
> -#include "qemu/main-loop.h"
> #include "hw/qdev-properties.h"
>
> #define USB_HZ_FS 1200
> --
> 2.21.3
>
>
Reviewed-by: Paul Zimmerman
gt; #include "qapi/error.h"
> #include "hw/usb/dwc2-regs.h"
> #include "hw/usb/hcd-dwc2.h"
> +#include "hw/irq.h"
> +#include "sysemu/dma.h"
> #include "migration/vmstate.h"
> #include "trace.h"
> +#include "qemu/timer.h"
> #include "qemu/log.h"
> #include "hw/qdev-properties.h"
>
> --
> 2.21.3
>
>
Reviewed-by: Paul Zimmerman
On 7/6/20 3:21 PM, Paul Zimmerman wrote:
On Sat, Jul 4, 2020 at 11:24 AM Paul Zimmerman mailto:pauld...@gmail.com>> wrote:
On Sat, Jul 4, 2020 at 11:21 AM Sai Pavan Boddu mailto:saip...@xilinx.com>> wrote:
Hi,
__ __
We are seeing some error
On Sat, Jul 4, 2020 at 11:24 AM Paul Zimmerman wrote:
>
>
> On Sat, Jul 4, 2020 at 11:21 AM Sai Pavan Boddu
> wrote:
>
>> Hi,
>>
>>
>>
>> We are seeing some errors when a usb-storage device is formatted or
>> mo
blk_update_request: I/O error, dev sda, sector 4096 op
> 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
>
> / # [Thread 0x7fffd4680700 (LWP 23270) exited]
>
>
>
>
>
> Bisect commit :
>
>
>
> commit 7ad3d51ebb8a522ffcad391c4bef281245739dde
>
> A
On Sat, Jul 4, 2020 at 7:50 AM Philippe Mathieu-Daudé
wrote:
> Add an section for the dwc2 host controller emulation
> introduced in commit 153ef1662c.
>
> Cc: Paul Zimmerman
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTAINERS | 6 ++
> 1 file changed,
On Wed, Jul 1, 2020 at 11:30 AM Gerd Hoffmann wrote:
> Hi,
>
> > This patch series adds emulation for the dwc-hsotg USB controller,
> > which is used on the Raspberry Pi 3 and earlier, as well as a number
> > of other development boards. The main benefit for Raspberry Pi is that
> > this
On Fri, Jun 5, 2020 at 7:28 AM Peter Maydell
wrote:
> On Thu, 21 May 2020 at 00:54, Paul Zimmerman wrote:
> >
> > This verion fixes a few things pointed out by Peter, and one by
> > Felippe.
> >
> > This patch series adds emulation for the dwc-hsotg
regressions.
Signed-off-by: Paul Zimmerman
---
hw/usb/dev-storage.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index 5c4b57b06b..ae3c550042 100644
--- a/hw/usb/dev-storage.c
+++ b/hw/usb/dev-storage.c
@@ -229,6 +229,9
Wire the dwc-hsotg (dwc2) emulation into Qemu
Signed-off-by: Paul Zimmerman
Reviewed-by: Philippe Mathieu-Daude
---
hw/arm/bcm2835_peripherals.c | 21 -
include/hw/arm/bcm2835_peripherals.h | 3 ++-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/hw
Add a check for functional dwc-hsotg (dwc2) USB host emulation to
the Raspi 2 acceptance test
Signed-off-by: Paul Zimmerman
Reviewed-by: Philippe Mathieu-Daude
---
tests/acceptance/boot_linux_console.py | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests
due to the tab
indentation, but I would rather import it as-is than reformat it.
Signed-off-by: Paul Zimmerman
---
include/hw/usb/dwc2-regs.h | 895 +
1 file changed, 895 insertions(+)
create mode 100644 include/hw/usb/dwc2-regs.h
diff --git a/include/hw/usb
ry regions for the controller registers.
Signed-off-by: Paul Zimmerman
---
hw/usb/Kconfig |5 +
hw/usb/Makefile.objs |1 +
hw/usb/hcd-dwc2.c| 1417 ++
hw/usb/trace-events | 50 ++
4 files changed, 1473 insertions(+)
create mode 100644 hw/us
Add the dwc-hsotg (dwc2) USB host controller state definitions.
Mostly based on hw/usb/hcd-ehci.h.
Signed-off-by: Paul Zimmerman
---
hw/usb/hcd-dwc2.h | 190 ++
1 file changed, 190 insertions(+)
create mode 100644 hw/usb/hcd-dwc2.h
diff --git a/hw
for your time,
Paul
---
Paul Zimmerman (7):
raspi: add BCM2835 SOC MPHI emulation
dwc-hsotg (dwc2) USB host controller register definitions
dwc-hsotg (dwc2) USB host controller state definitions
dwc-hsotg (dwc2) USB host controller emulation
usb: add short-packet handling to usb-storage driv
Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
emulation. It is very basic, only providing the FIQ interrupt
needed to allow the dwc-otg USB host controller driver in the
Raspbian kernel to function.
Signed-off-by: Paul Zimmerman
Acked-by: Philippe Mathieu-Daude
Reviewed-by: Peter
On Wed, May 20, 2020 at 6:18 AM Peter Maydell
wrote:
> On Wed, 20 May 2020 at 06:49, Paul Zimmerman wrote:
> > Is there a tree somewhere that has a working example of a
> > three-phase reset? I did a 'git grep' on the master branch and didn't
> > find any code that is actua
On Mon, May 18, 2020 at 8:34 AM Peter Maydell
wrote:
> On Tue, 12 May 2020 at 07:50, Paul Zimmerman wrote:
> >
>
> > +static void dwc2_reset(DeviceState *dev)
> > +{
> > +DWC2State *s = DWC2_USB(dev);
> > +int i;
> > +
> > +trace_usb
Have you seen the patch series I have posted on the qemu-devel mailing
list? "[PATCH v5 0/7] dwc-hsotg (aka dwc2) USB host controller emulation."
If you could test that and give your 'tested-by', it could help get the
patch series accepted. That would require you to download the latest Qemu
source
On Fri, May 15, 2020 at 1:10 AM Philippe Mathieu-Daudé
wrote:
> On 5/12/20 8:48 AM, Paul Zimmerman wrote:
> > Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
> > emulation. It is very basic, only providing the FIQ interrupt
> > needed to allow the dwc-otg USB h
ry regions for the controller registers.
Signed-off-by: Paul Zimmerman
---
hw/usb/Kconfig |5 +
hw/usb/Makefile.objs |1 +
hw/usb/hcd-dwc2.c| 1372 ++
hw/usb/trace-events | 47 ++
4 files changed, 1425 insertions(+)
create mode 100644 hw/us
Add a check for functional dwc-hsotg (dwc2) USB host emulation to
the Raspi 2 acceptance test
Reviewed-by: Philippe Mathieu-Daude
Signed-off-by: Paul Zimmerman
---
tests/acceptance/boot_linux_console.py | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests
Add the dwc-hsotg (dwc2) USB host controller state definitions.
Mostly based on hw/usb/hcd-ehci.h.
Signed-off-by: Paul Zimmerman
---
hw/usb/hcd-dwc2.h | 173 ++
1 file changed, 173 insertions(+)
create mode 100644 hw/usb/hcd-dwc2.h
diff --git a/hw
regressions.
Signed-off-by: Paul Zimmerman
---
hw/usb/dev-storage.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index 5c4b57b06b..ae3c550042 100644
--- a/hw/usb/dev-storage.c
+++ b/hw/usb/dev-storage.c
@@ -229,6 +229,9
indentation, but I
would rather import it as-is than reformat it.
Signed-off-by: Paul Zimmerman
---
include/hw/usb/dwc2-regs.h | 895 +
1 file changed, 895 insertions(+)
create mode 100644 include/hw/usb/dwc2-regs.h
diff --git a/include/hw/usb/dwc2-regs.h b
Wire the dwc-hsotg (dwc2) emulation into Qemu
Reviewed-by: Philippe Mathieu-Daude
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 21 -
include/hw/arm/bcm2835_peripherals.h | 3 ++-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/hw
Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
emulation. It is very basic, only providing the FIQ interrupt
needed to allow the dwc-otg USB host controller driver in the
Raspbian kernel to function.
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 17
- Updated a couple of the commit messages with more info.
Thanks for your time,
Paul
---
Paul Zimmerman (7):
raspi: add BCM2835 SOC MPHI emulation
dwc-hsotg (dwc2) USB host controller register definitions
dwc-hsotg (dwc2) USB host controller state definitions
dwc-hsotg (dwc2) USB host
Hi Phil,
On Tue, Apr 28, 2020 at 12:06 AM Philippe Mathieu-Daudé
wrote:
> Hi Paul,
>
> On 4/28/20 4:22 AM, Paul Zimmerman wrote:
> > Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
> > emulation. It is very basic, only providing the FIQ interrupt
> > need
regressions.
Signed-off-by: Paul Zimmerman
---
hw/usb/dev-storage.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index 5c4b57b06b..ae3c550042 100644
--- a/hw/usb/dev-storage.c
+++ b/hw/usb/dev-storage.c
@@ -229,6 +229,9
Add a check for functional dwc-hsotg (dwc2) USB host emulation to
the Raspi 2 acceptance test
Signed-off-by: Paul Zimmerman
---
tests/acceptance/boot_linux_console.py | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests
ry regions for the controller registers.
Signed-off-by: Paul Zimmerman
---
hw/usb/Kconfig |5 +
hw/usb/Makefile.objs |1 +
hw/usb/hcd-dwc2.c| 1378 ++
hw/usb/trace-events | 47 ++
4 files changed, 1431 insertions(+)
create mode 100644 hw/us
Wire the dwc-hsotg (dwc2) emulation into Qemu
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 21 -
include/hw/arm/bcm2835_peripherals.h | 3 ++-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm
Import the dwc-hsotg (dwc2) register definitions file from the
Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the
mainline Linux kernel, the only changes being two instances of
'u32' changed to 'uint32_t' to allow it to compile.
Signed-off-by: Paul Zimmerman
---
include/hw/usb/dwc2
Add the dwc-hsotg (dwc2) USB host controller state definitions.
Mostly based on hw/usb/hcd-ehci.h.
Signed-off-by: Paul Zimmerman
---
hw/usb/hcd-dwc2.h | 173 ++
1 file changed, 173 insertions(+)
create mode 100644 hw/usb/hcd-dwc2.h
diff --git a/hw
c, on the
advice of Gerd. I just dropped the debug prints in bcm2835_mphi.c,
since I didn't consider them very useful.
- Updated a couple of the commit messages with more info.
Thanks for your time,
Paul
---
Paul Zimmerman (7):
raspi: add BCM2835 SOC MPHI emulation
dwc-hsotg (dwc2)
Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
emulation. It is very basic, only providing the FIQ interrupt
needed to allow the dwc-otg USB host controller driver in the
Raspbian kernel to function.
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 17
On 4/21/20 12:13 AM, Philippe Mathieu-Daudé wrote:
Use 1 container holding 2 regions:
- I/O registers
- FIFOs
Remove all the static base addresses.
Name address space.
Signed-off-by: Philippe Mathieu-Daudé
---
Sometime a patch is cleaner/quicker than explanations.
Suggestion to be squashed
Just FYI I think I have the fix for this (missing a
DEFINE_PROP_END_OF_LIST()).
Thanks,
Paul
On Mon, Apr 20, 2020 at 8:15 PM wrote:
> Patchew URL:
> https://patchew.org/QEMU/20200421014551.10426-1-pauld...@gmail.com/
>
>
>
> Hi,
>
> This series failed the asan build test. Please find the
Add a check for functional dwc-hsotg (dwc2) USB host emulation to
the Raspi 2 acceptance test
Signed-off-by: Paul Zimmerman
---
tests/acceptance/boot_linux_console.py | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests
regressions.
Signed-off-by: Paul Zimmerman
---
hw/usb/dev-storage.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index 5c4b57b06b..ae3c550042 100644
--- a/hw/usb/dev-storage.c
+++ b/hw/usb/dev-storage.c
@@ -229,6 +229,9
r starting
on page 370.
https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
which has a description of the controller registers starting on
page 130.
Signed-off-by: Paul Zimmerman
---
hw/usb/hcd-dwc2.
Wire the dwc-hsotg (dwc2) emulation into Qemu
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 21 -
hw/usb/Kconfig | 5 +
hw/usb/Makefile.objs | 1 +
include/hw/arm/bcm2835_peripherals.h | 3 ++-
4 files
Add the dwc-hsotg (dwc2) USB host controller state definitions.
Mostly based on hw/usb/hcd-ehci.h.
Signed-off-by: Paul Zimmerman
---
hw/usb/hcd-dwc2.h | 184 ++
1 file changed, 184 insertions(+)
create mode 100644 hw/usb/hcd-dwc2.h
diff --git a/hw
Import the dwc-hsotg (dwc2) register definitions file from the
Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the
mainline Linux kernel, the only changes being two instances of
'u32' changed to 'uint32_t' to allow it to compile.
Signed-off-by: Paul Zimmerman
---
include/hw/usb/dwc2
Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
emulation. It is very basic, only providing the FIQ interrupt
needed to allow the dwc-otg USB host controller driver in the
Raspbian kernel to function.
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 17
kernel.
- Switched from debug printfs to tracepoints in hcd-dwc2.c, on the
advice of Gerd. I just dropped the debug prints in bcm2835_mphi.c,
since I didn't consider them very useful.
- Updated a couple of the commit messages with more info.
Thanks for your time,
Paul
---
Paul Zimmerm
Hi Philippe,
On Mon, Apr 20, 2020 at 12:16 AM Philippe Mathieu-Daudé
wrote:
> Hi Paul,
>
> On 3/29/20 1:17 AM, Paul Zimmerman wrote:
> > Add the dwc-hsotg (dwc2) USB host controller emulation code.
> > Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c.
> >
> > N
this in the future.
Thanks,
Paul
On Mon, Apr 20, 2020 at 12:25 AM Philippe Mathieu-Daudé
wrote:
> On 3/29/20 1:17 AM, Paul Zimmerman wrote:
> > Add the dwc-hsotg (dwc2) USB host controller emulation code.
> > Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c.
> >
Hi Peter,
On 4/16/20 8:45 AM, Peter Maydell wrote:
On Sun, 29 Mar 2020 at 00:18, Paul Zimmerman wrote:
< snip >
+/* nifty macros from Arnon's EHCI version */
+#define get_field(data, field) \
+(((data) & field##_MASK) >> field##_SHIFT)
+
+#define set_field(data, n
On 4/16/20 9:30 AM, Philippe Mathieu-Daudé wrote:
On 4/16/20 5:47 PM, Peter Maydell wrote:
On Thu, 16 Apr 2020 at 16:45, Peter Maydell wrote:
On Sun, 29 Mar 2020 at 00:18, Paul Zimmerman wrote:
+ s->as = _space_memory;
Ideally this should be a device property. (hw/dma/pl080.c
On Tue, Mar 31, 2020 at 4:16 AM Philippe Mathieu-Daudé
wrote:
> On 3/31/20 11:28 AM, Gerd Hoffmann wrote:
> > On Sat, Mar 28, 2020 at 05:16:59PM -0700, Paul Zimmerman wrote:
> >> This patch series adds emulation for the dwc-hsotg USB controller,
> >> which is
r starting on
page 370.
https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
has a description of the controller registers starting on page
130.
Signed-off-by: Paul Zimmerman
---
hw/usb/hcd-dwc2.c | 1301 +
Wire the dwc-hsotg (dwc2) emulation into Qemu
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 21 -
hw/usb/Kconfig | 5 +
hw/usb/Makefile.objs | 1 +
include/hw/arm/bcm2835_peripherals.h | 3 ++-
4 files
Import the dwc2 register definitions file from the Linux kernel.
This is a copy of drivers/usb/dwc2/hw.h from the mainline Linux
kernel, the only changes being two instances of 'u32' changed to
'uint32_t' to allow it to compile
Signed-off-by: Paul Zimmerman
---
include/hw/usb/dwc2-regs.h | 895
Add BCM2835 SOC MPHI emulation. It is very basic, only providing
the FIQ interrupt needed to allow the dwc-otg USB host controller
driver in the Raspbian kernel to function.
Signed-off-by: Paul Zimmerman
---
hw/arm/bcm2835_peripherals.c | 17 +++
hw/misc/Makefile.objs
t consider them very useful.
- Updated a couple of the commit messages with more info.
Thanks for your time,
Paul
---
Paul Zimmerman (6):
Add BCM2835 SOC MPHI emulation
dwc-hsotg USB host controller register definitions
dwc-hsotg USB host controller state definitions
dwc-hsotg USB host
regressions.
Signed-off-by: Paul Zimmerman
---
hw/usb/dev-storage.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index 5c4b57b06b..ae3c550042 100644
--- a/hw/usb/dev-storage.c
+++ b/hw/usb/dev-storage.c
@@ -229,6 +229,9
Add the dwc-hsotg (dwc2) USB host controller state definitions.
Mostly based on hw/usb/hcd-ehci.h.
Signed-off-by: Paul Zimmerman
---
hw/usb/hcd-dwc2.h | 180 ++
1 file changed, 180 insertions(+)
create mode 100644 hw/usb/hcd-dwc2.h
diff --git a/hw
Thanks Gerd. I will switch over to using tracepoints, wait a few days to
see if there are any more comments, then resubmit.
Thanks,
Paul
On Mon, Mar 23, 2020 at 4:10 AM Gerd Hoffmann wrote:
> Hi,
>
> > 1) I have used printf-based debug statements while developing the
> >code, and have
On Sun, Mar 22, 2020 at 3:28 PM Paul Zimmerman wrote:
< snip >
> 2) I have imported the register description file from the Linux
>kernel. This file is licensed GPL-2 only, is this OK?
Never mind about the license, I see it is actually GPL 2.0 or later. I
guess the question rem
The dwc-hsotg (dwc2) USB host depends on a short packet to
indicate the end of an IN transfer. The usb-storage driver
currently doesn't provide this, so fix it.
Signed-off-by: Paul Zimmerman
---
hw/usb/dev-storage.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff
81408_0902.pdf
has a description of the controller registers starting on page
130.
Signed-off-by: Paul Zimmerman
---
hw/usb/hcd-dwc2.c | 1353 +
1 file changed, 1353 insertions(+)
create mode 100644 hw/usb/hcd-dwc2.c
diff --git a/hw/usb/hcd-dwc2.c b/
Import the dwc2 register definitions file from the Linux kernel.
This is a copy of drivers/usb/dwc2/hw.h from the mainline Linux
kernel, the only changes being two instances of 'u32' changed to
'uint32_t' to allow it to compile
Signed-off-by: Paul Zimmerman
---
include/hw/usb/dwc2-regs.h | 895
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