On Thu, 18 Jul 2024 at 03:15, Alistair Francis wrote:
>
> From: Atish Patra
>
> The timer is setup function is invoked in both hpmcounter
> write and mcountinhibit write path. If the OF bit set, the
> LCOFI interrupt is disabled. There is no benefitting in
> setting up the qemu timer until LCOFI
On Thu, 18 Jul 2024 at 14:20, Peter Maydell wrote:
>
> From: Mostafa Saleh
>
> SMMUv3 OAS is currently hardcoded in the code to 44 bits, for nested
> configurations that can be a problem, as stage-2 might be shared with
> the CPU which might have different PARANGE, and accord
On Thu, 18 Jul 2024 at 03:12, Alistair Francis wrote:
>
> From: Atish Patra
>
> Privilege mode filtering can also be emulated for cycle/instret by
> tracking host_ticks/icount during each privilege mode switch. This
> patch implements that for both cycle/instret and mhpmcounters. The
> first one
On Sat, 20 Jul 2024 at 08:56, TaiseiIto wrote:
>
> Before this commit, an HPET driver can not write correct values to
> comparator registers of HPET timers. When I tested my HPET driver on QEMU, I
> ovserved too early HPET interruptions. I investigated cause and found that
> QEMU didn't write
On Fri, Jul 19, 2024 at 01:54:37PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Thu, Jul 18, 2024 at 07:32:05PM -0300, Fabiano Rosas wrote:
> >> Peter Xu writes:
> >>
> >> > On Thu, Jul 18, 2024 at 06:27:32PM -0300, Fab
g of migration, so it doesn't even have PCI config space migrated;
I thought the real mr->addr should be in there.
I also failed to understand yet on why the mr->addr check needs to be done
by ignore-shared only. Some explanation would be greatly helpful around
this area..
Thanks,
--
Peter Xu
On Fri, 19 Jul 2024 at 16:36, Julien Grall wrote:
>
> Hi,
>
> On 18/07/2024 10:43, Julien Grall wrote:
> > Hi Eric,
> >
> > On 17/07/2024 18:43, Eric Auger wrote:
> >> Hi Peter, Richard,
> >>
> >> On 7/17/24 17:09, Jean-Philippe Bruc
nts
> +++ b/migration/trace-events
> @@ -340,6 +340,11 @@ colo_receive_message(const char *msg) "Receive '%s'
> message"
> # colo-failover.c
> colo_failover_set_state(const char *new_state) "new state %s"
>
> +# cpr.c
> +cpr_save_fd(const char *name, int id, int fd) "%s, id %d, fd %d"
> +cpr_delete_fd(const char *name, int id) "%s, id %d"
> +cpr_find_fd(const char *name, int id, int fd) "%s, id %d returns %d"
> +
> # block-dirty-bitmap.c
> send_bitmap_header_enter(void) ""
> send_bitmap_bits(uint32_t flags, uint64_t start_sector, uint32_t nr_sectors,
> uint64_t data_size) "flags: 0x%x, start_sector: %" PRIu64 ", nr_sectors: %"
> PRIu32 ", data_size: %" PRIu64
> diff --git a/system/vl.c b/system/vl.c
> index 03951be..6521ee3 100644
> --- a/system/vl.c
> +++ b/system/vl.c
> @@ -77,6 +77,7 @@
> #include "hw/block/block.h"
> #include "hw/i386/x86.h"
> #include "hw/i386/pc.h"
> +#include "migration/cpr.h"
> #include "migration/misc.h"
> #include "migration/snapshot.h"
> #include "sysemu/tpm.h"
> @@ -3713,6 +3714,8 @@ void qemu_init(int argc, char **argv)
>
> qemu_create_machine(machine_opts_dict);
>
> +cpr_state_load(_fatal);
Might be good to add a rich comment here explaining the decision on why
loading here; I think most of the tricks lie here. E.g., it needs to be
before XXX and it needs to be after YYY.
Thanks,
> +
> suspend_mux_open();
>
> qemu_disable_default_devices();
> --
> 1.8.3.1
>
--
Peter Xu
On Thu, Jul 18, 2024 at 07:32:05PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Thu, Jul 18, 2024 at 06:27:32PM -0300, Fabiano Rosas wrote:
> >> Peter Xu writes:
> >>
> >> > On Thu, Jul 18, 2024 at 04:39:00PM -0300, Fabiano Rosas wro
On Thu, Jul 18, 2024 at 06:27:32PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Thu, Jul 18, 2024 at 04:39:00PM -0300, Fabiano Rosas wrote:
> >> v2 is ready, but unfortunately this approach doesn't work. When client A
> >> takes the payload, it fill
er of allocated pages */
uint32_t allocated;
RAMBlock *block;
/* offset of each page */
ram_addr_t offset[0];
} MultiFDPages_t;
--
Peter Xu
On Thu, 18 Jul 2024 at 17:37, Jonathan Cameron via
wrote:
>
> On Thu, 18 Jul 2024 05:07:53 -0400
> Yao Xingtao wrote:
>
> > When injecting a new poisoned region through qmp_cxl_inject_poison(),
> > the newly injected region should not overlap with existing poisoned
> > regions.
> >
> > The
On Thu, Jul 18, 2024 at 11:43:54AM -0400, Steven Sistare wrote:
> On 7/17/2024 3:24 PM, Peter Xu wrote:
> [...]
> >
> > PS to Steve: and I think I left tons of other comments in previous version
> > outside this patch too, but I don't think they're fully discussed when
On Thu, 30 May 2024 at 12:11, Gerd Hoffmann wrote:
>
> It's 2024. 4k display resolutions are a thing these days.
> Raise width and height limits of the qemu vnc server.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1596
> Signed-off-by: Gerd Hoffmann
> ---
> ui/vnc.h | 4 ++--
>
the channel, so this mode sends
> CPR state over a second migration channel that is not visible to the user.
> New QEMU reads the second channel prior to creating devices or backends.
Oh, maybe this is the reason that cpr-transfer will need a separate uri..
Thanks,
--
Peter Xu
son| 38 ++-
> qemu-options.hx| 8
> stubs/vmstate.c| 7
> system/vl.c| 3 ++
> 18 files changed, 359 insertions(+), 6 deletions(-)
> create mode 100644 migration/cpr-transfer.c
>
> --
> 1.8.3.1
>
--
Peter Xu
From: Akihiko Odaki
Asahi Linux supports KVM but lacks PMU support.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240716-pmu-v3-1-8c7c1858a...@daynix.com
Signed-off-by: Peter Maydell
---
tests/qtest/arm-cpu-features.c | 13 -
1 file changed, 8
Message-id: 20240715084519.1189624-18-smost...@google.com
Signed-off-by: Peter Maydell
---
hw/arm/smmuv3.c | 35 ++-
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 2d61637aed5..3db6c7c1357 100644
--- a/hw/arm/smmuv3.c
++
means
invalidate for all ASIDs.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-13-smost...@google.com
Signed-off-by: Peter Maydell
---
include/hw/arm/smmu-common.h | 3 ++-
hw/arm/smmu-common.c
Reviewed-by: Eric Auger
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-10-smost...@google.com
Signed-off-by: Peter Maydell
---
hw/arm/smmu-common.c | 64 +---
1 file changed, 43 insertions(+), 21 deletions(-)
diff --git a/hw/arm/smmu-common.c b/hw
-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Peter Maydell
---
tests/tcg/aarch64/sme-fmopa-1.c | 63 +++
tests/tcg/aarch64/sme-fmopa-2.c | 56 +++
tests/tcg/aarch64/sme-fmopa-3.c | 63
BIT(0) is stage-1 and BIT(1) is
stage-2 and both is nested.
- Tracing, as stage is printed as int.
Reviewed-by: Eric Auger
Reviewed-by: Alex Bennée
Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Message-id: 20240715084519.1189624-5-smost...@google.com
Signed-off-by: Peter
-by: Eric Auger
Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-7-smost...@google.com
Signed-off-by: Peter Maydell
---
include/hw/arm/smmu-common.h | 14 +++---
hw/arm/smmu-common.c | 10 +-
hw
-by: Alex Bennée
Message-id: 20240715084519.1189624-6-smost...@google.com
Signed-off-by: Peter Maydell
---
include/hw/arm/smmu-common.h | 8 ++
hw/arm/smmu-common.c | 59 +++
hw/arm/smmuv3.c | 194 +--
hw/arm/trace-events | 2
-Philippe Brucker
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-8-smost...@google.com
Signed-off-by: Peter Maydell
---
include/hw/arm/smmu-common.h | 3 +++
hw/arm/smmuv3.c | 3 +--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/smmu
lex Bennée
Message-id: 20240717060149.204788-3-richard.hender...@linaro.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2374
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-sme.c | 12
1 file changed, 8
SMMUPTWEventInfo as it would
have the correct stage set from the page table walk.
Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-17-smost...@google.com
Signed-off-by: Peter Maydell
---
hw/arm/smmuv3.c
off-by: Peter Maydell
---
include/hw/arm/smmu-common.h | 1 +
hw/arm/smmu-common.c | 16
hw/arm/smmuv3.c | 28 ++--
hw/arm/trace-events | 4 +++-
4 files changed, 46 insertions(+), 3 deletions(-)
diff --git a/include/hw/arm/s
p_event"
Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-9-smost...@google.com
Signed-off-by: Peter Maydell
---
hw/arm/smmuv3.c | 120 +---
1 f
-by: Mostafa Saleh
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-11-smost...@google.com
Signed-off-by: Peter Maydell
---
include/hw/arm/smmu-common.h | 1 +
hw/arm/smmu-common.c | 37
2 files changed, 34 insertions(+), 4 deletions(-)
diff
target/arm: Relax ordered/atomic alignment checks for
LSE2")
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20240709134504.357-3-peter.mayd...@linaro.org
---
target/arm/tcg/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ar
callback”
Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Message-id: 20240715084519.1189624-4-smost...@google.com
Signed-off-by: Peter Maydell
---
hw/arm/smmuv3-internal.h | 6 ++
hw/arm/smmuv3.c | 8 +++-
2 files changed, 13 insertions(+), 1
emu-project/qemu/-/issues/2419
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20240709134504.357-2-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/t
transaction.
Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-12-smost...@google.com
Signed-off-by: Peter Maydell
---
include/hw/arm/smmu-common.h | 7 ++--
hw/arm/smmu-c
.
There is already a similar check for stage-2 against effective PA.
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
Message-id: 20240715084519.1189624-2-smost...@google.com
Signed-off-by: Peter Maydell
---
hw/arm/smmu-common.c | 10 ++
1 file
hiko Odaki
Message-id: 20240716-pmu-v3-4-8c7c1858a...@daynix.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/hvf/hvf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index ef9bc42738d..eb090e67a2f 100644
--- a/target/arm
rtual size would be larger than the physical size if
either virtual dimension were larger than their physical counterparts
and not necessarily both.
Signed-off-by: SamJakob
Message-id: 20240713160353.62410-1...@samjakob.com
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Peter Maydell
---
OAS is greater than 48bits.
- Remove unused functions/macros: pa_range/MAX_PA.
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-19-smost...@google.com
Signed-off-by: Peter Maydell
---
hw/arm
-off-by: Peter Maydell
---
hw/arm/smmu-common.c | 10 ++
hw/arm/smmuv3.c | 4
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index e81b684d06c..e8cdbcd8aef 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
= -1 keeps the original
behaviour.
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Signed-off-by: Mostafa Saleh
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-14-smost...@google.com
Signed-off-by: Peter Maydell
---
include/hw/arm/smmu-common.h | 2 +-
hw/arm/smmu
-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Reviewed-by: Alex Bennée
Message-id: 20240715084519.1189624-16-smost...@google.com
Signed-off-by: Peter Maydell
---
hw/arm/smmuv3.c | 39 +--
hw/arm/trace-events | 2 +-
2 files
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Message-id: 20240717060149.204788-2-richard.hender...@linaro.org
[rth: Split from a larger patch]
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off
according to SMMUPTWEventInfo
hw/arm/smmuv3: Support and advertise nesting
hw/arm/smmu: Refactor SMMU OAS
Peter Maydell (2):
target/arm: Fix handling of LDAPR/STLR with negative offset
target/arm: LDAPR should honour SCTLR_ELx.nAA
Richard Henderson (1):
target/arm: Use
On Thu, 18 Jul 2024 at 13:14, Peter Maydell wrote:
>
> On Tue, 16 Jul 2024 at 13:50, Akihiko Odaki wrote:
> >
> > target/arm/kvm.c checked PMU availability but claimed PMU is
> > available even if it is not. In fact, Asahi Linux supports KVM but lacks
> > P
On Tue, 16 Jul 2024 at 13:50, Akihiko Odaki wrote:
>
> target/arm/kvm.c checked PMU availability but claimed PMU is
> available even if it is not. In fact, Asahi Linux supports KVM but lacks
> PMU support. Only advertise PMU availability only when it is really
> available.
>
> Fixes: dc40d45ebd8e
On Tue, 16 Jul 2024 at 13:51, Akihiko Odaki wrote:
>
> Setting pmu property used to have no effect for hvf so fix it.
>
> Signed-off-by: Akihiko Odaki
> ---
> target/arm/hvf/hvf.c | 317
> ++-
> 1 file changed, 163 insertions(+), 154 deletions(-)
On Tue, 16 Jul 2024 at 13:50, Akihiko Odaki wrote:
>
> kvm-steal-time and sve properties are added for KVM even if the
> corresponding features are not available. Always add pmu property for
> Armv8. Note that the property is added only for Armv8 as QEMU emulates
> PMUv3, which is part of Armv8.
On Tue, 16 Jul 2024 at 13:50, Akihiko Odaki wrote:
>
> kvm_arm_get_host_cpu_features() used to add the PMU feature
> unconditionally, and kvm_arch_init_vcpu() removed it when it is actually
> not available. Conditionally add the PMU feature in
> kvm_arm_get_host_cpu_features() to save code.
>
>
On Fri, 12 Jul 2024 at 14:15, Mauro Carvalho Chehab
wrote:
>
> Having magic numbers inside the code is not a good idea, as it
> is error-prone. So, instead, create a macro with the number
> definition.
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
> hw/arm/virt-acpi-build.c | 6 +++---
>
On Wed, 17 Jul 2024 at 07:02, Richard Henderson
wrote:
>
> Changes for v2:
> - Apply r-b.
> - Add license headers to two test cases.
>
> r~
>
> Daniyal Khan (2):
> target/arm: Use float_status copy in sme_fmopa_s
> tests/tcg/aarch64: Add test cases for SME FMOPA (widening)
>
> Richard
On Thu, 18 Jul 2024 at 07:15, Markus Armbruster wrote:
>
> Looks like this one fell through the cracks.
>
> Octavian Purdila writes:
>
> > Add path option to the pty char backend which will create a symbolic
> > link to the given path that points to the allocated PTY.
> >
> > This avoids having
On Wed, 17 Jul 2024 at 21:11, Volker Rümelin wrote:
>
> Fix the search function in Sphinx generated html docs when built
> with Sphinx >= 6.0.0.
>
> Quote from the Sphinx blog at
> https://blog.readthedocs.com/sphinx6-upgrade
>
> Sphinx 6 is out and has important breaking changes
>
> Bundled
On Wed, Jul 17, 2024 at 11:07:17PM +0200, Maciej S. Szmigiero wrote:
> On 17.07.2024 21:00, Peter Xu wrote:
> > On Tue, Jul 16, 2024 at 10:10:25PM +0200, Maciej S. Szmigiero wrote:
> > > > > > > The comment I removed is slightly misleading to me too, be
On Wed, Jul 17, 2024 at 11:07:43PM +0200, Maciej S. Szmigiero wrote:
> > Don't wait on me. I think I can make the changes Peter suggested without
> > affecting too much the interfaces used by this series. If it comes to
> > it, I can rebase this series "under" Maci
nts in previous version
outside this patch too, but I don't think they're fully discussed when this
series was sent. I can re-read the series again, but I don't think it'll
work out if we keep skipping discussions..
Thanks,
--
Peter Xu
On Wed, 17 Jul 2024 at 18:44, Eric Auger wrote:
>
> Hi Peter, Richard,
>
> On 7/17/24 17:09, Jean-Philippe Brucker wrote:
> > On Mon, Jul 15, 2024 at 08:45:00AM +, Mostafa Saleh wrote:
> >> Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
&g
gt; negotiation.
>
> The RFC version of my multifd device state transfer patch set introduced
> a new migration channel header (by Avihai) for clean and extensible
> migration channel handshaking but people didn't like so it was removed in v1.
Hmm, I'm not sure this is relevant to the context of discussion here, but I
confess I didn't notice the per-channel header thing in the previous RFC
series. Link is here:
https://lore.kernel.org/r/636cec92eb801f13ba893de79d4872f5d8342097.1713269378.git.maciej.szmigi...@oracle.com
Maciej, if you want, you can split that out of the seriess. So far it looks
like a good thing with/without how VFIO tackles it.
Thanks,
--
Peter Xu
On Tue, Jul 16, 2024 at 10:10:12PM +0200, Maciej S. Szmigiero wrote:
> On 27.06.2024 16:56, Peter Xu wrote:
> > On Thu, Jun 27, 2024 at 11:14:28AM +0200, Maciej S. Szmigiero wrote:
> > > On 26.06.2024 18:23, Peter Xu wrote:
> > > > On Wed, Jun 26, 2024 at 05:47:3
On Wed, Jul 17, 2024 at 09:40:06AM -0400, Michael S. Tsirkin wrote:
> On Wed, Jul 17, 2024 at 09:33:01AM -0400, Peter Xu wrote:
> > Hi, Michael,
> >
> > On Wed, Jul 17, 2024 at 04:55:52AM -0400, Michael S. Tsirkin wrote:
> > > I just want to understand how
ns when postcopy migration is close to the end.
Thanks,
--
Peter Xu
On Tue, 16 Jul 2024 at 22:53, Richard Henderson
wrote:
>
> On 7/17/24 02:55, Alex Bennée wrote:
> >> Are you expecting the same GdbCmdParseEntry object to be registered
> >> multiple times? Can we fix that at a higher level?
> >
> > Its basically a hack to deal with the fact everything is tied
On Tue, Jul 16, 2024 at 03:44:54PM +0530, Prasad Pandit wrote:
> Hello Peter,
>
> On Mon, 15 Jul 2024 at 19:10, Peter Xu wrote:
> > IMHO it's better we debug and fix all the issues before merging this one,
> > otherwise we may overlook something.
>
> * Well we
On Tue, 16 Jul 2024 at 18:45, Thomas Huth wrote:
>
> On 16/07/2024 15.06, Michael S. Tsirkin wrote:
> > On Tue, Jul 16, 2024 at 02:59:30PM +0200, Igor Mammedov wrote:
> >> CI often fails 'cross-i686-tci' job due to runner slowness
> >> Log shows that test almost complete, with a few remaining
>
On Tue, 9 Jul 2024 at 07:05, Ganapatrao Kulkarni
wrote:
>
> Extend the 'mte' property for the virt machine to cover KVM as
> well. For KVM, we don't allocate tag memory, but instead enable
> the capability.
>
> If MTE has been enabled, we need to disable migration, as we do not
> yet have a way
On Tue, Jul 16, 2024 at 02:34:07AM +, Liu, Yuan1 wrote:
> > -Original Message-
> > From: Yichen Wang
> > Sent: Tuesday, July 16, 2024 6:13 AM
> > To: Peter Xu ; Fabiano Rosas ; Paolo
> > Bonzini ; Daniel P. Berrangé ;
> > Eduardo Habkost ;
On Tue, 16 Jul 2024 at 15:37, Philippe Mathieu-Daudé wrote:
>
> On 16/7/24 12:35, Peter Maydell wrote:
> > On Sat, 13 Jul 2024 at 17:04, SamJakob wrote:
> >>
> >> It is common practice when implementing double-buffering
> >> on Video
On Tue, 16 Jul 2024 at 14:48, Alex Bennée wrote:
>
> Gustavo Romero writes:
>
> > Hi Alex,
> >
> > On 7/16/24 8:42 AM, Alex Bennée wrote:
> >> Coverity reported a memory leak (CID 1549757) in this code and its
> >> admittedly rather clumsy handling of extending the command table.
> >> Instead of
On Tue, 16 Jul 2024 at 14:07, Michael S. Tsirkin wrote:
>
> On Tue, Jul 16, 2024 at 02:59:30PM +0200, Igor Mammedov wrote:
> > CI often fails 'cross-i686-tci' job due to runner slowness
> > Log shows that test almost complete, with a few remaining
> > when bios-tables-test timeout hits:
> >
> >
On 16.07.24 14:32, David Woodhouse wrote:
> On 16 July 2024 12:54:52 BST, Peter Hilber
> wrote:
>> On 11.07.24 09:50, David Woodhouse wrote:
>>> On Thu, 2024-07-11 at 09:25 +0200, Peter Hilber wrote:
>>>>
>>>> IMHO this phrasing is
On Tue, 16 Jul 2024 at 12:36, Akihiko Odaki wrote:
>
> On 2024/07/16 20:32, Peter Maydell wrote:
> > On Tue, 16 Jul 2024 at 09:28, Akihiko Odaki
> > wrote:
> > Before we do this we need to do something to forbid setting
> > the pmu property to
On 08.07.24 11:27, David Woodhouse wrote:
> +
> + /*
> + * Time according to time_type field above.
> + */
> + uint64_t time_sec; /* Seconds since time_type epoch */
> + uint64_t time_frac_sec; /* (seconds >> 64) */
> + uint64_t time_esterror_picosec;
On 11.07.24 09:50, David Woodhouse wrote:
> On Thu, 2024-07-11 at 09:25 +0200, Peter Hilber wrote:
>>
>> IMHO this phrasing is better, since it directly refers to the state of the
>> structure.
>
> Thanks. I'll update it.
>
>> AFAIU if there would be abnor
On Mon, 15 Jul 2024 at 06:58, Richard Henderson
wrote:
>
> From: Daniyal Khan
>
> Signed-off-by: Daniyal Khan
> Message-Id: 172090222034.13953.1688870870882292209...@git.sr.ht
> [rth: Split test cases to separate patch, tidy assembly.]
> Signed-off-by: Richard Henderson
> --- /dev/null
> +++
On Tue, 16 Jul 2024 at 09:28, Akihiko Odaki wrote:
>
> kvm-steal-time and sve properties are added for KVM even if the
> corresponding features are not available. Always add pmu property too.
>
> Signed-off-by: Akihiko Odaki
> ---
> target/arm/cpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1
uot;'pmu' feature not suported by hvf");
> +return;
> +}
> if (kvm_enabled() && !kvm_arm_pmu_supported()) {
> error_setg(errp, "'pmu' feature not supported by KVM on this
> host");
> return;
Typo (should be "supported") but otherwise
Reviewed-by: Peter Maydell
thanks
-- PMM
On Sun, 14 Jul 2024 at 11:43, Akihiko Odaki wrote:
>
> Signed-off-by: Akihiko Odaki
> ---
> target/arm/gdbstub.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
> index c3a9b5eb1ed2..03f77362efc1 100644
> ---
On Sat, 13 Jul 2024 at 17:04, SamJakob wrote:
>
> It is common practice when implementing double-buffering
> on VideoCore to do so by multiplying the height of the
> virtual buffer by the number of virtual screens desired
> (i.e., two - in the case of
On Tue, 16 Jul 2024 at 09:48, Paolo Bonzini wrote:
>
> Queued, thanks.
Could you add
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2438
to the commit message?
thanks
-- PMM
On Tue, 16 Jul 2024 at 09:28, Akihiko Odaki wrote:
>
> Setting 'pmu' does not make sense for CPU types emulating physical
> CPUs.
>
> Signed-off-by: Akihiko Odaki
> ---
> target/arm/cpu.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index
t match reply to any of the previous response), then
the front-end can manage the threads well to serialize all the requests,
like using this rwlock.
Thanks,
--
Peter Xu
On Mon, Jul 15, 2024 at 01:44:00PM +0530, Prasad Pandit wrote:
> On Thu, 11 Jul 2024 at 21:12, Peter Xu wrote:
> > I apologize if I suggested WITH_QEMU_LOCK_GUARD when we talked.. I don't
> > remember which one I suggested, but in this case IIUC it'll be much easier
> >
dma_calibration().
>
> The value passed to aspeed_smc_hclk_divisor() is always between 0 and
> 15 and, in this case, there is always a matching hclk divisor. Remove
> the return 0 and use g_assert_not_reached() instead.
>
> Fixes: Coverity CID 1547822
> Suggested-by: Peter
te zeroes features support").
>
> Explicitly cast the 32-bit value before the shift to fix this issue.
>
> Fixes: Coverity CID 1549454
> Fixes: 5ab04420c3 ("contrib/vhost-user-*: use QEMU bswap helper functions")
> Fixes: caa1ee4313 ("vhost-user-blk: add disc
copy and
other special stuff.
--
Peter Xu
On Fri, Jul 12, 2024 at 10:02:43PM +1000, Nicholas Piggin wrote:
> This factors the CPU pause function from pause_all_vcpus() into a
> new cpu_pause() function, similarly to cpu_resume(). cpu_resume()
> is moved to keep it next to cpu_pause().
>
> Cc: Philippe Mathieu-Daudé
>
On Fri, 12 Jul 2024 at 16:18, Stefano Garzarella wrote:
>
> On Fri, Jul 12, 2024 at 03:24:47PM GMT, Peter Maydell wrote:
> >On Wed, 3 Jul 2024 at 23:48, Michael S. Tsirkin wrote:
> >> #if defined(__linux__) && defined(BLKDISCARD) && defined(BLKZERO
On Fri, 13 Sept 2019 at 16:50, Peter Maydell wrote:
>
> From: Cédric Le Goater
>
> When doing calibration, the SPI clock rate in the CE0 Control Register
> and the read delay cycles in the Read Timing Compensation Register are
> set using bit[11:4] of the DMA Control Regist
On Wed, 3 Jul 2024 at 23:48, Michael S. Tsirkin wrote:
>
> From: Stefano Garzarella
>
> Let's replace the calls to le*toh() and htole*() with qemu/bswap.h
> helpers to make the code more portable.
>
> Suggested-by: Philippe Mathieu-Daudé
> Reviewed-by: Philippe Mathieu-Daudé
> Tested-by:
On Fri, 5 Jul 2024 at 16:37, Alex Bennée wrote:
>
> From: Gustavo Romero
>
> This commit implements the stubs to handle the qIsAddressTagged,
> qMemTag, and QMemTag GDB packets, allowing all GDB 'memory-tag'
> subcommands to work with QEMU gdbstub on aarch64 user mode. It also
> implements the
On Fri, 5 Jul 2024 at 23:06, Philippe Mathieu-Daudé wrote:
>
> "General command" (GEN_CMD, CMD56) is described as:
>
> GEN_CMD is the same as the single block read or write
> commands (CMD24 or CMD17). The difference is that [...]
> the data block is not a memory payload data but has a
>
_likely(haddr)) {
> memset(haddr, byte, size);
> } else {
> MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
> @@ -236,7 +233,6 @@ static void do_access_memset(CPUS390XState *env, vaddr
> vaddr, char *haddr,
> cpu_stb_mmu(env, vaddr + i, byte, oi, ra);
> }
> }
> -#endif
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 10 Jul 2024 at 04:31, Richard Henderson
wrote:
>
> Avoid a race condition with munmap in another thread.
> Use around blocks that exclusively use "host_fn".
> Keep the blocks as small as possible, but without setting
> and clearing for every operation on one page.
>
> Signed-off-by:
guest page, if the memset() does fault it should only
be for the case of "the whole block went away", so you never
get the situation of "successfully wrote a chunk and then
faulted partway through, and we should have written the
tags for the partial write and did not".
So
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 10 Jul 2024 at 04:30, Richard Henderson
wrote:
>
> In a completely artifical memset benchmark object_dynamic_cast_assert
> dominates the profile, even above guest address resolution and
> the underlying host memset.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 4 ++--
de/exec/cpu_ldst.h | 34 ++
> accel/tcg/cpu-exec.c | 3 ---
> accel/tcg/user-exec.c| 1 -
> 4 files changed, 34 insertions(+), 32 deletions(-)
> delete mode 100644 accel/tcg/user-retaddr.h
Reviewed-by: Peter Maydell
thanks
-- PMM
currently implement the architectural
interrupt handling.
Add a "do nothing" implementation of cpu_exec_hook for Tricore,
assert on startup that the CPU does provide the hook, and remove
the runtime NULL check before calling it.
Signed-off-by: Peter Maydell
---
accel/tcg/cpu-
On Thu, Jul 11, 2024 at 06:12:44PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Thu, Jul 11, 2024 at 04:37:34PM -0300, Fabiano Rosas wrote:
> >
> > [...]
> >
> >> We also don't flush the iov at once, so f->buf seems redundant to
> >>
more.
So to summary, we'll have:
- 1 main thread (send / recv)
- N multifd threads (IOs only)
- M worker threads (jobs only)
Of course, postcopy not involved.. How's that sound?
--
Peter Xu
On Thu, Jul 11, 2024 at 09:48:02AM -0700, Yichen Wang wrote:
> On Thu, Jul 11, 2024 at 8:45 AM Peter Xu wrote:
> >
> > On Wed, Jul 10, 2024 at 07:52:24PM -0700, Yichen Wang wrote:
> > > v5:
> > > - Rebase changes on top of 59084feb256c617063e0dbe7e64821ae8852d7cf
hey look similar to me yet so far, as long as multifd is
managing the N buffers, while the clients will manage one for each. There
should have a helper to allocate/free the generic multifd buffers (SendData
in this case) so everyone should be using that.
>
> Let me know, I'll write some code and see what it looks like.
I think Maciej is working on this too since your absence, as I saw he
decided to base his work on top of yours and he's preparing the new
version. I hope you two won't conflict or duplicates the work. Might be
good to ask / wait and see how far Maciej has been going.
--
Peter Xu
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