On Fri, 7 Jun 2024 at 15:28, Sebastian Huber
wrote:
>
> On 30.05.24 12:30, Peter Maydell wrote:
> > On Fri, 24 May 2024 at 13:08, Sebastian Huber
> > wrote:
> >>
> >> v2:
> >>
> >> * Add Kconfig support
> >>
> >
On Fri, 9 Feb 2024 at 14:07, Daniel P. Berrangé wrote:
>
> From: Hyman Huang
>
> Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
>
> SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> Organization of State Commercial Administration of China (OSCCA)
> as an authorized
On Mon, 3 Jun 2024 at 09:38, Jeuk Kim wrote:
>
> From: Minwoo Im
>
> This patch adds support for MCQ defined in UFSHCI 4.0. This patch
> utilized the legacy I/O codes as much as possible to support MCQ.
>
> MCQ operation & runtime register is placed at 0x1000 offset of UFSHCI
> register
On Wed, 5 Jun 2024 at 15:43, Edgar E. Iglesias wrote:
>
> From: "Edgar E. Iglesias"
>
> Julien reported that he has seen strange behaviour when running
> Xen on QEMU using GICv2. When Xen migrates a guest's vCPU to
> another pCPU while the vCPU is handling an interrupt the guest
> is unable to
On Thu, 23 May 2024 at 02:48, Song Gao wrote:
>
> From: Bibo Mao
>
> Memory map table for fwcfg is used for UEFI BIOS, UEFI BIOS uses the first
> entry from fwcfg memory map as the first memory HOB, the second memory HOB
> will be used if the first memory HOB is used up.
>
> Memory map table for
On Tue, 4 Jun 2024 at 07:47, Paolo Bonzini wrote:
>
> From: Michael Roth
>
> Currently all SEV/SEV-ES functionality is managed through a single
> 'sev-guest' QOM type. With upcoming support for SEV-SNP, taking this
> same approach won't work well since some of the properties/state
> managed by
On Tue, 4 Jun 2024 at 07:49, Paolo Bonzini wrote:
>
> Add launch_update_data() in SevCommonStateClass and
> invoke as sev_launch_update_data() for SEV object.
>
> Signed-off-by: Pankaj Gupta
> Message-ID: <20240530111643.1091816-26-pankaj.gu...@amd.com>
> Signed-off-by: Paolo Bonzini
Hi;
On Tue, 4 Jun 2024 at 07:45, Paolo Bonzini wrote:
>
> From: Brijesh Singh
>
> SEV-SNP support relies on a different set of properties/state than the
> existing 'sev-guest' object. This patch introduces the 'sev-snp-guest'
> object, which can be used to configure an SEV-SNP guest. For example,
>
On Fri, 31 May 2024 at 19:16, Cord Amfmgm wrote:
> On Fri, May 31, 2024 at 9:03 AM Peter Maydell
> wrote:
>> What I would like to see is what we could classify under
>> "rationale", which is to say "what prompted us to make this
>> change?"
On Fri, 31 May 2024 at 10:37, Marcin Juszkiewicz
wrote:
>
> Trusted Firmware 2.11 got released, EDK2 202405 got released as well.
> Both were built for QEMU CI and proper patch is now in arm.next queue.
>
> So all requirements to move from legacy 62.5MHz to armv8.6-ready 1GHz
> frequency are
On Thu, 6 Jun 2024 at 22:18, Robin Murphy wrote:
>
> On 2024-06-06 6:13 pm, Jonathan Cameron wrote:
> > On Thu, 6 Jun 2024 12:56:59 +0100
> > Peter Maydell wrote:
> >
> >> On Thu, 6 Jun 2024 at 11:48, Zhenyu Zhang wrote:
> >>> In Linux, a chec
On Thu, 6 Jun 2024 at 15:31, Gerd Hoffmann wrote:
>
> Add policies for devices which are deprecated or not secure.
> There are three options: allow, warn and deny.
>
> It's implemented for devices only. Devices will probably be the main
> user of this. Also object_new() can't fail as of today
On Thu, 6 Jun 2024 at 11:30, Philippe Mathieu-Daudé wrote:
>
> Commit c9274b6bf0 ("target/s390x: start moving TCG-only code
> to tcg/") moved mem_helper.c, but the trace-events file is
> still in the parent directory, so is the generated trace.h.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
On Thu, 6 Jun 2024 at 12:04, Edgar E. Iglesias wrote:
>
> On Thu, Jun 6, 2024 at 12:00 PM Andrew.Yuan
> wrote:
>>
>> In the Cadence IP for Gigabit Ethernet MAC Part Number: IP7014 IP
>> Rev: R1p12 - Doc Rev: 1.3 User Guide, the specification for the
>> type2_compare_x_word_0 register
On Thu, 6 Jun 2024 at 11:48, Zhenyu Zhang wrote:
>
> Multiple warning messages and corresponding backtraces are observed when Linux
> guest is booted on the host with Fujitsu CPUs. One of them is shown as below.
>
> [0.032443] [ cut here ]
> [0.032446] uart-pl011
Update the 'monitor' component:
* qapi/ and monitor/ are now subdirectories
* add job-qmp.c
Signed-off-by: Peter Maydell
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/coverity-scan/COMPONENTS.md
b/scripts/coverity-scan
avoid the need to change them again in future if the build path
changes again.
This change was made with a search-and-replace of (/qemu)?
to .*/qemu .
Signed-off-by: Peter Maydell
---
scripts/coverity-scan/COMPONENTS.md | 104 ++--
1 file changed, 52 insertions(+), 52
. (There is, alas, no automated API for this.)
thanks
-- PMM
Peter Maydell (5):
scripts/coverity-scan/COMPONENTS.md: Update paths to match gitlab CI
scripts/coverity-scan/COMPONENTS.md: Fix 'char' component
scripts/coverity-scan/COMPONENTS.md: Add crypto headers in
host/include
host/include/*/host/crypto/ are relatively new headers; add them
to the crypto component.
Signed-off-by: Peter Maydell
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/coverity-scan/COMPONENTS.md
b/scripts/coverity-scan
current sources.
Signed-off-by: Peter Maydell
---
scripts/coverity-scan/COMPONENTS.md | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/scripts/coverity-scan/COMPONENTS.md
b/scripts/coverity-scan/COMPONENTS.md
index 98d4bcd6a50..fb081a59265 100644
--- a/scripts/coverity-scan
Add libqmp to the testlibs component.
Signed-off-by: Peter Maydell
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/coverity-scan/COMPONENTS.md
b/scripts/coverity-scan/COMPONENTS.md
index 3864f8eda07..858190be097 100644
On Fri, 31 May 2024 at 16:17, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 31/5/24 16:21, Peter Maydell wrote:
> > If there are any other changes we want to make to our component
> > regexes, now would be a great time to suggest them, because this
> > chan
confusing if A and M both use the same arm_cpu_exec_halt().
(This isn't a bug in the FEAT_WFxT commit, though -- the
behaviour is the same.)
thanks
-- PMM
Peter Maydell (3):
target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt()
target: Set TCGCPUOps::cpu_exec_halt to target's
, but it's perhaps a little
confusing. We would also like to make setting the cpu_exec_halt
method mandatory.
Initialize arm_v7m_tcg_ops cpu_exec_halt to the same function we use
for A-profile. (On M-profile we never set up the wfxt timer so there
is no change in behaviour here.)
Signed-off
to the source file it's defined in.
Signed-off-by: Peter Maydell
---
target/riscv/internals.h | 3 +++
target/alpha/cpu.c | 1 +
target/avr/cpu.c | 1 +
target/cris/cpu.c | 2 ++
target/hppa/cpu.c | 1 +
target/loongarch/cpu.c | 1 +
target/m68k/cpu.c
Now that all targets set TCGCPUOps::cpu_exec_halt, we can make it
mandatory and remove the fallback handling that calls cpu_has_work.
Signed-off-by: Peter Maydell
---
include/hw/core/tcg-cpu-ops.h | 9 ++---
accel/tcg/cpu-exec.c | 7 +--
2 files changed, 7 insertions(+), 9
On Thu, 30 May 2024 at 13:59, Song Gao wrote:
>
> The VM uses old bios to boot up only 1 cpu, causing the test case to fail.
> Update the bios to solve this problem.
>
> Reported-by: Thomas Huth
> Signed-off-by: Song Gao
> ---
> tests/avocado/machine_loongarch.py | 2 +-
> 1 file changed, 1
On Mon, 3 Jun 2024 at 15:58, Peter Maydell wrote:
>
> On Mon, 3 Jun 2024 at 15:49, Daniel P. Berrangé wrote:
> > We can't rely on the sanitizers to catch all cases where we're casting
> > functions, as we don't have good enough code coverage in tests to
> > iden
On Mon, 3 Jun 2024 at 15:49, Daniel P. Berrangé wrote:
> We can't rely on the sanitizers to catch all cases where we're casting
> functions, as we don't have good enough code coverage in tests to
> identify all places that way.
>
> Unless there's a warning flag we can use to get diagnosis of this
On Mon, 3 Jun 2024 at 13:56, Daniel P. Berrangé wrote:
>
> On Mon, Jun 03, 2024 at 01:23:00PM +0100, Peter Maydell wrote:
> > On Fri, 31 May 2024 at 22:21, Octavian Purdila wrote:
> > >
> > > Add path option to the pty char backend which will create a symboli
On Mon, 3 Jun 2024 at 06:17, Shiva sagar Myana wrote:
>
> Returning an uint32_t casted to a gint from g_cmp_ids causes the tx queue to
> become wrongly sorted when executing g_slist_sort. Fix this by always
> returning -1 or 1 from g_cmp_ids based on the ID comparison instead.
> Also, if two
On Fri, 31 May 2024 at 22:21, Octavian Purdila wrote:
>
> Add path option to the pty char backend which will create a symbolic
> link to the given path that points to the allocated PTY.
>
> Based on patch from Paulo Neves:
>
>
On Mon, 3 Jun 2024 at 12:42, Daniel P. Berrangé wrote:
> I think there's different answers here for upstream vs downstream.
>
> Upstream QEMU's scope is to emulate pretty much arbitrary hardware that
> may have existed at any point in time. Emulating Cirrus is very much
> in scope upstream, and
On Mon, 3 Jun 2024 at 09:46, Philippe Mathieu-Daudé wrote:
>
> On 31/5/24 16:11, Dr. David Alan Gilbert wrote:
> > * Don Porter (por...@cs.unc.edu) wrote:
> >> The new "info pg" monitor command prints the current page table,
> >> including virtual address ranges, flag bits, and snippets of
On Sun, 3 Mar 2024 at 14:08, Arnaud Minier
wrote:
>
> Update the RCC state and propagate frequency changes when writing to the
> RCC registers. Currently, ICSCR, CIER, the reset registers and the stop
> mode registers are not implemented.
>
> Some fields have not been implemented due to
In kvm-all.c, two lines have been accidentally indented with
hard-coded tabs rather than spaces. Normalise to match the rest
of the file.
Signed-off-by: Peter Maydell
---
accel/kvm/kvm-all.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm
On Fri, 31 May 2024 at 17:17, Eric Blake wrote:
>
> On Thu, May 30, 2024 at 07:22:16AM GMT, Eric Blake wrote:
> > The following changes since commit 3b2fe44bb7f605f179e5e7feb2c13c2eb3abbb80:
> >
> > Merge tag 'pull-request-2024-05-29' of https://gitlab.com/thuth/qemu into
> > staging
gt;
> Fix the parameter to address_space_write().
>
Coverity CID: 1544772
> Reported-by: Peter Maydell
> Link:
> https://lore.kernel.org/all/cafeaca-u4sytgwtksb__y+_+0o2-wwarntm3x8wnhvl1wfh...@mail.gmail.com/
> Fixes: 6bda41a69bdc ("hw/cxl: Add clear poison mailbox command support.&
On Fri, 31 May 2024 at 14:48, Peter Maydell wrote:
>
> On Fri, 24 May 2024 at 18:08, Don Porter wrote:
> >
> > This version of the 'info pg' command adopts Peter Maydell's request
> > to write some guest-agnostic page table iterator and accessor code,
> > along wi
avoid the need to change them again in future if the build path
changes again.
This change was made with a search-and-replace of (/qemu)?
to .*/qemu .
Signed-off-by: Peter Maydell
---
As usual with COMPONENTS.md changes, somebody with Coverity admin
access needs to make all the changes by hand
On Tue, 21 May 2024 at 00:26, David Hubbard wrote:
>
> From: Cord Amfmgm
>
> This changes the way the ohci emulation handles a Transfer Descriptor with
> "Current Buffer Pointer" set to "Buffer End" + 1.
>
> The OHCI spec 4.3.1.2 Table 4-2 allows td.cbp to be one byte more than td.be
> to signal
On Fri, 24 May 2024 at 18:08, Don Porter wrote:
>
> This version of the 'info pg' command adopts Peter Maydell's request
> to write some guest-agnostic page table iterator and accessor code,
> along with architecture-specific hooks. The first patch in this
> series contributes a generic page
On Mon, 20 May 2024 at 19:48, Perry Hung wrote:
>
> Philippe, Peter,
>
> Thank you for the comments. I am not even sure what the semantics of
> putting a breakpoint or watchpoint
> on device regions are supposed to be. I would imagine it is
> architecture-specific as to whether this is even
On Fri, 3 May 2024 at 17:53, Dorjoy Chowdhury wrote:
>
> On Fri, May 3, 2024 at 10:28 PM Peter Maydell
> wrote:
> >
> > On Fri, 19 Apr 2024 at 19:31, Dorjoy Chowdhury
> > wrote:
> > >
> > > Some ARM CPUs advertise themselves as SMT by having the MT
criptor endianness bug")
Signed-off-by: Peter Maydell
---
hw/dma/xlnx_dpdma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c
index dde4aeca401..a685bd28bb8 100644
--- a/hw/dma/xlnx_dpdma.c
+++ b/hw/dma/xlnx_dpdma.
Ping! This looks like it should be an easy one-liner fix
for a Coverity-detected read-from-bogus-memory bug --
could one of the CXL folks have a look at it and send
a patch, please ?
thanks
-- PMM
On Fri, 3 May 2024 at 13:45, Peter Maydell wrote:
>
> On Mon, 26 Jun 2023 at 13:28, Mic
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-23-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 6 --
target/arm/tcg/translate.h | 4 +
target/arm/tcg/gengvec.c
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-27-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 22 ++
2 files
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-30-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 8
target/arm/tcg/translate-a64.c | 77
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-22-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 11 +++
2 files changed, 5
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-19-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/gengvec.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-25-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 7 --
target/arm/tcg/translate.h | 4 +
target/arm/tcg/gengvec.c
t;
remains out-of-order, because this is not its own file
but is currently part of the aspeed.rst file.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240520141421.1895138-1-peter.mayd...@linaro.org
---
docs/system/target-a
From: Sebastian Huber
The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only
one core). Add support for up to two simulated cores.
Signed-off-by: Sebastian Huber
Message-id: 20240524120837.10057-3-sebastian.hu...@embedded-brains.de
Reviewed-by: Peter Maydell
[PMM
From: Richard Henderson
No need for a full comparison; xor produces non-zero bits
for QC just fine.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/gengvec.c | 32
as default to have stable set of features enabled
by default. It is still supported and can be selected with "--cpu"
argument.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Message-id: 20240523165353.6547-1-marcin.juszkiew...@linaro.org
Signed-off-by: Peter Maydell
---
h
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240528203044.612851-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 10 +
target/arm/tcg/translate.h | 4
target/arm/tcg
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4 ++
target/arm/tcg/translate-a64.c | 74
.8102-3-sebastian.hu...@embedded-brains.de
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/intc/arm_gic.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 04e5a11660c..806832439b4 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
-by: Peter Maydell
---
tests/avocado/machine_aarch64_sbsaref.py | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado/machine_aarch64_sbsaref.py
index 98c76c1ff70..6bb82f2a03c 100644
--- a/tests/avocado
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-29-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 5
target/arm/tcg/translate-a64.c | 51
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 6 ++
target/arm/tcg/translate-a64.c | 22 +++---
2
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-24-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 11 +++
2 files changed, 5
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240528203044.612851-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 8
target/arm/tcg/translate.h | 4
target/arm/tcg/neon
From: Richard Henderson
These are faux 2-operand instructions, reading from rd.
Sort them next to the other three-operand same insns for clarity.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-9-richard.hender...@linaro.org
Signed-off-by: Peter
From: Richard Henderson
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240528203044.612851-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/gengvec.c | 9 +
1 file changed, 9 insertions(+)
diff
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-18-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 12 +++
target/arm/tcg/translate-a64.c | 132
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 16 +
target/arm/tcg/translate-a64.h | 6 ++
target/arm/tcg/gengvec64.c | 110
From: Sebastian Huber
The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the
corresponding Qemu device to the xilinx-zynq-a9 machine.
Signed-off-by: Sebastian Huber
Message-id: 20240524120837.10057-2-sebastian.hu...@embedded-brains.de
Reviewed-by: Peter Maydell
Signed-off
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-34-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4 ++
target/arm/tcg/translate-a64.c | 108
as a nop, which is architecturally permitted and
matches the way we currently make WFE a nop.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20240430140035.3889879-3-peter.mayd...@linaro.org
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 8 ++
target/arm/tcg/translate.h | 4 +++
target/arm/tcg/neon
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 22 +++---
2 files
but about to
leave it.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20240430140035.3889879-2-peter.mayd...@linaro.org
---
include/hw/core/tcg-cpu-ops.h | 15 +--
target/i386/tcg/helper-tcg.h| 2 +-
accel/tcg
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 11
target/arm/tcg/translate-a64.c | 96
From: Richard Henderson
We already have a gvec helper for the operations, but we aren't
using it on the aa32 neon side. Create a unified expander for
use by both aa32 and aa64 translators.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-31
-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/cpu64.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c15d086049f..862d2b92fa4 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -109,7 +109,11 @@ void
):
tests/avocado: update sbsa-ref firmware
arm/sbsa-ref: move to Neoverse-N2 as default
target/arm: Disable SVE extensions when SVE is disabled
Peter Maydell (3):
docs/system/target-arm: Re-alphabetize board list
accel/tcg: Make TCGCPUOps::cpu_exec_halt return bool for whether
From: Richard Henderson
These are the only instructions in the 3 source scalar class.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240528203044.612851-33-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 10
From: Richard Henderson
These are the last instructions within disas_simd_three_reg_same
and disas_simd_scalar_three_reg_same, so remove them.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240528203044.612851-32-richard.hender...@linaro.org
Signed-off-by: Peter
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 7 ++
target/arm/tcg/translate-a64.c | 40
be=0qemu-system-x86_64:
> ../../hw/usb/core.c:744: usb_ep_get: Assertion `pid == USB_TOKEN_IN || pid ==
> USB_TOKEN_OUT' failed.
> Aborted (core dumped)
[1] The OS disk image has been emailed to phi...@linaro.org, m...@tls.msk.ru,
and kra...@redhat.com:
* testBadSetup.img.xz
* sha256: 0
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4 +++
target/arm/tcg/translate-a64.c | 48
From: Richard Henderson
This eliminates the last uses of these neon helpers.
Incorporate the MO_64 expanders as an option to the vector expander.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-6-richard.hender...@linaro.org
Signed-off-by: Peter
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-26-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 11 +++
2 files changed, 5
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-21-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 6 --
target/arm/tcg/translate.h | 5 ++
target/arm/tcg/gengvec.c
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-28-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 22 ++
2 files
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-20-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/gengvec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/arm
1."
Signed-off-by: Sebastian Huber
Message-id: 20240524113256.8102-2-sebastian.hu...@embedded-brains.de
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/intc/arm_gic.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic
From: Richard Henderson
This eliminates the last uses of these neon helpers.
Incorporate the MO_64 expanders as an option to the vector expander.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-7-richard.hender...@linaro.org
Signed-off-by: Peter
On Tue, 30 Apr 2024 at 15:00, Peter Maydell wrote:
>
> FEAT_WFxT introduces new instructions WFIT and WFET, which are like
> the existing WFI and WFE but allow the guest to pass a timeout value
> in a register. The instructions will wait for an interrupt/event as
> usual, but
On Fri, 31 May 2024 at 09:54, Alex Bennée wrote:
>
> Brian Cain writes:
> > Related: would a .clang-format file also be useful? git-clang-format
> > can be used to apply formatting changes only on the code that's been
> > changed.
>
> As a pre-commit hook? Or via something like clangd?
I think
On Fri, 31 May 2024 at 05:20, Itaru Kitayama wrote:
>
>
>
> > On May 30, 2024, at 22:30, Philippe Mathieu-Daudé wrote:
> >
> > Cc'ing more developers
> >
> > On 30/5/24 06:30, Itaru Kitayama wrote:
> >> Hi,
> >> When I see a Realm VM creation fails with:
> >> Unexpected error in
On Thu, 30 May 2024 at 18:37, Richard Henderson
wrote:
>
> On 5/30/24 05:51, Peter Maydell wrote:
> >> @@ -87,13 +87,13 @@ sub progress_update($)
> >> my $barlen = int($proglen * $done / $progmax);
> >> if ($barlen != $lastprog) {
&
On Tue, 30 Apr 2024 at 18:15, Alex Bennée wrote:
> The x86 version is essentially being called for side effects. Do we want
> to document this usage in the method?
I plan to take these two patches into target-arm.next, with
a slightly beefed up doc comment:
/**
* @cpu_exec_halt:
On Tue, 21 May 2024 at 00:26, David Hubbard wrote:
>
> From: Cord Amfmgm
>
> This changes the way the ohci emulation handles a Transfer Descriptor with
> "Current Buffer Pointer" set to "Buffer End" + 1.
>
> The OHCI spec 4.3.1.2 Table 4-2 allows td.cbp to be one byte more than td.be
> to signal
On Sun, 26 May 2024 at 21:46, Richard Henderson
wrote:
>
> From: Marcin Juszkiewicz
>
> Cc: qemu-sta...@nongnu.org
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304
> Reported-by: Marcin Juszkiewicz
> Signed-off-by: Richard Henderson
> ---
Applied to target-arm.next, thanks.
On Tue, 28 May 2024 at 21:31, Richard Henderson
wrote:
>
> Changes for v3:
> * Reword prefetch unpredictable patch.
> * Validate vector length when qc is an implied operand.
> * Adjust some legacy decode based on review.
> * Apply r-b.
>
> Patches needing review:
>
On Thu, 30 May 2024 at 12:23, Alex Bennée wrote:
>
> Hi Peter,
>
> Looking at bug #2322 I wanted to make sure SYS_GET_CMDLINE works as I
> expected. While at it I needed to fix a compile error with headers
> which I guess we got away with on earlier compilers.
>
> I've added an editorconfig for
m/tcg/translate-a64.c | 113 ++---
> target/arm/tcg/vec_helper.c| 64 +++
> 5 files changed, 245 insertions(+), 64 deletions(-)
Reviewed-by: Peter Maydell
thanks
-- PMM
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