On 06/06/16 18:58, Pranith Kumar wrote:
> On Mon, Jun 6, 2016 at 11:49 AM, Sergey Fedorov wrote:
>> On 06/06/16 18:47, Pranith Kumar wrote:
>>> On Mon, Jun 6, 2016 at 11:44 AM, Sergey Fedorov
>>> wrote:
>>>> On 03/06/16 21:27, Pranith Kumar wrote:
>&g
On 06/06/16 18:47, Pranith Kumar wrote:
> On Mon, Jun 6, 2016 at 11:44 AM, Sergey Fedorov wrote:
>> On 03/06/16 21:27, Pranith Kumar wrote:
>>> On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson wrote:
>>>> What if we have tcg_canonicalize_memop (or some such
On 03/06/16 21:27, Pranith Kumar wrote:
> On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson wrote:
>> Hum. That does seem helpful-ish. But I'm not certain how helpful it is to
>> complicate the helper functions even further.
>>
>> What if we have tcg_canonicalize_memop (or some such) split off t
On 06/06/16 11:58, Alex Bennée wrote:
> Sergey Fedorov writes:
>
>> On 15/04/16 17:23, Alex Bennée wrote:
>>> diff --git a/cpus.c b/cpus.c
>>> index 860e2a9..daa92c7 100644
>>> --- a/cpus.c
>>> +++ b/cpus.c
>>> @@ -171,12 +171,2
On 06/06/16 11:54, Alex Bennée wrote:
> Sergey Fedorov writes:
>
>> On 15/04/16 17:23, Alex Bennée wrote:
>>> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
>>> index f695577..858055b 100644
>>> --- a/include/exec/exec-all.h
>>> ++
On 06/06/16 11:54, Alex Bennée wrote:
> Sergey Fedorov writes:
>
>> On 15/04/16 17:23, Alex Bennée wrote:
>>> diff --git a/cputlb.c b/cputlb.c
>>> index 1412049..42a3b07 100644
>>> --- a/cputlb.c
>>> +++ b/cputlb.c
(snip)
>>> @@ -89,6
On 06/06/16 11:50, Alex Bennée wrote:
> Sergey Fedorov writes:
>
>> On 15/04/16 17:23, Alex Bennée wrote:
>>> diff --git a/cpus.c b/cpus.c
>>> index 9177161..860e2a9 100644
>>> --- a/cpus.c
>>> +++ b/cpus.c
>>> @@ -928,6 +928,
On 15/04/16 17:23, Alex Bennée wrote:
> This makes multi-threading the default for 32 bit ARM on x86. It has
> been tested with Debian Jessie as well as my extended KVM unit tests
> which stress the SMC and TB invalidation code. Those tests can be found
> at:
>
> https://github.com/stsquad/kvm-un
On 15/04/16 17:23, Alex Bennée wrote:
> From: KONRAD Frederic
>
> Instead of flushing each individual vCPU use the tlb_flush_page_all
> functions which is async enabled for MTTCG.
>
> Signed-off-by: KONRAD Frederic
> Signed-off-by: Alex Bennée
> ---
> include/exec/exec-all.h | 3 +++
> target-
On 15/04/16 17:23, Alex Bennée wrote:
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index f695577..858055b 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -307,6 +307,7 @@ struct TBContext {
>
> void tb_free(TranslationBlock *tb);
> void tb_flush
On 15/04/16 17:23, Alex Bennée wrote:
> +/*
> + * Safe work interface
> + *
> + * Safe work is defined as work that requires the system to be
> + * quiescent before making changes.
> + */
> +
> +void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, void *data)
> +{
> +CPUState *iter;
On 15/04/16 17:23, Alex Bennée wrote:
> diff --git a/cputlb.c b/cputlb.c
> index 1412049..42a3b07 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -56,22 +56,14 @@
> } \
> } while (0)
>
> +/* We need a solution for stuffing 64 bit pointers in 32 bit ones if
> + * we care about this combination
On 15/04/16 17:23, Alex Bennée wrote:
> diff --git a/cpu-exec-common.c b/cpu-exec-common.c
> index 3d7eaa3..c2f7c29 100644
> --- a/cpu-exec-common.c
> +++ b/cpu-exec-common.c
> @@ -79,3 +79,4 @@ void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
> cpu->current_tb = NULL;
> siglongjmp
On 03/06/16 23:43, Peter Maydell wrote:
> On 3 June 2016 at 20:49, Sergey Fedorov wrote:
>> I'm not so sure about acq/rel flags. Is there any architecture which has
>> explicit acq/rel barriers? I suppose acq/rel memory access instructions
>> are always load-link and
On 03/06/16 21:27, Pranith Kumar wrote:
> On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson wrote:
>> >
>> > Hum. That does seem helpful-ish. But I'm not certain how helpful it is to
>> > complicate the helper functions even further.
>> >
>> > What if we have tcg_canonicalize_memop (or some such
On 03/06/16 21:30, Pranith Kumar wrote:
> On Thu, Jun 2, 2016 at 9:08 PM, Richard Henderson wrote:
>> On 06/02/2016 02:37 PM, Sergey Fedorov wrote:
>>>
>>> It would give us three TCG operations for each memory operation instead
>>> of one. But then we
On 03/06/16 20:29, Sergey Fedorov wrote:
> On 03/06/16 20:22, Emilio G. Cota wrote:
>> On Sat, May 28, 2016 at 21:15:06 +0300, Sergey Fedorov wrote:
>>> On 25/05/16 04:13, Emilio G. Cota wrote:
>>> (snip)
>>>> +double qdist_avg(const struct qdist *dist
On 03/06/16 20:22, Emilio G. Cota wrote:
> On Sat, May 28, 2016 at 21:15:06 +0300, Sergey Fedorov wrote:
>> On 25/05/16 04:13, Emilio G. Cota wrote:
>> (snip)
>>> +double qdist_avg(const struct qdist *dist)
>>> +{
>>> +unsigned long count;
On 15/04/16 17:23, Alex Bennée wrote:
> diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
> index 5dba7db..94e7110 100644
> --- a/include/qemu/atomic.h
> +++ b/include/qemu/atomic.h
> @@ -123,6 +123,16 @@
> _old; \
> }
On 03/06/16 18:45, Richard Henderson wrote:
> On 06/03/2016 08:16 AM, Sergey Fedorov wrote:
>> On 03/06/16 04:08, Richard Henderson wrote:
>> So your suggestion is to generate different TCG opcode sequences
>> depending on the underlying target architecture? And you are again
On 03/06/16 14:41, Emilio G. Cota wrote:
> On Sun, May 29, 2016 at 23:45:23 +0300, Sergey Fedorov wrote:
>> On 25/05/16 04:13, Emilio G. Cota wrote:
>>> diff --git a/tests/qht-bench.c b/tests/qht-bench.c
>>> new file mode 100644
>>> index 000..30d27c8
&
On 03/06/16 14:01, Emilio G. Cota wrote:
> On Sun, May 29, 2016 at 22:52:27 +0300, Sergey Fedorov wrote:
>>> +/*
>>> + * Find the last valid entry in @head, and swap it with @orig[pos], which
>>> has
>>> + * just been invalidated.
>>> + */
>
On 03/06/16 12:18, Emilio G. Cota wrote:
> On Sun, May 29, 2016 at 22:52:27 +0300, Sergey Fedorov wrote:
>> I was just wondering if it could be worthwhile to pass a hash function
>> when initializing a QHT. Then we could have variants of qht_insert(),
>> qht_remove() and qh
On 03/06/16 04:08, Richard Henderson wrote:
> On 06/02/2016 02:37 PM, Sergey Fedorov wrote:
>> On 03/06/16 00:18, Richard Henderson wrote:
>>> On 06/02/2016 01:38 PM, Sergey Fedorov wrote:
>>>> On 02/06/16 23:36, Richard Henderson wrote:
>>>>> On 06/02/
On 03/06/16 00:18, Richard Henderson wrote:
> On 06/02/2016 01:38 PM, Sergey Fedorov wrote:
>> On 02/06/16 23:36, Richard Henderson wrote:
>>> On 06/02/2016 09:30 AM, Sergey Fedorov wrote:
>>>> I think we need to extend TCG load/store instruction attributes to
>&g
On 02/06/16 23:36, Richard Henderson wrote:
> On 06/02/2016 09:30 AM, Sergey Fedorov wrote:
>> I think we need to extend TCG load/store instruction attributes to
>> provide information about guest ordering requirements and leave this TCG
>> operation only for explici
On 15/04/16 17:23, Alex Bennée wrote:
> Useful for counting down.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Sergey Fedorov
> ---
> include/qemu/atomic.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
> in
On 31/05/16 21:39, Pranith Kumar wrote:
> Signed-off-by: Pranith Kumar
> Signed-off-by: Richard Henderson
> ---
> target-arm/translate.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index c946c0e..e1b16c0 100644
On 31/05/16 21:39, Pranith Kumar wrote:
> Cc: Alexander Graf
> Signed-off-by: Richard Henderson
> Signed-off-by: Pranith Kumar
> ---
> tcg/s390/tcg-target.inc.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
> index e95b04
On 02/06/16 00:35, Richard Henderson wrote:
> On 06/01/2016 11:43 AM, Pranith Kumar wrote:
>> All we want to do here is map a barrier instruction from guest to a
>> barrier instruction on hist. This mapping is 1:1 if the host has
>> barrier instructions with matching semantics. Otherwise we generat
On 31/05/16 21:39, Pranith Kumar wrote:
> diff --git a/tcg/README b/tcg/README
> index f4a8ac1..cfe79d7 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -402,6 +402,23 @@ double-word product T0. The later is returned in two
> single-word outputs.
>
> Similar to mulu2, except the two inputs T1
On 02/06/16 19:00, Alex Bennée wrote:
> Sergey Fedorov writes:
>> On 05/04/16 18:32, Alex Bennée wrote:
>>> @@ -1179,6 +1198,14 @@ static void *qemu_tcg_cpu_thread_fn(void *arg)
>>> }
>>> }
>>>
>>> +/* Set to kick if we
On 01/06/16 13:30, Alex Bennée wrote:
> Sergey Fedorov writes:
>
>> On 05/04/16 18:32, Alex Bennée wrote:
>> (snip)
>>> diff --git a/exec.c b/exec.c
>>> index 17f390e..c46c123 100644
>>> --- a/exec.c
>>> +++ b/exec.c
>>> @@ -211
On 31/05/16 10:46, Alex Bennée wrote:
> Sergey Fedorov writes:
>
>> On 25/05/16 04:13, Emilio G. Cota wrote:
>>> diff --git a/include/qemu/qht.h b/include/qemu/qht.h
>>> new file mode 100644
>>> index 000..aec60aa
>>> --- /dev/null
>>>
ckets 8192/8192 (100.00% head buckets used)
> TB hash occupancy 98.30% avg chain occ. Histogram:
> [95.3,95.8)%|▁▁▃▄▃▄▁▇▁█|[99.5,100.0]%
> TB hash avg chain 22.070 buckets. Histogram:
> [15.0,16.7)|▁▂▅▄█▅|[30.3,32.0]
I personally don't see much use of the histogram labels.
= get_page_addr_code(desc.env, pc);
> +desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
> h = tb_hash_func(phys_pc, pc, flags);
> -
> -/* Start at head of the hash entry */
> -ptb1 = tb_hash_head = &tcg_ctx.tb_ctx.tb_phys_hash[h];
> -tb = *ptb1;
> -
> -while (tb) {
On 25/05/16 04:13, Emilio G. Cota wrote:
> diff --git a/tests/test-qht-par.c b/tests/test-qht-par.c
> new file mode 100644
> index 000..fc0cb23
> --- /dev/null
> +++ b/tests/test-qht-par.c
> @@ -0,0 +1,56 @@
(snip)
> +
> +#define TEST_QHT_STRING "tests/qht-bench 1>/dev/null 2>&1 -R -S0.1 -D1000
On 25/05/16 04:13, Emilio G. Cota wrote:
> diff --git a/tests/qht-bench.c b/tests/qht-bench.c
> new file mode 100644
> index 000..30d27c8
> --- /dev/null
> +++ b/tests/qht-bench.c
> @@ -0,0 +1,474 @@
(snip)
> +static void do_rw(struct thread_info *info)
> +{
> +struct thread_stats *stats =
On 25/05/16 04:13, Emilio G. Cota wrote:
> Reviewed-by: Alex Bennée
> Reviewed-by: Richard Henderson
> Signed-off-by: Emilio G. Cota
Acked-by: Sergey Fedorov
> ---
> tests/.gitignore | 1 +
> tests/Makefile | 6 ++-
> t
On 29/05/16 22:52, Sergey Fedorov wrote:
> On 25/05/16 04:13, Emilio G. Cota wrote:
>> +
>> +/* call with head->lock held */
>> +static bool qht_insert__locked(struct qht *ht, struct qht_map *map,
>> + struct qht_bucket *he
On 25/05/16 04:13, Emilio G. Cota wrote:
> diff --git a/include/qemu/qht.h b/include/qemu/qht.h
> new file mode 100644
> index 000..aec60aa
> --- /dev/null
> +++ b/include/qemu/qht.h
> @@ -0,0 +1,183 @@
(snip)
> +/**
> + * qht_init - Initialize a QHT
> + * @ht: QHT to be initialized
> + * @n_el
On 25/05/16 04:13, Emilio G. Cota wrote:
> Reviewed-by: Richard Henderson
> Signed-off-by: Emilio G. Cota
Acked-by: Sergey Fedorov
> ---
> tests/.gitignore | 1 +
> tests/Makefile | 6 +-
> tests/test-qdist.c | 369
> +++
On 25/05/16 04:13, Emilio G. Cota wrote:
> diff --git a/util/qdist.c b/util/qdist.c
> new file mode 100644
> index 000..3343640
> --- /dev/null
> +++ b/util/qdist.c
> @@ -0,0 +1,386 @@
(snip)
> +
> +void qdist_add(struct qdist *dist, double x, long count)
> +{
> +struct qdist_entry *entry =
ie arm
> bootup). This is dealt with later in this series.
>
> Reviewed-by: Richard Henderson
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Cota
Reviewed-by: Sergey Fedorov
> ---
> cpu-exec.c | 4 ++--
> include/exec/tb-hash.h | 8 ++--
>
On 25/05/16 04:13, Emilio G. Cota wrote:
> This will be used by upcoming changes for hashing the tb hash.
>
> Add this into a separate file to include the copyright notice from
> xxhash.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Emilio G. Cota
Review
On 28/05/16 00:10, Emilio G. Cota wrote:
> On Fri, May 27, 2016 at 23:53:01 +0300, Sergey Fedorov wrote:
>> On 25/05/16 04:13, Emilio G. Cota wrote:
>>> Taken from the linux kernel.
>>>
>>> Reviewed-by: Richard Henderson
>>> Reviewed-by: A
On 25/05/16 04:13, Emilio G. Cota wrote:
> Taken from the linux kernel.
>
> Reviewed-by: Richard Henderson
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Cota
> ---
> include/qemu/processor.h | 30 ++
> 1 file changed, 30 insertions(+)
> create mode 100644 in
On 25/05/16 04:13, Emilio G. Cota wrote:
> It is a more appropriate name, now that the mutex embedded
> in the seqlock is gone.
>
> Reviewed-by: Alex Bennée
> Reviewed-by: Richard Henderson
> Signed-off-by: Emilio G. Cota
Reviewed-by: Sergey Fedorov
> ---
> cpu
On 25/05/16 04:13, Emilio G. Cota wrote:
> This option is unused; besides, it bloats the struct when not needed.
> Let's just let writers define their own locks elsewhere.
>
> Reviewed-by: Alex Bennée
> Reviewed-by: Richard Henderson
> Signed-off-by: Emilio G. Cota
Revi
On 25/05/16 04:13, Emilio G. Cota wrote:
> Reviewed-by: Richard Henderson
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Cota
Reviewed-by: Sergey Fedorov
> ---
> include/qemu/compiler.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/qemu/c
On 27/05/16 18:25, Paolo Bonzini wrote:
>
> On 27/05/2016 17:07, Sergey Fedorov wrote:
>>>>>> 1. Make 'cpu->thread_kicked' access atomic
>>>>>> 2. Remove global 'exit_request' and use per-CPU 'exit_request'
>>&
On 27/05/16 17:55, Paolo Bonzini wrote:
>
> On 27/05/2016 15:57, Sergey Fedorov wrote:
>> 1. Make 'cpu->thread_kicked' access atomic
>> 2. Remove global 'exit_request' and use per-CPU 'exit_request'
>> 3. Change how 'current_cpu
On 05/04/16 18:32, Alex Bennée wrote:
> From: KONRAD Frederic
>
> This allows the user to switch on multi-thread behaviour and spawn a
> thread per-vCPU. For a simple test like:
>
> ./arm/run ./arm/locking-test.flat -smp 4 -tcg mttcg=on
>
> Will now use 4 vCPU threads and have an expected FAIL (
On 27/05/16 17:17, Pranith Kumar wrote:
> Hi Sergey,
>
> Sergey Fedorov writes:
>
>> On 27/05/16 04:00, Richard Henderson wrote:
>>> diff --git a/tci.c b/tci.c
>>> index b488c0d..53b3f71 100644
>>> --- a/tci.c
>>> +++ b/tci.c
>>> @@
On 27/05/16 04:00, Richard Henderson wrote:
> diff --git a/tci.c b/tci.c
> index b488c0d..53b3f71 100644
> --- a/tci.c
> +++ b/tci.c
> @@ -1236,6 +1236,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t
> *tb_ptr)
> tcg_abort();
> }
> break;
> +
On 27/05/16 04:00, Richard Henderson wrote:
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 6d0410c..b772d90 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END)
> # define IMPL64 TCG_OPF_64BIT
> #endif
>
> +DEF(fence, 0, 0, 0, TCG_OPF_SI
On 26/05/16 14:21, Paolo Bonzini wrote:
>
> On 26/05/2016 12:42, Sergey Fedorov wrote:
>> I'm afraid even our recent efforts in
>> multi-threaded TCG won't change the situation. The problem is that it
>> would require to translate somehow ARM's exclusive a
On 05/04/16 18:32, Alex Bennée wrote:
> diff --git a/cpus.c b/cpus.c
> index e118fdf..46732a5 100644
> --- a/cpus.c
> +++ b/cpus.c
(snip)
> @@ -1109,7 +1108,7 @@ static void *qemu_dummy_cpu_thread_fn(void *arg)
> #endif
> }
>
> -static void tcg_exec_all(void);
> +static int tcg_cpu_exec(CPUStat
On 25/05/16 15:34, Jeff Epler wrote:
> Hi. Before I take the time to prepare a detailed bug report, I wanted to
> ask whether I'm doing something that is expected to work, or expected not
> to work.
>
> I am a developer of the LinuxCNC, Free and Open Source software for control
> of milling machin
On 25/05/16 22:59, Pranith Kumar wrote:
> On Wed, May 25, 2016 at 3:43 PM, Sergey Fedorov wrote:
>> I think it would better not to defer native support for the operation.
>> It should be relatively simple instruction. Otherwise we could wind up
>> deferring this indefinitely
On 25/05/16 22:25, Alex Bennée wrote:
> Richard Henderson writes:
>> On 05/24/2016 10:18 AM, Pranith Kumar wrote:
>>> Signed-off-by: Pranith Kumar
>>> ---
>>> tcg/i386/tcg-target.h | 1 +
>>> tcg/i386/tcg-target.inc.c | 9 +
>>> tcg/tcg-opc.h | 2 +-
>>> tcg/tcg.c
On 25/05/16 21:03, Paolo Bonzini wrote:
>> The page table seems to be protected by 'mmap_lock' in user mode
>> emulation but by 'tb_lock' in system mode emulation. It may turn to be
>> possible to read it safely even with no lock held.
> Yes, it is possible to at least follow the radix tree safely
On 16/05/16 17:36, Sergey Fedorov wrote:
> On 16/05/16 16:49, Richard Henderson wrote:
>> On 05/16/2016 06:13 AM, Sergey Fedorov wrote:
>>> It is not safe to make a direct jump to a TB spanning two pages in
>>> system emulation because the mapping for the second page
On 11/04/16 23:00, Sergey Fedorov wrote:
> On 05/04/16 18:32, Alex Bennée wrote:
>
> (snip)
>> +
>> +Memory maps and TLBs
>> +
>> +
>> +The memory handling code is fairly critical to the speed of memory
>> +access in the emulate
On 25/05/16 11:52, Alex Bennée wrote:
> Sergey Fedorov writes:
>
>> On 24/05/16 22:56, Emilio G. Cota wrote:
>>> On Tue, May 24, 2016 at 09:08:01 +0200, Paolo Bonzini wrote:
>>>> On 23/05/2016 19:09, Emilio G. Cota wrote:
>>>>> PS. And really eq
On 25/05/16 01:07, Emilio G. Cota wrote:
> On Mon, May 23, 2016 at 23:28:27 +0300, Sergey Fedorov wrote:
>> What if we turn qht::lock into a mutex and change the function as follows:
>>
>> static inline
>> struct qht_bucket *qht_bucket_lock__no_stale(struct qh
On 05/04/16 18:32, Alex Bennée wrote:
> diff --git a/cpu-exec.c b/cpu-exec.c
> index bd50fef..f558508 100644
> --- a/cpu-exec.c
> +++ b/cpu-exec.c
> @@ -28,6 +28,7 @@
> #include "qemu/rcu.h"
> #include "exec/tb-hash.h"
> #include "exec/log.h"
> +#include "qemu/main-loop.h"
> #if defined(TARGET_
On 24/05/16 23:06, Emilio G. Cota wrote:
> For correctness, smp_read_barrier_depends() is only required to
> emit a barrier on Sparc hosts. However, we are currently emitting
> a consume fence unconditionally.
>
> Fix it by keeping the consume fence if we're compiling with Thread
> Sanitizer, since
On 24/05/16 22:56, Emilio G. Cota wrote:
> On Tue, May 24, 2016 at 09:08:01 +0200, Paolo Bonzini wrote:
>> On 23/05/2016 19:09, Emilio G. Cota wrote:
>>> PS. And really equating smp_wmb/rmb to release/acquire as we have under
>>> #ifdef __ATOMIC is hard to justify, other than to please tsan.
>> Tha
I think I'm done reviewing v5. (Though I haven't reviewed tests and
statistics patches.)
Kind regards,
Sergey
On 14/05/16 06:34, Emilio G. Cota wrote:
> This patchset applies on top of tcg-next (8b1fe3f4 "cpu-exec:
> Clean up 'interrupt_request' reloading", tagged "pull-tcg-20160512").
>
> For re
On 14/05/16 06:34, Emilio G. Cota wrote:
> +/*
> + * Get a head bucket and lock it, making sure its parent map is not stale.
> + * @pmap is filled with a pointer to the bucket's parent map.
> + *
> + * Unlock with qemu_spin_unlock(&b->lock).
> + */
> +static inline
> +struct qht_bucket *qht_bucket_
On 21/05/16 05:48, Emilio G. Cota wrote:
> On Sat, May 21, 2016 at 01:13:20 +0300, Sergey Fedorov wrote:
>> Although the API is mostly intuitive some kernel-doc-style comments
>> wouldn’t hurt, I think. ;-)
> The nit that bothered me is the "external lock needed" bi
On 20/05/16 15:51, Pranith Kumar wrote:
> Hello all,
>
> I've been selected to participate in GSoC 2016 in the Qemu project. I will be
> mentored by Alex Bennée and will be working on solving memory consistency
> issues in the MTTCG project. In particular we are targeting to get ARM guests
> workin
On 21/05/16 05:48, Emilio G. Cota wrote:
> Thanks for taking a look! If you have time, please check patch 13 out.
> That patch should eventually be merged onto this one.
Actually, I was reviewing the final code with all the series applied :)
I'd like to spend some time and review all the series in
Wow, that's really great stuff!
On 14/05/16 06:34, Emilio G. Cota wrote:
> diff --git a/include/qemu/qht.h b/include/qemu/qht.h
> new file mode 100644
> index 000..c2ab8b8
> --- /dev/null
> +++ b/include/qemu/qht.h
> @@ -0,0 +1,66 @@
> +/*
> + * Copyright (C) 2016, Emilio G. Cota
> + *
> + *
On 18/05/16 23:52, Emilio G. Cota wrote:
> On Wed, May 18, 2016 at 22:51:09 +0300, Sergey Fedorov wrote:
>> On 14/05/16 06:34, Emilio G. Cota wrote:
>>> +static inline void qemu_spin_lock(QemuSpin *spin)
>>> +{
>>> +while (atomic_test_and_set_acquire(&sp
On 14/05/16 06:34, Emilio G. Cota wrote:
> +static inline void qemu_spin_lock(QemuSpin *spin)
> +{
> +while (atomic_test_and_set_acquire(&spin->value)) {
A possible optimization might be using unlikely() here, copmare:
spin.o: file format elf64-littleaarch64
Disassembly of section .text
On 18/05/16 21:29, Emilio G. Cota wrote:
> On Wed, May 18, 2016 at 20:47:56 +0300, Sergey Fedorov wrote:
>> Why don't do like this:
>>
>> #if defined(__foo__)
>> # define ...
>> #elif defined(__bar__)
>> # define ...
>> #else
>> # d
On 14/05/16 06:34, Emilio G. Cota wrote:
> +static inline int qemu_spin_trylock(QemuSpin *spin)
> +{
> +if (atomic_test_and_set_acquire(&spin->value)) {
> +return -EBUSY;
Seems this should be:
return EBUSY;
> +}
> +return 0;
> +}
On 14/05/16 06:34, Emilio G. Cota wrote:
> Taken from the linux kernel.
>
> Reviewed-by: Richard Henderson
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Cota
> ---
> include/qemu/processor.h | 34 ++
> 1 file changed, 34 insertions(+)
> create mode 10064
On 18/05/16 18:44, Peter Maydell wrote:
> On 18 May 2016 at 16:36, Paolo Bonzini wrote:
>> On 18/05/2016 17:35, Peter Maydell wrote:
> $ arm-linux-gnueabi-gcc -march=armv6 -O2 -c a.c
>>> I don't think armv6 is a sufficiently common host for us to
>>> worry too much about how its atomic primiti
On 18/05/16 17:59, Paolo Bonzini wrote:
>
> On 18/05/2016 16:47, Sergey Fedorov wrote:
>>>>>> Why not? AFAIK the reason to avoid __sync primitives is that in most
>>>>>> cases
>>>>>> they include barriers that callers might not necessar
On 18/05/16 17:18, Sergey Fedorov wrote:
> On 18/05/16 03:28, Emilio G. Cota wrote:
>> On Tue, May 17, 2016 at 23:20:11 +0300, Sergey Fedorov wrote:
>>> On 17/05/16 23:04, Emilio G. Cota wrote:
>> (snip)
>>>> +/*
>>>> + * We might we tempted to
On 18/05/16 03:28, Emilio G. Cota wrote:
> On Tue, May 17, 2016 at 23:20:11 +0300, Sergey Fedorov wrote:
>> On 17/05/16 23:04, Emilio G. Cota wrote:
> (snip)
>>> +/*
>>> + * We might we tempted to use __atomic_test_and_set with __ATOMIC_ACQUIRE;
>>> + * how
On 18/05/16 17:05, Paolo Bonzini wrote:
>
> On 18/05/2016 15:59, Sergey Fedorov wrote:
>> But actually (cf include/qemu/atomic.h) we can have:
>>
>>
On 18/05/16 02:18, Emilio G. Cota wrote:
> On Tue, May 17, 2016 at 23:35:57 +0300, Sergey Fedorov wrote:
>> On 17/05/16 22:38, Emilio G. Cota wrote:
>>> On Tue, May 17, 2016 at 20:13:24 +0300, Sergey Fedorov wrote:
>>>> On 14/05/16 06:34, Emilio G. Cota wrote:
On 17/05/16 23:04, Emilio G. Cota wrote:
> On Tue, May 17, 2016 at 12:19:27 -0700, Richard Henderson wrote:
>> On 05/17/2016 10:13 AM, Sergey Fedorov wrote:
>>>>> +static inline void qemu_spin_lock(QemuSpin *spin)
>>>>> +{
>>>>> +while (
On 17/05/16 22:19, Richard Henderson wrote:
> On 05/17/2016 10:13 AM, Sergey Fedorov wrote:
>>>> +static inline void qemu_spin_lock(QemuSpin *spin)
>>>> +{
>>>> +while (atomic_test_and_set_acquire(&spin->value)) {
>> >From gcc-
On 17/05/16 22:57, Sergey Fedorov wrote:
> On 17/05/16 22:19, Richard Henderson wrote:
>> On 05/17/2016 10:13 AM, Sergey Fedorov wrote:
>>>>> +static inline void qemu_spin_lock(QemuSpin *spin)
>>>>> +{
>>>>> +while (atomic_test_and_set_acqu
On 17/05/16 22:38, Emilio G. Cota wrote:
> On Tue, May 17, 2016 at 20:13:24 +0300, Sergey Fedorov wrote:
>> On 14/05/16 06:34, Emilio G. Cota wrote:
(snip)
>>> +while (atomic_read(&spin->value)) {
>>> +cpu_relax();
>>> +}
>
On 14/05/16 06:34, Emilio G. Cota wrote:
> For some workloads such as arm bootup, tb_phys_hash is performance-critical.
> The is due to the high frequency of accesses to the hash table, originated
> by (frequent) TLB flushes that wipe out the cpu-private tb_jmp_cache's.
> More info:
> https://lis
On 14/05/16 06:34, Emilio G. Cota wrote:
> This will be used by upcoming changes for hashing the tb hash.
>
> Add this into a separate file to include the copyright notice from
> xxhash.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Emilio G. Cota
> ---
> include/exec/tb-hash-xx.h | 94
>
On 14/05/16 06:34, Emilio G. Cota wrote:
> When __atomic is not available, we use full memory barriers instead
> of smp/wmb, since acquire/release barriers apply to all memory
> operations and not just to loads/stores, respectively.
>
> Signed-off-by: Emilio G. Cota
> ---
> include/qemu/atomic.h
On 17/05/16 19:23, Paolo Bonzini wrote:
>
> On 17/05/2016 18:15, Sergey Fedorov wrote:
>> On 14/05/16 06:34, Emilio G. Cota wrote:
>>> This new helper expands to __atomic_test_and_set with acquire semantics
>>> where available; otherwise it expands to __sync_test_
On 14/05/16 06:34, Emilio G. Cota wrote:
> This new helper expands to __atomic_test_and_set with acquire semantics
> where available; otherwise it expands to __sync_test_and_set, which
> has acquire semantics.
Why don't also add atomic_clear_release() for completeness?
Kind regards,
Sergey
>
> S
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> cpu-exec-common.c | 2 +-
> translate-all.c | 12
> translate-all.h | 2 +-
> user-exec.c | 41 +
> 4 files changed, 39 insertions(+), 18 de
On 16/05/16 19:09, Peter Maydell wrote:
> The exception_action() function in user-exec.c is just a call to
> cpu_loop_exit() for every target CPU except i386. Since this
> function is only called if the target's handle_mmu_fault() hook has
> indicated an MMU fault, and that hook is only called fro
need to do it again in cpu_exit_tb_from_sighandler().
> This then means we don't need to pass a usercontext pointer in to
> handle_cpu_signal() at all.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> user-exec.c | 48 ---
ny exception, so rename
> it to cpu_loop_exit_noexc() and drop the useless unused argument.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> cpu-exec-common.c| 6 ++
> exec.c | 2 +-
> hw/i386/kvmvapic.c | 2 +
On 16/05/16 20:15, Peter Maydell wrote:
> On 16 May 2016 at 18:13, Sergey Fedorov wrote:
>> On 16/05/16 19:09, Peter Maydell wrote:
>>> @@ -1996,7 +1997,10 @@ int page_unprotect(target_ulong address, uintptr_t
>>> pc, void *puc)
>>>
>>>
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