match
Sergey Fedorov (2):
target-arm: Fix GDB breakpoint handling
target-arm: Fix CPU breakpoint handling
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 36 ++--
target-arm/translate-a64.c | 14 --
target-arm/translate.c | 13
GDB breakpoints have higher priority so they have to be checked first.
Should GDB breakpoint match, just return from the debug exception
handler.
Signed-off-by: Sergey Fedorov <serge.f...@gmail.com>
---
target-arm/op_helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/
On 25.09.2015 17:42, Christopher Covington wrote:
> This should help clarify the purpose of the function that returns
> the host system's CPU cycle count.
+1
Best regards,
Sergey
On 18.09.2015 17:07, Sergey Fedorov wrote:
> On 18.09.2015 16:50, Peter Maydell wrote:
>> On 14 September 2015 at 11:51, Sergey Fedorov <serge.f...@gmail.com> wrote:
>> @@ -904,7 +913,16 @@ void arm_debug_excp_handler(CPUState *cs)
>>
On 25.09.2015 14:34, Sergey Fedorov wrote:
> On 18.09.2015 17:07, Sergey Fedorov wrote:
>> On 18.09.2015 16:50, Peter Maydell wrote:
>>> On 14 September 2015 at 11:51, Sergey Fedorov <serge.f...@gmail.com> wrote:
>>> @@ -904,7 +913,16 @@ void ar
On 18.09.2015 13:32, Peter Maydell wrote:
>> +/* Return true if PC matches an installed breakpoint. */
>> > +static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
>> > +{
>> > +CPUBreakpoint *bp;
>> > +
>> > +if (unlikely(!QTAILQ_EMPTY(>breakpoints))) {
>> > +
On 18.09.2015 16:50, Peter Maydell wrote:
> On 14 September 2015 at 11:51, Sergey Fedorov <serge.f...@gmail.com> wrote:
>> A QEMU breakpoint match is not definitely an architectural breakpoint
>> match. If an exception is generated unconditionally during translation,
>
On 18.09.2015 17:11, Peter Maydell wrote:
> On 18 September 2015 at 15:08, Peter Maydell <peter.mayd...@linaro.org> wrote:
>> On 14 September 2015 at 11:53, Sergey Fedorov <serge.f...@gmail.com> wrote:
>>> Implement debug exception routing according to ARM ARM D2.
On 18.09.2015 18:57, Sergey Fedorov wrote:
> On 18.09.2015 17:11, Peter Maydell wrote:
>> On 18 September 2015 at 15:08, Peter Maydell <peter.mayd...@linaro.org>
>> wrote:
>>> On 14 September 2015 at 11:53, Sergey Fedorov <serge.f...@gmail.com> wrote:
&g
On 18.09.2015 17:14, Peter Maydell wrote:
> On 18 September 2015 at 15:07, Sergey Fedorov <serge.f...@gmail.com> wrote:
>> On 18.09.2015 16:50, Peter Maydell wrote:
>>> On 14 September 2015 at 11:51, Sergey Fedorov <serge.f...@gmail.com> wrote:
>>>> -
On 18.09.2015 18:40, Richard Henderson wrote:
> On 09/18/2015 03:32 AM, Peter Maydell wrote:
>>> +if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
>>> +gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
>>> +/* Advance PC so that clearing the breakpoint will
On 18.09.2015 19:36, Peter Maydell wrote:
> On 18 September 2015 at 17:33, Sergey Fedorov <serge.f...@gmail.com> wrote:
>> On 18.09.2015 17:14, Peter Maydell wrote:
>>> On 18 September 2015 at 15:07, Sergey Fedorov <serge.f...@gmail.com> wrote:
>>>>
to the dedicated watchpoint checking callback.
Signed-off-by: Sergey Fedorov <serge.f...@gmail.com>
---
target-arm/cpu.c | 1 +
target-arm/internals.h | 3 +++
target-arm/op_helper.c | 35 +--
3 files changed, 25 insertions(+), 14 deletions(-)
diff --git a/
raising a TCG exception.
Signed-off-by: Sergey Fedorov <serge.f...@gmail.com>
---
exec.c| 5 +
include/qom/cpu.h | 3 +++
qom/cpu.c | 9 +
3 files changed, 17 insertions(+)
diff --git a/exec.c b/exec.c
index 54cd70a..64ed543 100644
--- a/exec.c
+++ b/exec.c
@@ -
breakpoint architecturally matches.
Signed-off-by: Sergey Fedorov <serge.f...@gmail.com>
---
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 20 +++-
target-arm/translate-a64.c | 12 +++-
target-arm/translate.c | 12 +++-
4 files chang
Implement debug exception routing according to ARM ARM D2.3.1 Pseudocode
description of routing debug exceptions.
Signed-off-by: Sergey Fedorov <serge.f...@gmail.com>
---
target-arm/cpu.h | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/target-arm/c
ARM breakpoint and watchpoint emulation misbehavior can be
found at:
https://lists.gnu.org/archive/html/qemu-devel/2015-08/msg02715.html
https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg00527.html
Sergey Fedorov (2):
cpu: Add callback to check architectural watchpoint match
target-arm
On 10.09.2015 16:49, Peter Maydell wrote:
>> @@ -2406,6 +2411,8 @@ static inline int tcg_gen_code_common(TCGContext *s,
>> > check_regs(s);
>> > #endif
>> > }
>> > +tcg_debug_assert(num_insns >= 0);
> This is claiming that every TB will have at least one insn_start,
> right? I
On 11.09.2015 13:32, Peter Maydell wrote:
> On 11 September 2015 at 11:29, Sergey Fedorov <serge.f...@gmail.com> wrote:
>> On 10.09.2015 16:49, Peter Maydell wrote:
>>>> @@ -2406,6 +2411,8 @@ static inline int tcg_gen_code_common(TCGContext *s,
>>>>
On 07.09.2015 16:17, Peter Maydell wrote:
> See review discussion on v1. The arm_boot_info structure includes
> fields that use data types that are only available to source files
> compiled per-target, and the GIC source files are compiled once-only.
Ah, sorry for that.
Best,
Sergey
Hi Peter,
On 04.09.2015 19:22, Peter Maydell wrote:
> +typedef struct ARMLinuxBootIfClass {
> +/*< private >*/
> +InterfaceClass parent_class;
> +
> +/*< public >*/
> +/** arm_linux_init: configure the device for a direct boot
> + * of an ARM Linux kernel (so that device reset
On 02.09.2015 22:45, Peter Maydell wrote:
> Maybe rather than trying to be clever with the existing wp APIs
> we should have support for targets to register "did this really hit?"
> callbacks that get called before the core code tries to really
> generate the exception.
Thank you, Peter, for the
On 28.08.2015 22:21, Peter Maydell wrote:
> The watchpoint code has a chance of cpu_resume_from_signal
> doing the right thing, because we really did have the
> code to do the load/store. However I have a feeling this
> won't interact properly with the fact that ARM needs
> BP_STOP_BEFORE_ACCESS
On 02.09.2015 19:53, Sergey Fedorov wrote:
> On 28.08.2015 22:21, Peter Maydell wrote:
>> The watchpoint code has a chance of cpu_resume_from_signal
>> doing the right thing, because we really did have the
>> code to do the load/store. However I have a feeling this
>&
28.08.2015 22:21, Peter Maydell wrote:
I think what we need to do is have the translate-a64.c
code be smarter, and actually generate the real code
if we're not going to really hit the bp. Except that we
don't really have all the info in the flags to know for
sure about that. So we probably need
Hi all,
Seems there is a bug in ARM breakpoint emulation. I am not sure how to
fix it and I would appreciate any suggestion. It is best illustrated by
a simple test which sets up and enables an unlinked address match
breakpoint but does not enable debug exceptions globally by
MDSCR_EL1.MDE bit.
ping.
On 30.06.2015 12:35, Sergey Fedorov wrote:
Instead of invalidating an original TB in cpu_exec_nocache()
prematurely, just save a link to it in the temporary generated TB. If
cpu_io_recompile() is raised subsequently from the temporary TB,
invalidate the original one as well. That allows
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs
in the same Inner Sharable domain, not just on the current CPU. So we
must use tlbiall_is_write() here.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1
() is called to handle expired instruction
counter in icount mode.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
v2:
* take tcg_ctx.tb_ctx.tb_invalidated_flag into account
cpu-exec.c | 8 ++--
include/exec/exec-all.h | 2 ++
translate-all.c | 8
3 files
On 18.06.2015 23:46, Peter Maydell wrote:
On 17 June 2015 at 16:25, Sergey Fedorov serge.f...@gmail.com wrote:
cp_reg_reset() is called from g_hash_table_foreach() which does not
define a specific ordering of the hash table iteration. Thus doing reset
for registers marked as ALIAS would give
On 19.06.2015 00:01, Peter Maydell wrote:
On 18 June 2015 at 21:57, Sergey Fedorov serge.f...@gmail.com wrote:
On 18.06.2015 23:46, Peter Maydell wrote:
On 17 June 2015 at 16:25, Sergey Fedorov serge.f...@gmail.com wrote:
cp_reg_reset() is called from g_hash_table_foreach() which does
On 18.06.2015 09:57, Paolo Bonzini wrote:
On 17/06/2015 19:54, Sergey Fedorov wrote:
-/* tb_gen_code can flush our orig_tb, invalidate it now */
-tb_phys_invalidate(orig_tb, -1);
-tb = tb_gen_code(cpu, pc, cs_base, flags,
+tb = tb_gen_code(cpu, orig_tb-pc, orig_tb-cs_base
() is called to handle expired instruction
counter in icount mode.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
cpu-exec.c | 8 ++--
include/exec/exec-all.h | 2 ++
translate-all.c | 6 ++
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/cpu
passed an alias register. Then clean up alias
register definitions from needless resetvalue and resetfn.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
target-arm/cpu.c| 2 +-
target-arm/cpu.h| 4 ++--
target-arm/helper.c | 28 +---
3 files changed, 12
On 02.06.2015 16:28, Peter Maydell wrote:
On 2 June 2015 at 14:18, Peter Maydell peter.mayd...@linaro.org wrote:
NB: a bug that's been on my todo list for ages is that the comment
is incorrect about the wildcard being unnecessary -- this was a
misreading of the ARM ARM by me when I wrote that
This patch series combines two changes:
* use correct REVIDR reset value for Cortex-A53/A57
* add missing MIDR AArch32 aliases
Sergey Fedorov (2):
target-arm: Fix REVIDR reset value
target-arm: Add AArch32 MIDR aliases in ARMv8
target-arm/cpu-qom.h | 1 +
target-arm/cpu64.c | 2
On 02.06.2015 16:54, Peter Maydell wrote:
On 2 June 2015 at 13:21, Sergey Fedorov serge.f...@gmail.com wrote:
According to ARM Cortex-A57 TRM, REVIDR reset value should be zero. So
let REVIDR reset value be specified by CPU model and fix it for
Cortex-A57.
Signed-off-by: Sergey Fedorov
According to ARMv8 ARM, there are additional aliases to MIDR system register in
AArch32 state. So add them to the list.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
target-arm/helper.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b
According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let
REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu64.c | 2 ++
target-arm/helper.c | 5
Since ARMv7 with LPAE support, a supersection short translation table
descriptor has had extended base address fields which hold bits 39:32 of
translated address. These fields are IMPDEF in ARMv6 and ARMv7 without
LPAE support.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
target-arm
On 01.06.2015 21:41, Peter Crosthwaite wrote:
On Thu, May 28, 2015 at 4:00 AM, Sergey Fedorov serge.f...@gmail.com wrote:
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5d0f011..fc3f192 100644
--- a/target-arm
Since ARMv7 with LPAE support, a supersection short translation table
descriptor has had extended base address fields which hold bits 39:32 of
translated address. These fields are IMPDEF in ARMv6 and ARMv7 without
LPAE support.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
v3
According to ARM Cortex-A57 TRM, REVIDR reset value should be zero. So
let REVIDR reset value be specified by CPU model and fix it for
Cortex-A57.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu64.c | 1 +
target-arm/helper.c | 2 +-
3 files
On 01.06.2015 20:02, Peter Maydell wrote:
On 28 May 2015 at 12:00, Sergey Fedorov serge.f...@gmail.com wrote:
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5d0f011..fc3f192 100644
--- a/target-arm/helper.c
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5d0f011..fc3f192 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5333,6 +5333,8 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t
address, int
On 13.05.2015 14:05, Edgar E. Iglesias wrote:
On Wed, May 13, 2015 at 10:52:55AM +0300, Sergey Fedorov wrote:
On 13.05.2015 09:52, Edgar E. Iglesias wrote:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/helper.c
On 13.05.2015 09:52, Edgar E. Iglesias wrote:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/helper.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index
On 22.04.2015 10:09, Greg Bellows wrote:
Add a utility function for choosing the correct TTBR system register based on
the specified MMU index. Add use of function on physical address lookup.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/helper.c | 24
On 21.04.2015 06:49, Peter Maydell wrote:
On 17 March 2015 at 16:23, Peter Maydell peter.mayd...@linaro.org wrote:
On 17 March 2015 at 15:33, Sergey Fedorov serge.f...@gmail.com wrote:
Rename the field holding CPACR_EL1 system register state in AArch64
naming style.
Signed-off-by: Sergey
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
target-arm/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 986f04c..327b1e5 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -524,9 +524,10 @@ static void
On 27.03.2015 12:10, Greg Bellows wrote:
Add a utility function for choosing the correct TTBR system register based on
the specified MMU index. Add use of function on physical address lookup.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/helper.c | 44
On 27.03.2015 12:10, Greg Bellows wrote:
Add a utility function for choosing the correct TTBR system register based on
the specified MMU index. Add use of function on physical address lookup.
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/helper.c | 44
On 25.03.2015 04:06, Peter Maydell wrote:
On 25 March 2015 at 01:43, Sergey Fedorov serge.f...@gmail.com wrote:
On 24.03.2015 18:30, Sergey Fedorov wrote:
So if I understand you correctly, it would be suitable to implement a
model like Juno ARM Development Platform in order to get AArch64 VE
On 23.03.2015 04:29, Merten Sach wrote:
On 21/03/15 04:16, Sergey Fedorov wrote:
Hi!
I am currently working on AArch64 EL2 support. There is a plan to submit
the changes to the community. Merten, IIUYC, you are going to support
only AArch32 EL2?
Best regards,
Sergey
Hi
Yes, my
Require secondary CPU release address to be specified explicitly in each
daughterboard info structure.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
hw/arm/vexpress.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index
This default secondary loader is used to bring up secondary CPUs using
spin table boot method.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
hw/arm/boot.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index
itself.
The changes were tested by running a Linux system in SMP mode using
'arch/arm64/boot/dts/rtsm_ve-aemv8a.dts' from Linux kernel source code for
generating device tree blob.
Sergey Fedorov (3):
hw/arm/boot: add secondary loader for AArch64
hw/arm/vexpress: introduce VEDBoardInfo
This patch allows to boot AA64 linux kernel in SMP mode with DTB
generated from 'arch/arm64/boot/dts/rtsm_ve-aemv8a.dts' of Linux kernel
source code.
CPU and GIC creation parts are adaptation of code from hw/arm/virt.c.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
hw/arm/vexpress.c
On 24.03.2015 17:13, Peter Maydell wrote:
On 24 March 2015 at 23:55, Sergey Fedorov serge.f...@gmail.com wrote:
These patches add support for ARM Fixed Virtual Platform Versatile Express
board. ARM VFP VE is similar to hardware Versatile Express boards. So these
changes rely largely
On 24.03.2015 17:23, Peter Maydell wrote:
On 25 March 2015 at 00:18, Sergey Fedorov serge.f...@gmail.com wrote:
This model uses spin table boot method.
Yes, I noticed, that's a strong reason why I don't want to
add it if we can avoid it :-)
Why not? :-)
So it enables SMP on AArch64 in TCG
On 24.03.2015 17:48, Peter Maydell wrote:
On 25 March 2015 at 00:31, Sergey Fedorov serge.f...@gmail.com wrote:
On 24.03.2015 17:23, Peter Maydell wrote:
On 25 March 2015 at 00:18, Sergey Fedorov serge.f...@gmail.com wrote:
This model uses spin table boot method.
Yes, I noticed, that's
On 24.03.2015 18:30, Sergey Fedorov wrote:
On 24.03.2015 17:48, Peter Maydell wrote:
On 25 March 2015 at 00:31, Sergey Fedorov serge.f...@gmail.com wrote:
On 24.03.2015 17:23, Peter Maydell wrote:
On 25 March 2015 at 00:18, Sergey Fedorov serge.f...@gmail.com wrote:
This model uses spin
On 20.03.2015 21:49, Edgar E. Iglesias wrote:
Hi all,
Sergey, that's good to hear!
Peter, Yes I have quite a bit of patch material but unfortunately a lot of
it is not in a state for upstreaming. I know I've promised to clean
it up and submit more but I have not been able to find time for
On 20.03.2015 20:44, Peter Maydell wrote:
On 20 March 2015 at 17:25, Merten Sach ms...@mailbox.tu-berlin.de wrote:
I'm interested in participating in this years edition of Google Summer of
Code.
Initially I wanted to propose the implementation of ARMv7
virtualization extensions. I know this
Rename the field holding CPACR_EL1 system register state in AArch64
naming style.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
hw/arm/pxa2xx.c | 2 +-
target-arm/cpu.h| 4 ++--
target-arm/helper.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/arm
On 23.01.2015 19:17, Greg Bellows wrote:
These patches add extended EL support for ARMv8. Specifically the following
changes were made:
- Fix issue in RVBAR_EL1 CP register definition
- Add missing RVBAR_ELx CP register definitions
- Add missing SP_ELx CP register definitions
- Add reset
On 20.01.2015 01:30, Greg Bellows wrote:
Added support for running an AArch32 guest on a AArch64 KVM host. Support has
only been added to the QEMU machvirt machine. The addition of CPU properties
specifiable from the command line were added to allow disablement of AArch64
execution state
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
device_tree.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/device_tree.c b/device_tree.c
index df9eed9..4cb1cd5 100644
--- a/device_tree.c
+++ b/device_tree.c
@@ -324,6 +324,7 @@ int
Hi!
I am wondering is there any case when timer list lock could be under
contention?
Thanks,
Serge
() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Signed-off-by: Greg Bellows greg.bell...@linaro.org
---
target-arm/cpu.h | 38 ++
1 file changed, 38
On 06.10.2014 09:13, Peter Maydell wrote:
On 30 September 2014 22:49, Greg Bellows greg.bell...@linaro.org wrote:
From: Sergey Fedorov s.fedo...@samsung.com
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2
On 30.09.2014 14:49, Greg Bellows wrote:
From: Fabian Aggeler aggel...@ethz.ch
Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly infered from arm_
current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3.
arm_current_pl()
On 22.08.2014 14:29, Fabian Aggeler wrote:
ICDDCR/GICD_CTLR is banked in GICv1 implementations with Security
Extensions or in GICv2 in independent from Security Extensions.
This makes it possible to enable forwarding of interrupts from
Distributor to the CPU interfaces for Group0 and Group1.
On 22.08.2014 14:29, Fabian Aggeler wrote:
Preparing for FIQ lines from GIC to CPUs, which is needed for GIC
Security Extensions.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c| 3 +++
include/hw/intc/arm_gic_common.h | 1 +
2 files changed, 4
On 22.08.2014 14:29, Fabian Aggeler wrote:
The existing implementation does not support Security Extensions mentioned
in the GICv1 and GICv2 architecture specification. Security Extensions are
not available on all GICs. This property makes it possible to enable Security
Extensions.
It also
Ping.
On 13.08.2014 20:31, Sergey Fedorov wrote:
Take IRQ target mask into account when determining the highest priority
pending interrupt.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
hw/intc/arm_gic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw
On 25.08.2014 13:39, Aggeler Fabian wrote:
On 25 Aug 2014, at 11:20, Sergey Fedorov serge.f...@gmail.com wrote:
On 22.08.2014 14:29, Fabian Aggeler wrote:
The existing implementation does not support Security Extensions mentioned
in the GICv1 and GICv2 architecture specification. Security
Take IRQ target mask into account when determining the highest priority
pending interrupt.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
hw/intc/arm_gic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1532ef9..a5ad7b9
Hi,
Maybe you are trying to write into read-only, device MMIO or unassigned
address? You can launch qemu with '-S' and then try 'info mtree' qemu
monitor command to see the memory mapping.
// Sergey
On 24.06.2014 11:20, Shubham Gupta wrote:
Hello
I am attempting to write into the guest
On 24.06.2014 20:06, Michael Tokarev wrote:
19.06.2014 17:15, Sergey Fedorov wrote:
The only use for GPROF_CFLAGS is in main makefile, but this variable put
only to taget config file which is not included to the main makefile.
Lets put gprof config variables to host config file.
I'm not sure
The only use for GPROF_CFLAGS is in main makefile, but this variable put
only to taget config file which is not included to the main makefile.
Lets put gprof config variables to host config file.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
configure | 6 +-
1 file changed, 5
On 17.06.2014 13:15, Edgar E. Iglesias wrote:
Hi, I think the patch looks OK but I'm unsure if it brings any benefits
unless we add separate TLBs for S and NS.
I noticed that TTBR0 gets banked in the series, but are changes to
SCR.NS flushing the TLBs? I might have missed that from the
I am missing your point. In patch 6 arm_current_pl calls
arm_is_secure. Can you elaborate?
Greg
On 11 June 2014 07:17, Sergey Fedorov serge.f...@gmail.com
mailto:serge.f...@gmail.com wrote:
On 11.06.2014 03:54, Fabian Aggeler wrote:
arm_is_secure() function allows to determine
identical. In the case of
arm_current_pl, it returns the PL regardless of the SCR.NS bit. In
the case of arm_is_secure, the secure state takes into consideration
both the PL and the SCR.NS setting.
On 12 June 2014 12:26, Sergey Fedorov serge.f...@gmail.com
mailto:serge.f...@gmail.com wrote
Hi Fabian,
11.06.2014 03:55, Fabian Aggeler wrote:
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 14 +++---
target-arm/helper.c
On 11.06.2014 03:54, Fabian Aggeler wrote:
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed
On 09.06.2014 21:36, Alex Bligh wrote:
On 9 Jun 2014, at 17:42, Sergey Fedorov wrote:
If there is no deadline across all timerlists attached to the clock
then qemu_clock_deadline_ns_all() returns -1. Cast it to unsinged so
MIN() do not treat it as minimum.
Signed-off-by: Sergey Fedorov
Use dedicated qemu_soonest_timeout() instead of MIN().
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
cpus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cpus.c b/cpus.c
index dd7ac13..af06dc0 100644
--- a/cpus.c
+++ b/cpus.c
@@ -347,7 +347,7 @@ void
If there is no deadline across all timerlists attached to the clock
then qemu_clock_deadline_ns_all() returns -1. Cast it to unsinged so
MIN() do not treat it as minimum.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
cpus.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On 05.06.2014 12:02, Alex Bennée wrote:
Chaos Shu writes:
Hi
I'm running SPEC CPU2006 on three kinds of situation, native aarch64 binary
and emulator x86_64 system running SPEC CPU2006 and linux user mode level
running x86_64 SPEC CPU2006 binary.
To find where the performance lose,
On 05.06.2014 17:07, Peter Maydell wrote:
Probably worth making sure you also test workloads that do different
things in multiple processes (to catch performance issues from over
frequent TB/TLB flushes, and so on).
Maybe make -jN?
Thanks,
Sergey
On 29.05.2014 13:04, Peter Maydell wrote:
No, we don't in general have any benchmarking of TCG
codegen. I think if we did do benchmarking we'd be interested
in performance benchmarking -- code expansion ratio doesn't
seem like a very interesting thing to measure to me.
Hi,
I have a plan to
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
---
qtest.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qtest.c b/qtest.c
index 2aba20d..87ccd62 100644
--- a/qtest.c
+++ b/qtest.c
@@ -148,7 +148,7 @@ static int hex2nib(char ch)
} else if (ch = 'a' ch = 'f
/load.
Regards,
Sergey
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 121
+
target-arm/helper.c| 64 --
target-arm/translate.c
/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm/Booting#n183
Christopher
AFAIK, in real hardware this switch to non-secure state is actually done
by bootloader. Why don't implement this in Qemu bootloader stub so far?
Regards,
Sergey Fedorov.
access h/w or registers which aren't accessible
from NS. I guess we need to implement it and then see if any of our
guest images stop working...
Then maybe we can extend arm_boot_info structure to deal with this.
Regards,
Sergey Fedorov.
On 15.05.2014 23:10, Aggeler Fabian wrote:
On 15 May 2014, at 20:42, Sergey Fedorov serge.f...@gmail.com wrote:
13.05.2014 20:15, Fabian Aggeler wrote:
@@ -771,6 +862,14 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t
cpregid)
* IO indicates that this register does I/O and therefore its
On 15.05.2014 13:28, Aggeler Fabian wrote:
Hi Greg
Thanks for your comments. I still have to work through them. I am using
OpenVirtualization in secure world, which then switches to a Linux kernel in
non-secure world to test the patches. What about you?
Best,
Fabian
Hi, Fabian, are
On 15.05.2014 18:44, Fabian Aggeler wrote:
Please, look at disas_vfp_insn() and disas_neon_*_insn() functions.
Looks like them should be updated. In that case do not forget to adjust
arm_cpu_reset() so user emulation would be able to execute VFP/NEON
instructions.
See ARM ARM v7-AR B1.11.1
13.05.2014 20:15, Fabian Aggeler wrote:
@@ -771,6 +862,14 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
* IO indicates that this register does I/O and therefore its accesses
* need to be surrounded by gen_io_start()/gen_io_end(). In particular,
* registers which implement
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