On 15.05.2014 13:28, Aggeler Fabian wrote:
> Hi Greg
>
> Thanks for your comments. I still have to work through them. I am using
> OpenVirtualization in secure world, which then switches to a Linux kernel in
> non-secure world to test the patches. What about you?
>
> Best,
> Fabian
Hi, Fabian, a
cro anymore as MMU index in translation
> code. Use new MEM_INDEX() and MEM_INDEX_USER() macros instead.
>
> Signed-off-by: Sergey Fedorov
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/cpu.h | 42 +++-
> target-arm/helper.c| 2 +-
> target-a
On 13.05.2014 20:15, Fabian Aggeler wrote:
> From: Sergey Fedorov
>
> CPACR register allows to control access rights to coprocessor 0-13
> interfaces. Bits corresponding to unimplemented coprocessors should be
> RAZ/WI. QEMU implements only VFP coprocessor on ARMv6+ targets. So onl
On 13.05.2014 20:15, Fabian Aggeler wrote:
> arm_is_secure() function allows to determine CPU security state
> if the CPU implements Security Extensions.
>
> Signed-off-by: Sergey Fedorov
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/cpu.h | 15 +++
On 13.05.2014 20:15, Fabian Aggeler wrote:
> From: Svetlana Fedoseeva
>
> Signed-off-by: Svetlana Fedoseeva
> Signed-off-by: Sergey Fedorov
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/helper.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git
Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6ebd7dc
A single cast cache is used for both an object casting and a class
casting. In case of interface presence a class cast result may be not
the same pointer as opposite to an object casting. So do not cache cast
results for an object casting in a presence of interfaces.
Signed-off-by: Sergey
A single cast cache is used for both an object casting and a class
casting. In case of interface presence a class cast result may be not
the same pointer as opposite to an object casting. So do not cache cast
results for an object casting in a presence of interfaces.
Signed-off-by: Sergey
descriptor format and, therefore, TTBCR format.
Signed-off-by: Sergey Fedorov
---
target-arm/helper.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3445813..8b1ddce 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
From: Svetlana Fedoseeva
Define TrustZone CPU feature. Set that feature for relevant CPUs.
Signed-off-by: Svetlana Fedoseeva
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.c |4
target-arm/cpu.h |1 +
2 files changed, 5 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm
Define appropriate coprocessor registers with banked type. The register
state fields are defined with BANKED_CP_REG() macro.
Banked coprocessor registers with a special behaviour is adjusted to
correctly use its active or banked non-secure state.
Signed-off-by: Sergey Fedorov
---
target-arm
SMC instruction is implemented similar to SVC instruction. When
executing SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h |1 +
target-arm/helper.c| 11 +++
target-arm/translate.c | 37
MVBAR register provides an exception vector base address for exceptions
taking to CPU monitor mode.
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h|1 +
target-arm/helper.c | 16 +++-
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/target-arm/cpu.h b
Signed-off-by: Sergey Fedorov
---
target-arm/helper.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d4407cf..e406ec9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2018,12 +2018,13 @@ static int
SCR.{IRQ/FIQ} bits allows to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
---
target-arm/helper.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/target-arm/helper.c b
Define a new ARM CP register info list for TrustZone Security Extension
feature. Register that list only for ARM cores with TrustZone support.
SCR and VBAR are security extension registers. So move them into
TrustZone feature register list.
Signed-off-by: Sergey Fedorov
---
target-arm/helper.c
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h|1 +
target-arm/helper.c |3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5aeb630..ffc1b21 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -150,6 +150,7 @@ typedef struct
arm_is_secure() helper allows to determine CPU security state.
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 94d8bd1..a00c86f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
. In non-secure state an active
register state field is always used.
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h | 14 ++-
target-arm/translate.c | 60
2 files changed, 69 insertions(+), 5 deletions(-)
diff --git a/target
state.
Translation table base masks are updated on register switch instead
of TTBCR write.
Signed-off-by: Sergey Fedorov
---
target-arm/helper.c | 77 ++-
1 file changed, 76 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target
NSACR allows to control non-secure access to coprocessor interfaces 0-13
and CPACR bits.
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h |1 +
target-arm/helper.c| 21 +
target-arm/translate.c |3 +++
3 files changed, 25 insertions(+)
diff --git a
change. Do not use IS_USER() macro anymore as MMU index in translation
code. Use new MEM_INDEX() and MEM_INDEX_USER() macros instead.
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h | 14 ++-
target-arm/helper.c|2 +-
target-arm/translate.c | 247
CPACR register allows to control access rights to coprocessor 0-13
interfaces. Bits corresponding to unimplemented coprocessors should be
RAZ/WI. QEMU implement only VFP coprocessor on ARMv6+ targets. So only
cp10 & cp11 bits is writable.
Signed-off-by: Sergey Fedorov
---
target-arm/help
Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov
---
target-arm/helper.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9442e08..e1e9762 100644
--- a/target-arm
SCR register is accessible in PL3 (secure privileged) mode only. Fix SRC
access rights since arm_current_pl() can return PL3 now.
Signed-off-by: Sergey Fedorov
---
target-arm/helper.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm
From: Svetlana Fedoseeva
Define CPU monitor mode. Adjust core registers banking. Adjust CPU VM
state info. Provide CPU mode name for monitor mode.
Signed-off-by: Svetlana Fedoseeva
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h |7 ---
target-arm/helper.c|3
Make arm_current_pl() to return PL3 in secure privileged mode.
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a00c86f..1b03450 100644
--- a/target-arm/cpu.h
+++ b/target
TTBCR has additional fields PD0 and PD1 when using Short-descriptor
translation table format on a CPU with TrustZone feature support.
Signed-off-by: Sergey Fedorov
---
target-arm/helper.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm
secure state.
Signed-off-by: Sergey Fedorov
---
target-arm/cpu.h |7 +++
target-arm/translate.c |3 +++
target-arm/translate.h |1 +
3 files changed, 11 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1b03450..f47dbdf 100644
--- a/target-arm/cpu.h
+++ b
uest for comments for the proof of concept.
Sergey Fedorov (18):
target-arm: move SCR & VBAR into TrustZone register list
target-arm: adjust TTBCR for TrustZone feature
target-arm: add arm_is_secure() helper
target-arm: reject switching to monitor mode from non-secure state
target-arm
From: Svetlana Fedoseeva
Signed-off-by: Svetlana Fedoseeva
Signed-off-by: Sergey Fedorov
---
target-arm/helper.c |4
1 file changed, 4 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6642e53..d7922ad 100644
--- a/target-arm/helper.c
+++ b/target-arm
Do not return after net_hub_flush(). Always flush callee network client
incoming queue.
Signed-off-by: Sergey Fedorov
---
net/net.c |1 -
1 file changed, 1 deletion(-)
diff --git a/net/net.c b/net/net.c
index c330c9a..aeb479b 100644
--- a/net/net.c
+++ b/net/net.c
@@ -442,7 +442,6 @@ void
queue will be really flushed and
no packets will be stalled in the sender network queue.
Signed-off-by: Sergey Fedorov
---
net/hub.c | 20
1 file changed, 20 deletions(-)
diff --git a/net/hub.c b/net/hub.c
index df32074..552e970 100644
--- a/net/hub.c
+++ b/net/hub.c
801 - 833 of 833 matches
Mail list logo
