Re: [PATCH] target/riscv: deprecate capital 'Z' CPU properties

That's great! I submitted a patch set to deal with the exact problem: But this one is simpler than mine (and also fits to the latest QEMU). I support this

Re: [PULL 3/5] contrib/gitdm: add Tsukasa as an individual contributor

On 2023/03/11 0:57, Alex Bennée wrote: > I wasn't sure if you want to be added as an individual contributor or > an academic so please confirm. Individual. > > Signed-off-by: Alex Bennée > Acked-by: Tsukasa OI > Message-Id: <20221219121914.851488-7-alex.ben...@lin

Re: [PATCH 06/11] contrib/gitdm: add Tsukasa as an individual contributor

19, Alex Bennée wrote: > I wasn't sure if you want to be added as an individual contributor or > an academic so please confirm. > > Signed-off-by: Alex Bennée > Cc: Tsukasa OI > --- > contrib/gitdm/group-map-individuals | 1 + > 1 file changed, 1 insertion(+) > >

Re: [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings

On 2022/08/06 0:54, Conor Dooley wrote: > From: Palmer Dabbelt > > The ISA strings we're providing from QEMU aren't actually legal RISC-V > ISA strings, as both S and U cannot exist as single-letter extensions > and must instead be multi-letter strings. We're still using the ISA > strings inside

[PATCH v3 2/3] target/riscv: Make CPU property names lowercase

ility, but with deprecated status). Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 27 --- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3f21563f2d..83262586e4 100644 --- a/target/riscv/cpu.c +++ b/target/r

[PATCH v3 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases)

names. See v1 for background. [Changes: PATCH v2 -> PATCH v3] - Rebased to newer master - Fixed a typo - Clarified intent of PATCH 1/3 Tsukasa OI (3): target/riscv: Reorganize riscv_cpu_properties target/riscv: Make CPU property names lowercase target/riscv: Deprecate capit

[PATCH v3 3/3] target/riscv: Deprecate capitalized property names

This commit adds a deprecation note of capitalized property names of RISC-V CPU to documentation. Signed-off-by: Tsukasa OI --- docs/about/deprecated.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index a92ae0f162

[PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties

Because many developers introduced new properties in various ways, the entire riscv_cpu_properties block is getting too complex. This commit reorganizes riscv_cpu_properties for clarity on future. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 64

Re: [PATCH v2 2/3] target/riscv: Make CPU property names lowercase

On 2022/05/25 21:10, Víctor Colombo wrote: > On 25/05/2022 06:54, Tsukasa OI wrote: >> Many CPU properties for RISC-V are in lowercase except those with >> "capitalized" (or CamelCase) names: >> >> -   Counters >> -   Zifencei >> -   Zicsr >

[PATCH v2.1 2/3] target/riscv: Make CPU property names lowercase

ility, but with deprecated status). Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 27 --- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3f21563f2d..83262586e4 100644 --- a/target/riscv/cpu.c +++ b/target/r

[PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties

This commit reorganizes riscv_cpu_properties for clarity. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 64 +++--- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a91253d4bd..3f21563f2d

[PATCH v2 2/3] target/riscv: Make CPU property names lowercase

, but with deprecated status). Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 27 --- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3f21563f2d..83262586e4 100644 --- a/target/riscv/cpu.c +++ b/target/r

[PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases)

uot;System emulator command line arguments" or - A new section under "Device options" (THIS PATCH) 2. Is it okay to use the word "7.1" (an unreleased version number)? Tsukasa OI (3): target/riscv: Reorganize riscv_cpu_properties target/riscv: Make CPU property names low

[PATCH v2 3/3] target/riscv: Deprecate capitalized property names

This commit adds a deprecation note of capitalized property names of RISC-V CPU to documentation. Signed-off-by: Tsukasa OI --- docs/about/deprecated.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index a92ae0f162

Re: [PATCH v2 2/5] target/riscv: Disable "G" by default

On 2022/05/17 3:04, Víctor Colombo wrote: > On 14/05/2022 23:56, Tsukasa OI wrote: >> Because "G" virtual extension expands to "IMAFD", we cannot separately >> disable extensions like "F" or "D" without disabling "G".  Because a

Re: [PATCH v2 4/5] target/riscv: FP extension requirements

On 2022/05/15 23:37, Weiwei Li wrote: > > 在 2022/5/15 上午10:56, Tsukasa OI 写道: >> QEMU allowed inconsistent configurations that made floating point >> arithmetic effectively unusable. >> >> This commit adds certain checks for consistent FP arithmetic: >>

[PATCH v2 4/5] target/riscv: FP extension requirements

by default (and an error will not occur unless we manually disable one or more of prerequisites), this commit just enforces the user to give consistent combinations. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a

[PATCH v2 3/5] target/riscv: Change "G" expansion

On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei". Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to be (virtually) enabled as well, it should be safe to change its expansion. Signed-off-by: Tsuka

[PATCH v2 2/5] target/riscv: Disable "G" by default

Because "G" virtual extension expands to "IMAFD", we cannot separately disable extensions like "F" or "D" without disabling "G". Because all "IMAFD" are enabled by default, it's harmless to disable "G" by default. S

[PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks

We should separate "check" and "configure" steps as possible. This commit separates both steps except vector/Zfinx-related checks. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 31 --- 1 file changed, 16 insertions(+), 15 deletions(-) diff

[PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion

Because ext_? members are boolean variables, operator `&&' should be used instead of `&'. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..0

[PATCH v2 0/5] target/riscv: Enhanced ISA extension checks

test were in the wrong place PATCH 5: Zfinx/F exclusivity test was completely wrong I meant Zfinx&&F but when finalizing my patchset, I somehow changed this place to Zfinx&&!F. Tsukasa OI (5): target/riscv: Fix coding style on "G" expansion target/ri

[PATCH v2 2/2] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

generous on sifive_e/u and opentitan machines. It now just prints error message and quits (without coredumps and aborts). This is separate from spike/virt because it involves different type (TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines. Signed-off-by: Tsukasa OI --- hw/riscv

[PATCH v2 1/2] hw/riscv: Make CPU config error handling generous (virt/spike)

generous on virt/spike machines. It now just prints error message and quits (without coredumps and aborts). Signed-off-by: Tsukasa OI --- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index

[PATCH v2 0/2] hw/riscv: Make CPU config error handling generous

c.f. <https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00229.html> This patchset is functionally equivalent to v1 but fixes commit titles. Tsukasa OI (2): hw/riscv: Make CPU config error handling generous (virt/spike) hw/riscv: Make CPU config error handling generous (si

Re: [RFC PATCH v4 1/4] target/riscv: Add smstateen support

On 2022/05/13 17:51, Mayuresh Chitale wrote: > Smstateen extension specifies a mechanism to close > the potential covert channels that could cause security issues. > > This patch adds the CSRs defined in the specification and > the corresponding predicates and read/write functions. > > Signed-off

[PATCH 2/2] target/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

generous on sifive_e/u and opentitan machines. It now just prints error message and quits (without coredumps and aborts). This is separate from spike/virt because it involves different type (TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines. Signed-off-by: Tsukasa OI --- hw/riscv

[PATCH 0/2] hw/riscv: Make CPU config error handling generous

cicle-kit (RV64 only) ...but since CPU realization on those machine currently never fails (because they require fixed CPU), I didn't touch those (may be a TODO). Tsukasa OI (2): target/riscv: Make CPU config error handling generous (virt/spike) target/riscv: Make CPU config error ha

[PATCH 1/2] target/riscv: Make CPU config error handling generous (virt/spike)

generous on virt/spike machines. It now just prints error message and quits (without coredumps and aborts). Signed-off-by: Tsukasa OI --- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index

[RFC PATCH 1/1] target/riscv: Make property names lowercase

d names as aliases for compatibility. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..16227a1ac5 100644 --- a/target/riscv/cpu.c +++ b/target/r

[RFC PATCH 0/1] target/riscv: Make property names lowercase and add capitalized aliases

y share three arguments but on alias (the second one),: - it uses DEFINE_PROP on alias to disable setting default value and - it defines property type (that is generally set by DEFINE_PROP_BOOL but must be set manually because the alias uses DEFINE_PROP). DEFINE_PROP_BOOL("

[PATCH 1/5] target/riscv: Fix "G" extension expansion typing

Because ext_? members are in bool type, operator `&&' should be used instead of `&'. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..00bf26ec

[PATCH 3/5] target/riscv: Change "G" expansion

On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei". Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to be (virtually) enabled as well, it should be safe to change its expansion. Signed-off-by: Tsuka

[PATCH 0/5] target/riscv: Enhanced ISA extension checks

to RISC-V CPU realization process). I think we generally use generic "rv32" or "rv64" on heavy customizing so I don't think this is not a big problem. Still, we could fix this later (e.g. by setting properties on CPU init function or by che

[PATCH 5/5] target/riscv: Move/refactor ISA extension checks

We should separate "check" and "configure" steps as possible. This commit separates both steps except vector/Zfinx-related checks. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/

[PATCH 4/5] target/riscv: FP extension requirements

by default (and an error will not occur unless we manually disable one or more of prerequisites), this commit just enforces the user to give consistent combinations. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a

[PATCH 2/5] target/riscv: Disable "G" by default

Because "G" virtual extension expands to "IMAFD", we cannot separately disable extensions like "F" or "D" without disabling "G". Because all "IMAFD" are enabled by default, it's harmless to disable "G" by default. S

[PATCH v2 2/2] target/riscv: Add short-isa-string option

pport caused a kernel panic. Operating Systems which short-isa-string might be helpful: 1. Linux (5.17 or earlier) 2. FreeBSD (at least 14.0-CURRENT) 3. OpenBSD (at least current development version) Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 5 - target/riscv/cpu.h | 2 ++ 2

[PATCH v2 1/2] target/riscv: Move Zhinx* extensions on ISA string

This commit moves ISA string conversion for Zhinx and Zhinxmin extensions. Because extension category ordering of "H" is going to be after "V", their ordering is going to be valid (on canonical order). Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 4 ++-- 1 file changed

[PATCH v2 0/2] target/riscv: ISA string conversion fix and enhancement

we have reasons to make extension ordering canonical as possible for toolchain compatibility (for now). Tsukasa OI (2): target/riscv: Move Zhinx* extensions on ISA string target/riscv: Add short-isa-string option target/riscv/cpu.c | 9 ++--- target/riscv/cpu.h | 2 ++ 2 f

Re: [PATCH 1/2] target/riscv: Tentatively remove Zhinx* from ISA extension string

On 2022/04/28 11:39, Weiwei Li wrote: > > 在 2022/4/28 上午7:58, Alistair Francis 写道: >> On Sun, Apr 24, 2022 at 3:22 PM Tsukasa OI >> wrote: >>> This commit disables ISA string conversion for Zhinx and Zhinxmin >>> extensions for now.  Because exten

Re: [PATCH 2/2] target/riscv: Add short-isa-string option

On 2022/05/09 18:51, Alistair Francis wrote: > On Sun, Apr 24, 2022 at 7:22 AM Tsukasa OI > wrote: >> >> Because some operating systems don't correctly parse long ISA extension >> string, this commit adds short-isa-string boolean option to disable >> gener

[PATCH 2/2] target/riscv: Add short-isa-string option

D (at least 14.0-CURRENT) 3. OpenBSD (at least current development version) Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 5 - target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c765f7ff00..9718cd0e7e 1

[PATCH 0/2] target/riscv: ISA string conversion fix and enhancement

Without "short-isa-string=on", QEMU generates DeviceTree with following ISA extension string: rv64imafdch_zba_zbb_zbc_zbs_svinval_svnapot With it, QEMU generates following ISA extension string: rv64imafdch Tsukasa OI (2): target/riscv: Tentatively remove Zhi

[PATCH 1/2] target/riscv: Tentatively remove Zhinx* from ISA extension string

This commit disables ISA string conversion for Zhinx and Zhinxmin extensions for now. Because extension category ordering of "H" is not ratified, their ordering is likely invalid. Once "H"-extension ordering is determined, we can add Zhinx* again. Signed-off-by: Tsukasa O

Re: [PATCH v2 1/1] target/riscv: misa to ISA string conversion fix

On 2022/03/30 1:29, Frédéric Pétrot wrote: > Hello, > > Le 28/03/2022 à 15:11, Tsukasa OI a écrit : >> Some bits in RISC-V `misa' CSR should not be reflected in the ISA >> string.  For instance, `S' and `U' (represents existence of supervisor >> and user

[PATCH v2 0/1] target/riscv: misa to ISA string conversion fix

;L": Dropped. - "N": Dropped. - "T": Dropped. Signed-off-by: Tsukasa OI Tsukasa OI (1): target/riscv: misa to ISA string conversion fix target/riscv/cpu.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) base-commit: 3d31fe4d662f13c70eb7e87f29513623ccd76322 -- 2.32.0

Re: [PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix

Hi Alistair, On 2022/03/28 8:29, Alistair Francis wrote: > On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI > wrote: >> >> Some bits in RISC-V `misa' CSR should not be reflected in the ISA >> string. For instance, `S' and `U' (represents existence of superv

Re: [PATCH (PING) 0/1] target/riscv: misa to ISA string conversion fix

On 2022/03/28 8:29, Alistair Francis wrote: > On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI > wrote: >> >> [This is the same patch as previous ones] > > Hello, > > Thanks for the patch! > >> <https://lists.nongnu.org/archive/html/qemu-riscv/2022-02/msg0

[PATCH v2 1/1] target/riscv: misa to ISA string conversion fix

single-letter extension (misa.K is reserved). - "L": Dropped. - "N": Dropped. - "T": Dropped. It also clarifies that the variable `riscv_single_letter_exts' is a single-letter extension order list. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 10 ++

[PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix

commit restricts which bits to copy from `misa' CSR to ISA string with another fix: `C' extension should be preceded by `L' extension. It also clarifies that RISC-V extension order string is actually a single-letter extension order list. Signed-off-by: Tsukasa OI --- target/r

[PATCH (PING) 0/1] target/riscv: misa to ISA string conversion fix

hope this is applied before the QEMU 7.0 release. Signed-off-by: Tsukasa OI Reviewed-by: Frank Chang S and U are misa bits but not extensions (instead, they are supported privilege modes). Thus, they should not be copied to the ISA string. I am truly surprised that this patchset is the THIRD at