> On Jul 24, 2020, at 1:46 PM, Lijun Pan wrote:
>
>
>
>> On Jul 24, 2020, at 1:00 PM, Richard Henderson > <mailto:richard.hender...@linaro.org>> wrote:
>>
>> On 7/23/20 9:58 PM, Lijun Pan wrote:
>>> vmsumudm (Power ISA 3.0) - Vector
> On Jul 24, 2020, at 1:00 PM, Richard Henderson
> wrote:
>
> On 7/23/20 9:58 PM, Lijun Pan wrote:
>> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
>> VA-form.
>> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan
---
v4/v5: no change
Reviewed-by: Richard Henderson
v3: inline the helper_vmulh{su}w multiply directly instead of using macro
v2: fix coding style
use Power ISA 3.1 flag
target
Group vmuluwm and vmulld. Make vmulld-specific
changes since it belongs to new ISA 3.1.
Signed-off-by: Lijun Pan
---
v5: no change
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
tcg/ppc/tcg-target.h | 2
Doubleword
Signed-off-by: Lijun Pan
---
v5: no change
v4: add a comment on undefined result of divide operation.
fix if(){} coding style issue, remove blank line.
v3: add missing divided-by-zero, divided-by-(-1) handling
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan
---
v4/v5: no change
Reviewed-by: Richard Henderson
v3: simplify helper_vmulh{su}d
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h
vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
VA-form.
vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
Doubleword VA-form.
Signed-off-by: Lijun Pan
---
v5: update instruction flag for vmsumcud.
integrate into this isa3.1 patch serie
Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
Signed-off-by: Lijun Pan
---
v5: match the definition with that in linux's
arch/powerpc/include/uapi/asm/cputable.h
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
, and 9/11 of v4 was accepted by Lauren Vivier.
This v5 version updates PPC_FEATURE2_ARCH_3_10 definition in 6/11 of v4,
rebases 7/11 8/11 10/11 11/11 of v4, and integrates vmsumudm/vmsumcud
patch.
Lijun Pan (6):
Update PowerPC AT_HWCAP2 definition
target/ppc: add vmulld to INDEX_op_mul_vec
> On Jul 13, 2020, at 6:47 PM, David Gibson wrote:
>
> On Mon, Jul 13, 2020 at 02:20:20PM -0500, Lijun Pan wrote:
>>
>>
>>> On Jul 13, 2020, at 12:14 AM, David Gibson
>>> wrote:
>>>
>>> On Wed, Jul 01, 2020 at 06:43:41PM -0500,
> On Jul 1, 2020, at 6:43 PM, Lijun Pan wrote:
>
> Group vmuluwm and vmulld. Make vmulld-specific
> changes since it belongs to new ISA 3.1.
>
> Signed-off-by: Lijun Pan
> ---
> v4: add missing changes, and split to 5/11, 6/11, 7/11
> v3: use tcg_gen_gvec_m
> On Jul 1, 2020, at 6:47 PM, Lijun Pan wrote:
>
> vdivsw: Vector Divide Signed Word
> vdivuw: Vector Divide Unsigned Word
> vdivsd: Vector Divide Signed Doubleword
> vdivud: Vector Divide Unsigned Doubleword
> vmodsw: Vector Modulo Signed Word
> vmoduw: Vector Modul
> On Jul 1, 2020, at 6:47 PM, Lijun Pan wrote:
>
> vmulhsd: Vector Multiply High Signed Doubleword
> vmulhud: Vector Multiply High Unsigned Doubleword
>
> Signed-off-by: Lijun Pan
> ---
> Reviewed-by: Richard Henderson
> v3: simplify helper_vmulh{su}d
> v2: f
> On Jul 1, 2020, at 6:43 PM, Lijun Pan wrote:
>
> vmulhsw: Vector Multiply High Signed Word
> vmulhuw: Vector Multiply High Unsigned Word
>
> Signed-off-by: Lijun Pan
> ---
> Reviewed-by: Richard Henderson
> v3: inline the helper_vmulh{su}w multiply directly
> On Jul 6, 2020, at 2:53 AM, David Gibson wrote:
>
> On Mon, Jun 22, 2020 at 11:25:01PM -0500, Lijun Pan wrote:
>> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
>> VA-form.
>> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write C
> On Jul 13, 2020, at 12:14 AM, David Gibson
> wrote:
>
> On Wed, Jul 01, 2020 at 06:43:41PM -0500, Lijun Pan wrote:
>> Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
>>
>> Signed-off-by: Lijun Pan
>> ---
>> v4: add missing ch
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan
---
Reviewed-by: Richard Henderson
v3: simplify helper_vmulh{su}d
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 2 ++
target/ppc
Doubleword
Signed-off-by: Lijun Pan
---
v4: add a comment on undefined result of divide operation.
fix if(){} coding style issue, remove blank line.
v3: add missing divided-by-zero, divided-by-(-1) handling
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 8
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 4
2
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan
---
v4: make it compile on all targets
v3: fix the store issue in br[dwh]
simplify brw implementation
The prototypes of muls64/mulu64 in host-utils.h should match the
definitions in host-utils.c
Signed-off-by: Lijun Pan
---
Reviewed-by: Richard Henderson
no change since v1
include/qemu/host-utils.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/host
Convert the original implementation of vmuluwm to the more generic
tcg_gen_gvec_mul.
Signed-off-by: Lijun Pan
---
Reviewed-by: Richard Henderson
v3: newly introduced
target/ppc/helper.h | 1 -
target/ppc/int_helper.c | 13 -
target/ppc/translate/vmx
Group vmuluwm and vmulld. Make vmulld-specific
changes since it belongs to new ISA 3.1.
Signed-off-by: Lijun Pan
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
tcg/ppc/tcg-target.h | 2 ++
tcg/ppc/tcg
This patch series add several newly introduced 32/64-bit vector
instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in
this version. In v4 version, coding style issues are fixed, community
reviews/suggestions are taken into consideration.
Lijun Pan (11):
target/ppc: Introduce Power
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan
---
Reviewed-by: Richard Henderson
v3: inline the helper_vmulh{su}w multiply directly instead of using macro
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h
This patch enables the Power ISA 3.1 in QEMU.
Signed-off-by: Lijun Pan
---
v4: split to 01/11 and 02/11
v2: add Power ISA 3.1 flag
target/ppc/cpu.h| 2 +-
target/ppc/translate_init.inc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b
Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
Signed-off-by: Lijun Pan
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
include/elf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a
This flag will be used for Power10 instructions.
Signed-off-by: Lijun Pan
---
v4: split to 01/11 and 02/11
v2: add Power ISA 3.1 flag
target/ppc/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1988b436cb..a5e9c08dcc 100644
--- a/target/ppc
> On Jun 25, 2020, at 1:37 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> +#define VDIV_MOD_DO(name, op, element, sign, bit) \
>> +void helper_v##name(ppc_avr_t *r, pp
> On Jun 25, 2020, at 1:25 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> vmulld: Vector Multiply Low Doubleword.
>>
>> Signed-off-by: Lijun Pan
>> ---
>> v3: use tcg_gen_gvec_mul()
>>
>> target/ppc/tran
> On Jun 25, 2020, at 12:40 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> +/* POWER ISA 3.1
>> */
>> +PPC2_ISA310= 0x0010ULL,
>
&g
> On Jun 25, 2020, at 12:42 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> +static void gen_brh(DisasContext *ctx)
>> +{
>> +TCGv_i64 t0 = tcg_temp_new_i64();
>> +TCGv_i64 t1 = tcg_temp_new_i64();
&g
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan
---
v3: inline the helper_vmulh{su}w multiply directly instead of using macro
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 19
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan
---
v3: simplify helper_vmulh{su}d
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 16
target/ppc/translate/vmx
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan
---
v3: fix the store issue in br[dwh]
simplify brw implementation
add "if defined(TARGET_
Convert the original implementation of vmuluwm to the more generic
tcg_gen_gvec_mul.
Signed-off-by: Lijun Pan
---
v3: newly introduced.
target/ppc/helper.h | 1 -
target/ppc/int_helper.c | 13 -
target/ppc/translate/vmx-impl.inc.c | 2 +-
3 files
The prototypes of muls64/mulu64 in host-utils.h should match the
definitions in host-utils.c
Signed-off-by: Lijun Pan
---
include/qemu/host-utils.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 4cd170e6cd
Doubleword
Signed-off-by: Lijun Pan
---
v3: add missing divided-by-zero, divided-by-(-1) handling
target/ppc/helper.h | 8
target/ppc/int_helper.c | 26 ++
target/ppc/translate.c | 3 +++
target/ppc/translate/vmx-impl.inc.c
This patch series add several newly introduced 32/64-bit vector
instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in
this version. In v3 version, coding style issues are fixed, community
reviews/suggestions are taken into consideration.
Lijun Pan (8):
target/ppc: Introduce Power
This flag will be used for Power10 instructions.
Signed-off-by: Lijun Pan
---
target/ppc/cpu.h| 4 +++-
target/ppc/translate_init.inc.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1988b436cb..ebb5a0811a 100644
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan
---
v3: use tcg_gen_gvec_mul()
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 4
tcg/ppc/tcg-target.h| 2 ++
tcg/ppc/tcg-target.inc.c| 7 +--
4 files changed
vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
VA-form.
vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
Doubleword VA-form.
Signed-off-by: Lijun Pan
---
v3: implement vmsumudm/vmsumcud through int128 functions,
suggested by Ric
> On Jun 18, 2020, at 6:29 PM, Richard Henderson
> wrote:
>
> On 6/12/20 9:20 PM, Lijun Pan wrote:
>> +#define VMULH_DO(name, op, element, cast_orig, cast_temp) \
>> +void helper_vmulh##name(ppc_avr_t *r, pp
> On Jun 18, 2020, at 6:27 PM, Richard Henderson
> wrote:
>
> On 6/12/20 9:20 PM, Lijun Pan wrote:
>> vmulld: Vector Multiply Low Doubleword.
>>
>> Signed-off-by: Lijun Pan
>> ---
>> target/ppc/helper.h | 1 +
>> target/
> On Jun 18, 2020, at 6:19 PM, Richard Henderson
> wrote:
>
> On 6/12/20 9:20 PM, Lijun Pan wrote:
>> POWER ISA 3.1 introduces following byte-reverse instructions:
>> brd: Byte-Reverse Doubleword X-form
>> brw: Byte-Reverse Word X-form
>> brh: Byte-Rever
> On Jun 18, 2020, at 6:09 PM, Richard Henderson
> wrote:
>
> On 6/15/20 1:53 PM, Lijun Pan wrote:
>>>> +static inline void uint128_add(uint64_t ah, uint64_t al, uint64_t bh,
>>>> + uint64_t bl, uint64_t *rh, uint64_t *rl, uint64_t *ca)
>>
TEST SCRIPT END ===
It look like the errors generated below are not directly related to the code
changes I made.
Does anyone know why it still reports errors?
Thanks,
Lijun
>
> GEN docs/interop/qemu-qmp-ref.html
> GEN docs/interop/qemu-qmp-ref.txt
> GEN docs/in
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan
---
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 24
target
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan
---
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 14 ++
target/ppc/translate/vmx
This flag will be used for Power10 instructions.
Signed-off-by: Lijun Pan
---
v2: add Power ISA 3.1 flag
target/ppc/cpu.h| 4 +++-
target/ppc/translate_init.inc.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index
Doubleword
Signed-off-by: Lijun Pan
---
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 8
target/ppc/int_helper.c | 19 +++
target/ppc/translate.c | 3 +++
target/ppc/translate/vmx-impl.inc.c | 15
The prototypes of muls64/mulu64 in host-utils.h should match the
definitions in host-utils.c
Signed-off-by: Lijun Pan
---
v2: no change
include/qemu/host-utils.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan
---
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/translate.c | 62
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan
---
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 1 +
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 4
4
This patch series add several newly introduced 32/64-bit vector
instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in
this version. Coding style issues are fixed in this version.
Lijun Pan (7):
target/ppc: Introduce Power ISA 3.1 flag
target/ppc: add byte-reverse br[dwh
> On Jun 15, 2020, at 11:12 AM, Richard Henderson
> wrote:
>
> On 6/12/20 8:55 PM, Lijun Pan wrote:
>> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
>> VA-form.
>> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-
> On Jun 15, 2020, at 12:36 PM, Cédric Le Goater wrote:
>
> Hello,
>
> On 6/13/20 6:20 AM, Lijun Pan wrote:
>> This patch series add several newly introduced 32/64-bit vector
>> instructions in Power ISA 3.1. The newly added instructions are
>> flagged as IS
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan
---
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 24
target/ppc/translate/vmx-impl.inc.c | 2 ++
target/ppc
been fully enabled in QEMU
yet. When Power ISA 3.1 and next generation processor are fully
supported, the flags should be changed.
Lijun Pan (6):
target/ppc: add byte-reverse br[dwh] instructions
target/ppc: add vmulld instruction
targetc/ppc: add vmulh{su}w instructions
target/ppc: add
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan
---
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 14 ++
target/ppc/translate/vmx-impl.inc.c | 6 ++
target/ppc/translate/vmx
Doubleword
Signed-off-by: Lijun Pan
---
target/ppc/helper.h | 8
target/ppc/int_helper.c | 19 +++
target/ppc/translate.c | 3 +++
target/ppc/translate/vmx-impl.inc.c | 15 +++
target/ppc/translate/vmx-ops.inc.c | 15
The prototypes of muls64/mulu64 in host-utils.h should match the
definitions in host-utils.c
Signed-off-by: Lijun Pan
---
include/qemu/host-utils.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 4cd170e6cd
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 1 +
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/target
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan
---
target/ppc/translate.c | 62 ++
1 file changed, 62 insertions
vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
VA-form.
vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
Doubleword VA-form.
Signed-off-by: Lijun Pan
---
v2: move vmsumcudm() to qemu/int128.h as Richard Henderson suggested,
also re
vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
VA-form.
vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
Doubleword VA-form.
Signed-off-by: Lijun Pan
---
disas/ppc.c | 2 ++
include/qemu/host-utils.h
On 04/22/2014 05:21 PM, Marcel Apfelbaum wrote:
On Wed, 2014-04-16 at 22:20 +0800, Jun Li wrote:
Add remove_boot_device_path() function to remove bootindex when hot-unplug
a device. This patch fixed virtio-blk/virtio-net/scsi-disk/scsi-generic device.
So it has fixed bug1086603, ref:
https://bu
Hi list,
Ping, could anyone help to review the following patch. Thank you very
much. The patch url is:
http://lists.nongnu.org/archive/html/qemu-devel/2014-04/msg01431.html
The above link is the version 2 of the patch. The original patch url is:
http://lists.nongnu.org/archive/html/qemu-dev
Hi list,
Ping. Could someone help to review this patch, thank you very much.
The following is the patch url:
http://lists.nongnu.org/archive/html/qemu-devel/2014-04/msg00805.html
On 04/05/2014 12:52 AM, Jun Li wrote:
As the realization of raw shrinking, so when do qcow2 shrinking, do not
ch
On 04/15/2014 12:18 AM, Markus Armbruster wrote:
lijun writes:
Hi Markus,
Really appreciate your review first. I almost a new participant. And
I read other's patches very little. So maybe this patch is duplicate
to one of Marcel's patch. But I really do not know. And I re
On 04/15/2014 02:04 AM, Andreas Färber wrote:
Am 13.04.2014 15:24, schrieb Jun Li:
Add remove_boot_device_path() function to remove bootindex when hot-unplug
a device. This patch fixed virtio-blk/virtio-net/scsi-disk/scsi-generic device.
So it has fixed bug1086603, ref:
https://bugzilla.redhat.
Hi Markus,
Really appreciate your review first. I almost a new participant. And
I read other's patches very little. So maybe this patch is duplicate to
one of Marcel's patch. But I really do not know. And I really don't
copying Marcel's. This is my own analysis. When I modify this issue, I
o
As Eric and Eduardo's suggestions, use is_power_of_2 to check whether
nr_cores
and nr_threads is the power of 2 in function x86_apicid_from_cpu_idx in file
target-i386/topology.h. This check is very simple, I prefer add it in a
function to write a new function. Thanks for Eric and Eduardo.
Best
Hi all,
As qemu core dump cause by "sockets=2,cores=3,threads=2", so add
this patch to check whether cores and threads is a power of 2.
The following is the realization of apicid_from_topo_ids function
in file target-i386/topology.h. It uses shift to get the values of
pkg_id and core_id
Hi all,
when set "-smp" more than 160, qemu will give the following warning:
Warning: Number of SMP cpus requested (161) exceeds the recommended cpus
supported by KVM (160)
As the above warning, when set "-smp 160,sockets=2,cores=3,threads=2",
but find that apic_id(hw/i386/acpi-build.c) is 259
On 12/09/2013 08:17 PM, Stefan Hajnoczi wrote:
On Mon, Dec 09, 2013 at 02:06:21PM +0800, jun muzi wrote:
If mount a local file(disk) in two different dirctories, it is similar to the
network storage. Detecting identical "files" is still a problem.
Such as:
dd if=/dev/zero of=aa bs=1M count=10
m
From: Jun Li
Hi all,
snapshot_blkdev can not consider //root/sn1 and /root/sn1 as the same
file. when file /root/sn1 is the base file, do snapshot using file
//root/sn1, qemu consider it as a new file. So this will rewrite the
base file.
Signed-off-by: Jun Li
--- a/hmp.c2013-11-15 23
From: Jun Li
Hi all,
snapshot_blkdev can not consider //root/sn1 and /root/sn1 as the same
file. When file /root/sn1 is the base file, do snapshot using file
//root/sn1, qemu consider it as a new file. So this will rewrite the
base file.
Signed-off-by: Jun Li
--- a/hmp.c2013-11-15 23
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