Alistair Francis writes:
> I have started on the effort, but I have not finished yet. Adding
> riscv_cpu_is_32bit() was the first step there and I have some more
> patches locally but I don't have anything working yet.
That's awesome. I think waiting until we see what APIs you're developing
for
On Mon, Mar 8, 2021 at 5:10 AM Peter Maydell wrote:
>
> On Sat, 6 Mar 2021 at 16:54, Keith Packard wrote:
> >
> > Peter Maydell writes:
> > > Part of why I asked is that the current RISCV implementation
> > > is just looking at sizeof(target_ulong); but the qemu-system-riscv64
> > > executable
On Sat, 6 Mar 2021 at 16:54, Keith Packard wrote:
>
> Peter Maydell writes:
> > Part of why I asked is that the current RISCV implementation
> > is just looking at sizeof(target_ulong); but the qemu-system-riscv64
> > executable AIUI now supports emulating both "this is a 64 bit
> > guest CPU"
Peter Maydell writes:
> ILP32 for AArch64 is a zombie target -- it is kinda-sorta
> supported in some toolchains but has no support in eg
> the Linux syscall ABI. The semihosting ABI does not implement
> any kind of ILP32 variant -- you can have A32/T32 (AArch32)
> semihosting, where register
On Fri, 5 Mar 2021 at 23:54, Keith Packard wrote:
>
> Peter Maydell writes:
>
> > For semihosting for Arm what matters is "what state is the core
> > in at the point where it makes the semihosting SVC/HLT/etc insn?".
>
> Ok, that means we *aren't* talking about -mabi=ilp32, which is good --
> in
On 3/5/21 3:54 PM, Keith Packard via wrote:
I don't know of any implementation in hardware or software that supports
modifying this value. I'm not sure we need to support this in the
semihosting code for qemu as I'm pretty sure getting qemu to support
dynamic XLEN values would be a large project
Peter Maydell writes:
> For semihosting for Arm what matters is "what state is the core
> in at the point where it makes the semihosting SVC/HLT/etc insn?".
Ok, that means we *aren't* talking about -mabi=ilp32, which is good --
in my current picolibc implementation, the semihosting code uses a
On Fri, 5 Mar 2021 at 20:22, Keith Packard wrote:
>
> Peter Maydell writes:
>
> > Also, you don't seem to have the correct "is the CPU in
> > 32-bit or 64-bit mode" test here: you cannot rely on target_ulong
> > being the right size, you must make a runtime check.
>
> Do you mean whether a dual
Peter Maydell writes:
> Also, you don't seem to have the correct "is the CPU in
> 32-bit or 64-bit mode" test here: you cannot rely on target_ulong
> being the right size, you must make a runtime check.
Do you mean whether a dual aarch64/arm core is in arm or aarch64 mode,
or whether an aarch64
Alex Bennée writes:
> I'm not sure this every worked properly and it's certainly not
> exercised by check-tcg or Peter's semihosting tests. Hoist it into
> it's own helper function and attempt to validate the results in the
> linux-user semihosting test at the least.
The patch is mostly code
On Fri, 5 Mar 2021 at 13:54, Alex Bennée wrote:
>
> I'm not sure this every worked properly and it's certainly not
> exercised by check-tcg or Peter's semihosting tests. Hoist it into
> it's own helper function and attempt to validate the results in the
> linux-user semihosting test at the least.
I'm not sure this every worked properly and it's certainly not
exercised by check-tcg or Peter's semihosting tests. Hoist it into
it's own helper function and attempt to validate the results in the
linux-user semihosting test at the least.
Bug: https://bugs.launchpad.net/bugs/1915925
Cc: Bug
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