On Tue, Sep 17, 2019 at 04:49:56PM -0500, Paul Clarke wrote:
> On 9/17/19 3:46 PM, Richard Henderson wrote:
> > On 9/16/19 1:02 PM, Paul A. Clarke wrote:
> >> From: "Paul A. Clarke"
> >>
> >> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
> >> instructions: mffsce, mffs
On 9/17/19 3:46 PM, Richard Henderson wrote:
> On 9/16/19 1:02 PM, Paul A. Clarke wrote:
>> From: "Paul A. Clarke"
>>
>> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
>> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
>> This patch adds support for
On 9/16/19 1:02 PM, Paul A. Clarke wrote:
> From: "Paul A. Clarke"
>
> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
> This patch adds support for 'mffsce' instruction.
>
> 'mffsce' is identical t
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsce' instruction.
'mffsce' is identical to 'mffs', except that it also clears the exception
enabl
