On 23 December 2013 07:43, Fedorov Sergey s.fedo...@samsung.com wrote:
On 12/20/2013 06:33 PM, Peter Maydell wrote:
This sounds like it could work, though there are some wrinkles for
registers with readfns/writefns -- do we have extra s vs ns read/write
functions, or just one set of functions
On 22 December 2013 01:08, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Sat, Dec 21, 2013 at 12:33 AM, Peter Maydell
peter.mayd...@linaro.org wrote:
On 20 December 2013 14:12, Fedorov Sergey s.fedo...@samsung.com wrote:
I've briefly looked at the v8 ARM ARM. As I can see there is
On 12/22/2013 05:08 AM, Peter Crosthwaite wrote:
On Sat, Dec 21, 2013 at 12:33 AM, Peter Maydell
peter.mayd...@linaro.org wrote:
On 20 December 2013 14:12, Fedorov Sergey s.fedo...@samsung.com wrote:
I've briefly looked at the v8 ARM ARM. As I can see there is no banked
system control
On 12/20/2013 06:33 PM, Peter Maydell wrote:
This sounds like it could work, though there are some wrinkles for
registers with readfns/writefns -- do we have extra s vs ns read/write
functions, or just one set of functions which has to look in env-ns to
figure out whether to use the S or NS
On Sat, Dec 21, 2013 at 12:33 AM, Peter Maydell
peter.mayd...@linaro.org wrote:
On 20 December 2013 14:12, Fedorov Sergey s.fedo...@samsung.com wrote:
I've briefly looked at the v8 ARM ARM. As I can see there is no banked
system control registers in AArch64. Seems the concept is changed to
On 12/19/2013 03:38 PM, Peter Maydell wrote:
On 19 December 2013 07:27, Fedorov Sergey s.fedo...@samsung.com wrote:
Yes, this banking scheme makes state changing events quite heavy. But
maintaining the active copies allows to keep translation table walking code
untouched. I think there is a
On 20 December 2013 14:12, Fedorov Sergey s.fedo...@samsung.com wrote:
I've briefly looked at the v8 ARM ARM. As I can see there is no banked
system control registers in AArch64. Seems the concept is changed to provide
separate registers for each meaningful execution level. Please, correct me
On 12/20/2013 06:33 PM, Peter Maydell wrote:
On 20 December 2013 14:12, Fedorov Sergey s.fedo...@samsung.com wrote:
I've briefly looked at the v8 ARM ARM. As I can see there is no banked
system control registers in AArch64. Seems the concept is changed to provide
separate registers for each
On 12/20/2013 06:38 PM, Fedorov Sergey wrote:
On 12/20/2013 06:33 PM, Peter Maydell wrote:
On 20 December 2013 14:12, Fedorov Sergey s.fedo...@samsung.com wrote:
I've briefly looked at the v8 ARM ARM. As I can see there is no banked
system control registers in AArch64. Seems the concept is
On 19 December 2013 07:27, Fedorov Sergey s.fedo...@samsung.com wrote:
Yes, this banking scheme makes state changing events quite heavy. But
maintaining the active copies allows to keep translation table walking code
untouched. I think there is a trade-off between state changing and
On Thu, Dec 19, 2013 at 9:38 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 December 2013 07:27, Fedorov Sergey s.fedo...@samsung.com wrote:
Yes, this banking scheme makes state changing events quite heavy. But
maintaining the active copies allows to keep translation table walking code
On 12/19/2013 04:44 PM, Peter Crosthwaite wrote:
On Thu, Dec 19, 2013 at 9:38 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 December 2013 07:27, Fedorov Sergey s.fedo...@samsung.com wrote:
Yes, this banking scheme makes state changing events quite heavy. But
maintaining the active
On Thu, Dec 19, 2013 at 11:39 PM, Fedorov Sergey s.fedo...@samsung.com wrote:
On 12/19/2013 04:44 PM, Peter Crosthwaite wrote:
On Thu, Dec 19, 2013 at 9:38 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 19 December 2013 07:27, Fedorov Sergey s.fedo...@samsung.com wrote:
Yes, this
On 19 December 2013 14:01, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Thu, Dec 19, 2013 at 11:39 PM, Fedorov Sergey s.fedo...@samsung.com
wrote:
Banked system control registers have two copies, one Secure and one
Non-secure.
Ok fair enough. I will wager though that sooner or
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov s.fedo...@samsung.com wrote:
Banked coprocessor registers are switched on two cases:
1) Entering or leaving CPU monitor mode with SCR.NS bit set;
2) Setting SCR.NS bit not from CPU monitor mode
Coprocessor register banking is done similar to CPU
On 12/19/2013 08:37 AM, Peter Crosthwaite wrote:
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov s.fedo...@samsung.com wrote:
Banked coprocessor registers are switched on two cases:
1) Entering or leaving CPU monitor mode with SCR.NS bit set;
2) Setting SCR.NS bit not from CPU monitor mode
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