Hi,
I mostly agree with everything said, but I'd like to add some thoughts tp the
pot.
I think it's important to understand that that a product that coverts clusters
to
virtual MP could be designed with different requirements in mind.
We are working on a research project that represents clust
> But how often will the virtual CPUs need the same page and is there any
> other shared resource other than memory? I don't know how independent
> each CPU is. Though in side discussions, everyone agrees with you, I
> haven't seen numbers to convince my gut. If page only needs to be
> faulted b
> The only solution I can imagine being even vaguely worthwhile is a running
> user-mode qemu on top of a native openmozix system.
Probably if you want to run a distributed SMP-style sytem using QEmu, the most
effective approach is going to be running OpenMosix *in* QEmu, on multiple
hosts.
Sad
On Tuesday 17 May 2005 21:41, Joe Batt wrote:
> On Tue, 2005-05-17 at 21:21 +0100, Paul Brook wrote:
> > > What inter processor synchronization issues are there? Could you take
> > > this a step further and use processes on different machines for each
> > > processor? (There are many shared memory
On Tue, 2005-05-17 at 21:21 +0100, Paul Brook wrote:
> > What inter processor synchronization issues are there? Could you take
> > this a step further and use processes on different machines for each
> > processor? (There are many shared memory implementations to choose
> > from.) Are there so ma
> What inter processor synchronization issues are there? Could you take
> this a step further and use processes on different machines for each
> processor? (There are many shared memory implementations to choose
> from.) Are there so many resources shared
> between the CPUs to make this a ridic
Quoting Fabrice Bellard <[EMAIL PROTECTED]> :
> SMP est definitely possible in QEMU - a few days of work are
> necessary to add the missing generic support and an x86
> implementation...
ok.
> but currently I prefer to work an other topics.
>
ok.
So, perhaps in the next releases?
--
On Sat, 2005-05-14 at 14:16 +0200, Fabrice Bellard wrote:
...
> 2) The first implementation would use a cycle counter to schedule
> between CPUs. Is it interesting to go further and to use a host thread
> for each guest CPU at the expense of more locking overhead ?
What inter processor synchroni
I guess you'd really want to simulate multiple CPUs with multiple host
threads. One of the additional problems could then be memory/cache
coherency.
I'm not sure how much of a problem this would be in practice. If both host
and guest require the same (or no) explicit SMP memory barriert it's not a
SMP est definitely possible in QEMU - a few days of work are necessary to
add the missing generic support and an x86 implementation... but currently
I prefer to work an other topics.
Just for your information, some choices need to be made:
1) Do the CPUs share the same translation cache ?
This c
On 14 May 2005, at 14:16, Fabrice Bellard wrote:
1) Do the CPUs share the same translation cache ?
2) The first implementation would use a cycle counter to schedule
between CPUs. Is it interesting to go further and to use a host
thread for each guest CPU at the expense of more locking overhead
Blue Swirl wrote:
Hi,
The architecture used in sparc target (sun4m) supports SMP up to a
maximum of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*),
it would be easy to add the missing interprocessor interrupts, per-CPU
counters and atomic instructions. It would also be simple to add
On Saturday 14 May 2005 10:37, Blue Swirl wrote:
> Hi,
>
> The architecture used in sparc target (sun4m) supports SMP up to a maximum
> of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*), it would be
> easy to add the missing interprocessor interrupts, per-CPU counters and
> atomic inst
Hi,
The architecture used in sparc target (sun4m) supports SMP up to a maximum
of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*), it would be
easy to add the missing interprocessor interrupts, per-CPU counters and
atomic instructions. It would also be simple to add the prom function
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