On Tue, 7 Dec 2021 at 15:49, Damien Hedde wrote:
>
>
>
> On 12/7/21 16:45, Peter Maydell wrote:
> > On Tue, 7 Dec 2021 at 15:24, Peter Maydell wrote:
> >> The bug is a bug in any case and we'll fix it, it's just a
> >> question of whether it meets the bar to go into 6.2, which is
> >> hopefully
On 12/7/21 16:45, Peter Maydell wrote:
On Tue, 7 Dec 2021 at 15:24, Peter Maydell wrote:
The bug is a bug in any case and we'll fix it, it's just a
question of whether it meets the bar to go into 6.2, which is
hopefully going to have its final RC tagged today. If this
patch had arrived a
On Tue, 7 Dec 2021 at 15:24, Peter Maydell wrote:
> The bug is a bug in any case and we'll fix it, it's just a
> question of whether it meets the bar to go into 6.2, which is
> hopefully going to have its final RC tagged today. If this
> patch had arrived a week ago then the bar would have been
>
> -Original Message-
> From: Peter Maydell
...
> On Tue, 7 Dec 2021 at 15:18, Brian Cain wrote:
> > Peter Maydell wrote:
> > > I won't try to put this into 6.2 unless you have a common guest
> > > that runs into this bug.
>
> > I know that Qualcomm encounters this issue with its
On Tue, 7 Dec 2021 at 15:18, Brian Cain wrote:
> Peter Maydell wrote:
> > I won't try to put this into 6.2 unless you have a common guest
> > that runs into this bug.
> I know that Qualcomm encounters this issue with its hypervisor
> (https://github.com/quic/gunyah-hypervisor). Apologies for
On 12/7/21 15:21, Peter Maydell wrote:
On Tue, 7 Dec 2021 at 09:44, Damien Hedde wrote:
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when
> -Original Message-
> From: Qemu-devel
> On Behalf Of Peter Maydell
...
> On Tue, 7 Dec 2021 at 09:44, Damien Hedde
> wrote:
> >
> > According to the "Arm Generic Interrupt Controller Architecture
> > Specification GIC architecture version 3 and 4" (version G: page 345
> > for aarch64
On Tue, 7 Dec 2021 at 09:44, Damien Hedde wrote:
>
> According to the "Arm Generic Interrupt Controller Architecture
> Specification GIC architecture version 3 and 4" (version G: page 345
> for aarch64 or 509 for aarch32):
> LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
>
On Tue, 7 Dec 2021 at 13:05, Damien Hedde wrote:
> On 12/7/21 13:45, Philippe Mathieu-Daudé wrote:
> > On 12/7/21 10:44, Damien Hedde wrote:
> >> According to the "Arm Generic Interrupt Controller Architecture
> >> Specification GIC architecture version 3 and 4" (version G: page 345
> >> for
On 12/7/21 13:45, Philippe Mathieu-Daudé wrote:
On 12/7/21 10:44, Damien Hedde wrote:
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when
On 12/7/21 10:44, Damien Hedde wrote:
> According to the "Arm Generic Interrupt Controller Architecture
> Specification GIC architecture version 3 and 4" (version G: page 345
> for aarch64 or 509 for aarch32):
> LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
> ICH_HCR.EOIcount is
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