device config header (blue swirl)
v5 - v6:
- PCI config space fixes (isaku)
- remove CONFIG_AHCI from x86 default configs (paul brook)
- use snprintf (blue swirl)
- add generic PCI config file (paul brook)
- build ahci on all PCI platforms (paul brook)
Alexander Graf (11):
ide: split ide
Due to popular request, this patch moves pieces that are successfully identified
as PATA only to a new file called pata.c.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |2 +-
hw/ide/core.c | 144 +--
hw/ide/internal.h |3
On 26.11.2010, at 22:58, Andreas Färber wrote:
Am 25.11.2010 um 08:35 schrieb Alexander Graf:
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
I'm confused by the subject: Are you positive that PReP is little
On 27.11.2010, at 00:00, Andreas Färber wrote:
Am 25.11.2010 um 08:35 schrieb Alexander Graf:
The way we're currently modeling mmio is too simplified. We assume that
every device has the same endianness as the target CPU. In reality,
most devices are little endian (all PCI and ISA ones I'm
the following patches now:
Alexander Graf (10):
ide: split ide command interpretation off
ide: fix whitespace gap in ide_exec_cmd
ide: add DMA hooks to bus ops
pci: add storage class for sata
pci: add ich7 pci id
ahci: add ahci emulation
ahci: add -drive support
On 27.11.2010, at 20:00, Peter Maydell peter.mayd...@linaro.org wrote:
On 26 November 2010 16:34, wolfgang mueller wolfg...@acm.org wrote:
In this case is it possible to do the introductionary talk of the workshop
with a QEMU overview.
People are here interested in QEMU CPU (and evtl.
On 28.11.2010, at 01:17, Nathan Froyd wrote:
On Fri, Nov 26, 2010 at 01:26:31AM +0100, François Revol wrote:
the people we are addressing and we would like to bring together is from
the QEMU emulation community.
We are interested in running different ISAs mainly under Linux and Windows
Frederic,
On 28.11.2010, at 09:20, Frédéric Pétrot wrote:
Hi there,
IMHO someone from code sourcery would be great, as they (Paul Brooks in the
older versions, it seems that Nathan is now taking over) are contributing
most of the ARM emulation stuff.
We may also have both talks
On 28.11.2010, at 09:12, Gleb Natapov wrote:
On Thu, Nov 25, 2010 at 08:35:41AM +0100, Alexander Graf wrote:
The way we're currently modeling mmio is too simplified. We assume that
every device has the same endianness as the target CPU. In reality,
most devices are little endian (all PCI
On 28.11.2010, at 16:59, Jan Kiszka wrote:
From: Jan Kiszka jan.kis...@siemens.com
Xen target bits in qemu are intended for x86. Let the build system
reflect this and avoid useless building/linking for other targets.
Not sure I understand the split. Xen is x86 only, yes. But why split it
On 29.11.2010, at 13:44, Jan Kiszka wrote:
Am 29.11.2010 13:40, Alexander Graf wrote:
On 29.11.2010, at 13:30, Jan Kiszka wrote:
Am 29.11.2010 13:24, Alexander Graf wrote:
On 28.11.2010, at 16:59, Jan Kiszka wrote:
From: Jan Kiszka jan.kis...@siemens.com
Xen target bits in qemu
On 23.11.2010, at 20:51, anthony.per...@citrix.com wrote:
From: Anthony PERARD anthony.per...@citrix.com
Hi all,
Here is the V7 of the patch series that adds Xen device model support in QEMU.
The change made on it since the v6:
- I introduce a patch from Alexander Graf to add
On 29.11.2010, at 07:43, Frédéric Pétrot wrote:
Nathan Froyd a écrit :
On Sun, Nov 28, 2010 at 09:20:25AM +0100, Frédéric Pétrot wrote:
IMHO someone from code sourcery would be great, as they (Paul Brooks in
the
older versions, it seems that Nathan is now taking over) are contributing
On 29.11.2010, at 15:27, Jan Kiszka wrote:
Am 29.11.2010 15:15, Alexander Graf wrote:
On 29.11.2010, at 13:44, Jan Kiszka wrote:
Am 29.11.2010 13:40, Alexander Graf wrote:
On 29.11.2010, at 13:30, Jan Kiszka wrote:
Am 29.11.2010 13:24, Alexander Graf wrote:
On 28.11.2010, at 16
On 29.11.2010, at 16:10, Anthony PERARD wrote:
On Mon, 29 Nov 2010, Alexander Graf wrote:
On 23.11.2010, at 20:51, anthony.per...@citrix.com wrote:
From: Anthony PERARD anthony.per...@citrix.com
Hi all,
Here is the V7 of the patch series that adds Xen device model support
On 23.11.2010, at 20:51, anthony.per...@citrix.com wrote:
From: Anthony PERARD anthony.per...@citrix.com
With MapCache, we can handle a 64b target, even with a 32b host/qemu.
So, we need to have target_phys_addr_t to 64bits.
Signed-off-by: Anthony PERARD anthony.per...@citrix.com
---
On 29.11.2010, at 17:06, Anthony PERARD wrote:
On Mon, 29 Nov 2010, Alexander Graf wrote:
On 29.11.2010, at 16:10, Anthony PERARD wrote:
On Mon, 29 Nov 2010, Alexander Graf wrote:
On 23.11.2010, at 20:51, anthony.per...@citrix.com wrote:
From: Anthony PERARD anthony.per
On 29.11.2010, at 18:49, Anthony Liguori wrote:
On 11/29/2010 11:37 AM, Attila Sukosd wrote:
Hi,
I guess it should be abstract enough to support multiple back-ends, be it a
kernel driver or through libusb?
Is this something that should just live in libusb?
If what libusb presented
On 29.11.2010, at 18:42, Anthony Liguori wrote:
Hi,
0.13 was a mess of a release (largely due to my lack of time) and I'd like to
get us back onto a predictable schedule.
Here's what I propose:
12/6 - fork off stable-0.14 tree; simultaneously release qemu-0.14.0-rc0
For the
On 29.11.2010, at 20:29, Anthony Liguori wrote:
On 11/29/2010 12:10 PM, Alexander Graf wrote:
On 29.11.2010, at 18:42, Anthony Liguori wrote:
Hi,
0.13 was a mess of a release (largely due to my lack of time) and I'd like
to get us back onto a predictable schedule.
Here's what I
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Because we don't depend on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |1 +
Makefile.target |3 ---
hw/usb
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 23 ++-
1 files changed, 2 insertions(+), 21 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 0e287bd..7b75d3f 100644
missing conversion
- make endian choice be an enum
Alexander Graf (15):
exec: introduce endianness swapped mmio
Add endianness as io mem parameter
Make simple io mem handler endian aware
dbdma: Make little endian
pci-host: Delegate bswap to mmio layer
uninorth: Get rid of bswap
e1000
, this patch only introduces the helper framework
but doesn't allow the registering code to set its endianness yet.
Signed-off-by: Alexander Graf ag...@suse.de
---
v0 - v1:
- don't restrict to big endian targets
- move constants to enum
---
cpu-common.h |8 +++-
exec.c | 123
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc4xx_pci.c | 17 ++---
1 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index f2ecece..f62f1f9 100644
As an alternative to the 3 individual handlers, there is also a simplified
io mem hook function. To be consistent, let's add an endianness parameter
there too.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/apb_pci.c |3 ++-
hw/pci_host.c | 12
hw/unin_pci.c |6
on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |1 +
Makefile.target |1 -
hw/e1000.c | 11 ++-
3 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/Makefile.objs b
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Because we don't depend on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |1 +
Makefile.target |3 ---
hw
-by: Alexander Graf ag...@suse.de
---
hw/dec_pci.c |6 ++-
hw/grackle_pci.c |6 ++-
hw/pci_host.c| 105 ++---
hw/pci_host.h|6 +--
hw/ppce500_pci.c |6 ++-
hw/unin_pci.c| 18 ++---
6 files changed, 46 insertions(+), 101
There's no need to bswap once we correctly set the mmio to be little endian.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/unin_pci.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index f2e440e..5f15058 100644
--- a/hw/unin_pci.c
On 01.12.2010, at 11:21, Anthony PERARD wrote:
On Mon, 29 Nov 2010, Alexander Graf wrote:
On 29.11.2010, at 15:27, Jan Kiszka wrote:
Am 29.11.2010 15:15, Alexander Graf wrote:
On 29.11.2010, at 13:44, Jan Kiszka wrote:
Am 29.11.2010 13:40, Alexander Graf wrote:
On 29.11.2010
This patch converts the ISA MMIO bridge code to always use little endian mmio.
All bswap code that existed was only there to convert from native cpu
endianness to little endian ISA devices.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/bonito.c|4 +-
hw/gt64xxx.c
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/heathrow_pic.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index 390b63c..b19b754 100644
--- a/hw
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc_prep.c | 38 +++---
1 files changed, 3 insertions(+), 35 deletions(-)
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 80f5db6
The device is only used on big endian systems, but always byte swaps. That's
a very good indicator that it's actually a little endian device ;-).
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/mac_dbdma.c |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/hw
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/versatile_pci.c | 14 +-
1 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 3baad96..cc8f9f8
On 01.12.2010, at 14:17, Kevin Wolf wrote:
Am 01.12.2010 14:09, schrieb Stefan Hajnoczi:
On Fri, Nov 26, 2010 at 7:17 PM, Alexander Graf ag...@suse.de wrote:
Just some cosmetic suggestions.
@@ -2716,6 +2736,12 @@ static void ide_init1(IDEBus *bus, int unit
From: Roland Elek elek.rol...@gmail.com
I modified ide_identify() to include the zero-based queue length
value in word 75, and set bit 8 in word 76 to signal NCQ support
in the identify data for AHCI SATA drives.
Signed-off-by: Roland Elek elek.rol...@gmail.com
---
hw/ide/core.c |7
This patch enables AHCI for all machines supporting PCI.
Signed-off-by: Alexander Graf ag...@suse.de
---
default-configs/pci.mak |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/default-configs/pci.mak b/default-configs/pci.mak
index c74a99f..33fc073 100644
--- a/default
The ATA command interpretation code can be used for PATA and SATA
interfaces alike. So let's split it out into a separate function.
Signed-off-by: Alexander Graf ag...@suse.de
---
v6 - v7:
- use bus instead of opaque (stefanha)
---
hw/ide/core.c | 20 ++--
hw/ide
Due to popular request, this patch moves pieces that are successfully identified
as PATA only to a new file called pata.c.
Signed-off-by: Alexander Graf ag...@suse.de
---
v6 - v7:
- stick to new IDEBusOps (stefanha, kwolf)
---
Makefile.objs |2 +-
hw/ide/core.c | 144
We need a PCI ID for our new AHCI adapter. I just picked an ICH-7M
because that's the one built into the first Macbooks.
This patch adds a PCI ID define for an ICH-7 AHCI adapter.
Signed-off-by: Alexander Graf ag...@suse.de
---
v3 - v4:
- add ICH7 instead of ICH7M (herbszt)
v4 - v5
This patch adds the storage sata class id.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/pci_ids.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 82cba7e..ea3418c 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -15,6 +15,7
This patch adds an emulation layer for an ICH-7M AHCI controller. For now
this controller does not do IDE legacy emulation. It is a pure AHCI controller.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- rename IDEExtender to IDEBusOps and make a pointer (kraxel)
- make dma hooks
From: Roland Elek elek.rol...@gmail.com
We need to hook into some of the core IDE functionality for AHCI. To
do that, the easiest way is to make explicit functions calls be implicit
through a function call struct.
Signed-off-by: Roland Elek elek.rol...@gmail.com
Signed-off-by: Alexander Graf ag
Now that we have the function split out, we have to reindent it.
In order to increase the readability of the actual functional change,
this is split out.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/core.c | 734
1 files changed
- osx 10.5.0 works as of this version
- use non-raid ich7 ahci (herbszt)
- reflect normal ich7 in pci dump
- stick to new IDEBusOps (stefanha, kwolf)
- stefan's ahci comments
Alexander Graf (8):
ide: split ide command interpretation off
ide: fix whitespace gap in ide_exec_cmd
ide
For DMA operations, we need to hook into even more IDE functionality.
This patch adds the respective hooking points, allowing us to handle
SG lists ourselves in the AHCI code.
Signed-off-by: Roland Elek elek.rol...@gmail.com
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- make
On 24.11.2010, at 12:44, Gerd Hoffmann wrote:
On 11/23/10 15:34, Alexander Graf wrote:
This patch adds support for AHCI emulation. I have tested and verified it
works
in Linux, OpenBSD, Windows Vista and Windows 7.
Also seabios ;)
http://cgit.freedesktop.org/~kraxel/seabios/log/?h=ahci
Xen work only for
this type of target.
You can find a git tree here:
git://xenbits.xen.org/people/aperard/qemu-dm.git qemu-dm-v8
Very nice patch set :).
Signed-off-by: Alexander Graf ag...@suse.de
Alex
On 02.12.2010, at 00:40, Alexander Graf wrote:
On 01.12.2010, at 18:39, anthony.per...@citrix.com wrote:
From: Anthony PERARD anthony.per...@citrix.com
Hi all,
Here is the V8 of the patch series that adds Xen device model support in
QEMU.
The change mades on it since the v7
On 02.12.2010, at 11:43, Gerd Hoffmann wrote:
On 12/02/10 00:29, Alexander Graf wrote:
On 24.11.2010, at 12:44, Gerd Hoffmann wrote:
On 11/23/10 15:34, Alexander Graf wrote:
This patch adds support for AHCI emulation. I have tested and verified it
works
in Linux, OpenBSD, Windows
On 05.12.2010, at 17:25, Blue Swirl wrote:
'info tlb' didn't show correct information for PAE mode and
x86_64 long mode.
Implement the missing modes. Also print NX bit for PAE and long modes.
Fix off-by-one error in 32 bit mode mask.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
Hi Vandeir,
On 06.12.2010, at 11:49, Vandeir Eduardo wrote:
Hi guys,
I have a KVM guest machine, lets name it VMTEST,
using an iSCSI LUN as a virtio device. Something like this:
disk type='block' device='disk'
driver name='qemu' type='raw' cache='none'/
source
On 06.12.2010, at 19:38, Blue Swirl wrote:
On Mon, Dec 6, 2010 at 11:12 AM, Alexander Graf ag...@suse.de wrote:
On 05.12.2010, at 17:25, Blue Swirl wrote:
'info tlb' didn't show correct information for PAE mode and
x86_64 long mode.
Implement the missing modes. Also print NX bit
ping?
On 25.11.2010, at 08:20, Alexander Graf wrote:
I get a warning on a signed comparison with an unsigned variable, so
let's make the variable signed and be happy.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/kvm.c |2 +-
1 files changed, 1 insertions(+), 1 deletions
The device is only used on big endian systems, but always byte swaps. That's
a very good indicator that it's actually a little endian device ;-).
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/mac_dbdma.c |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/hw
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 23 ++-
1 files changed, 2 insertions(+), 21 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 9e2500a..6d2cf99 100644
As an alternative to the 3 individual handlers, there is also a simplified
io mem hook function. To be consistent, let's add an endianness parameter
there too.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/apb_pci.c |3 ++-
hw/pci_host.c | 12
hw/unin_pci.c |6
There's no need to bswap once we correctly set the mmio to be little endian.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/unin_pci.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index f2e440e..5f15058 100644
--- a/hw/unin_pci.c
, this patch only introduces the helper framework
but doesn't allow the registering code to set its endianness yet.
Signed-off-by: Alexander Graf ag...@suse.de
---
v0 - v1:
- don't restrict to big endian targets
- move constants to enum
---
cpu-common.h |8 +++-
exec.c | 123
:
git://repo.or.cz/qemu/agraf.git qemu-endian-fix-v2
v0-v1:
- make LE targets compile
- add one missing conversion
- make endian choice be an enum
v1 - v2:
- rebase (this thing bitrots _fast_!)
Alexander Graf (15):
exec: introduce endianness swapped mmio
Add endianness as io mem
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/versatile_pci.c | 14 +-
1 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 3baad96..cc8f9f8
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc_prep.c | 38 +++---
1 files changed, 3 insertions(+), 35 deletions(-)
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 80f5db6
This patch converts the ISA MMIO bridge code to always use little endian mmio.
All bswap code that existed was only there to convert from native cpu
endianness to little endian ISA devices.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/bonito.c|4 +-
hw/gt64xxx.c
on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |1 +
Makefile.target |1 -
hw/e1000.c | 11 ++-
3 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/Makefile.objs b
-by: Alexander Graf ag...@suse.de
---
hw/dec_pci.c |6 ++-
hw/grackle_pci.c |6 ++-
hw/pci_host.c| 105 ++---
hw/pci_host.h|6 +--
hw/ppce500_pci.c |6 ++-
hw/unin_pci.c| 18 ++---
6 files changed, 46 insertions(+), 101
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Because we don't depend on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |1 +
Makefile.target |3 ---
hw/usb
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Because we don't depend on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |1 +
Makefile.target |3 ---
hw
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/heathrow_pic.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index 390b63c..b19b754 100644
--- a/hw
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc4xx_pci.c | 17 ++---
1 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index f2ecece..f62f1f9 100644
We need a PCI ID for our new AHCI adapter. I just picked an ICH-7M
because that's the one built into the first Macbooks.
This patch adds a PCI ID define for an ICH-7 AHCI adapter.
Signed-off-by: Alexander Graf ag...@suse.de
---
v3 - v4:
- add ICH7 instead of ICH7M (herbszt)
v4 - v5
This patch enables AHCI for all machines supporting PCI.
Signed-off-by: Alexander Graf ag...@suse.de
---
default-configs/pci.mak |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/default-configs/pci.mak b/default-configs/pci.mak
index d700b3c..0471efb 100644
--- a/default
From: Roland Elek elek.rol...@gmail.com
I modified ide_identify() to include the zero-based queue length
value in word 75, and set bit 8 in word 76 to signal NCQ support
in the identify data for AHCI SATA drives.
Signed-off-by: Roland Elek elek.rol...@gmail.com
---
hw/ide/core.c |7
From: Sebastian Herbszt herb...@gmx.de
Set SATA Mode Select to AHCI in the Address Map Register.
Signed-off-by: Sebastian Herbszt herb...@gmx.de
---
hw/ide/ahci.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 7e7aa89..2ef03ed
From: Sebastian Herbszt herb...@gmx.de
Set pci revision id to 0x01.
Signed-off-by: Sebastian Herbszt herb...@gmx.de
---
hw/ide/ahci.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 2ef03ed..fdfc011 100644
--- a/hw/ide/ahci.c
+++
The IDE core doesn't care about BMDMA blocking IRQs from getting submitted,
so let's reflect that in the code and make IRQ blocking fully transparent.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/core.c |6 --
hw/ide/internal.h |4 ++--
hw/ide/pci.c | 44
Every device that can do PCI should also be able to do IDE. So let's move
the IDE definitions over to pci.mak.
Signed-off-by: Alexander Graf ag...@suse.de
---
default-configs/arm-softmmu.mak |1 -
default-configs/i386-softmmu.mak |3 ---
default-configs/mips-softmmu.mak
The bmdma header definitions currently reside in generic code, but only PCI
specific code should know about BMDMA internals. So let's move the definitions
and everything using them out to pci.h.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/internal.h | 27
The ATA command interpretation code can be used for PATA and SATA
interfaces alike. So let's split it out into a separate function.
Signed-off-by: Alexander Graf ag...@suse.de
---
v6 - v7:
- use bus instead of opaque (stefanha)
---
hw/ide/core.c | 20 ++--
hw/ide
on the fly
- reimplement immediate dma rw
- add safety net for busy engine
- adjust ahci code for new DMA framework
- move ide core+pci to pci.mak
- add sebastian's config space patches
Alexander Graf (10):
ide: split ide command interpretation off
ide: fix whitespace gap in ide_exec_cmd
This patch adds the storage sata class id.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/pci_ids.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 82cba7e..ea3418c 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -15,6 +15,7
Now that we have the function split out, we have to reindent it.
In order to increase the readability of the actual functional change,
this is split out.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/core.c | 734
1 files changed
The ATA core is currently heavily intertwined with BMDMA code. Let's loosen
that a bit, so we can happily replace the DMA backend with different
implementations.
Signed-off-by: Alexander Graf ag...@suse.de
---
v7 - v8:
- rewrite as DMA ops
---
hw/ide/cmd646.c |6 +-
hw/ide/core.c
This patch adds an emulation layer for an ICH-7M AHCI controller. For now
this controller does not do IDE legacy emulation. It is a pure AHCI controller.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- rename IDEExtender to IDEBusOps and make a pointer (kraxel)
- make dma hooks
On 08.12.2010, at 15:26, Stefan Hajnoczi wrote:
On Wed, Dec 8, 2010 at 12:13 PM, Alexander Graf ag...@suse.de wrote:
@@ -486,8 +440,8 @@ void ide_dma_error(IDEState *s)
ide_transfer_stop(s);
s-error = ABRT_ERR;
s-status = READY_STAT | ERR_STAT;
-ide_dma_set_inactive(s-bus
Kevin Wolf wrote:
Am 09.12.2010 16:48, schrieb Alexander Graf:
+static void ncq_cb(void *opaque, int ret)
+{
+NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;
+IDEState *ide_state;
+
+if (ret 0) {
+/* XXX error */
+}
Missing error
Stefan Hajnoczi wrote:
On Wed, Dec 8, 2010 at 12:13 PM, Alexander Graf ag...@suse.de wrote:
+struct AHCIDevice {
+IDEBus port;
+int port_no;
+uint32_t port_state;
+uint32_t finished;
+AHCIPortRegs port_regs;
+struct AHCIState *hba;
+uint8_t *lst
On 10.12.2010, at 13:37, Markus Armbruster wrote:
Alexander Graf ag...@suse.de writes:
On 21.11.2010, at 13:37, Blue Swirl wrote:
On Fri, Nov 19, 2010 at 2:56 AM, Alexander Graf ag...@suse.de wrote:
So far we have C preprocessor defines for target and host config
options, but we're
On 11.12.2010, at 23:33, Blue Swirl wrote:
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
CC: Alexander Graf ag...@suse.de
Signed-off-by: Blue Swirl blauwir...@gmail.com
Acked-by: Alexander Graf ag...@suse.de
Alex
We hook into transfer_start and immediately call the end function
for ahci. This means that everything needs to be in place for the
end function when we start the transfer, so let's move the function
down to where all state is in place.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide
The ATA command interpretation code can be used for PATA and SATA
interfaces alike. So let's split it out into a separate function.
Signed-off-by: Alexander Graf ag...@suse.de
---
v6 - v7:
- use bus instead of opaque (stefanha)
---
hw/ide/core.c | 20 ++--
hw/ide
We need a PCI ID for our new AHCI adapter. I just picked an ICH-9
because that's the one in the Q35 chipset.
This patch adds a PCI ID define for an ICH-9 AHCI adapter.
Signed-off-by: Alexander Graf ag...@suse.de
---
v3 - v4:
- add ICH7 instead of ICH7M (herbszt)
v4 - v5:
- rename
From: Roland Elek elek.rol...@gmail.com
I modified ide_identify() to include the zero-based queue length
value in word 75, and set bit 8 in word 76 to signal NCQ support
in the identify data for AHCI SATA drives.
Signed-off-by: Roland Elek elek.rol...@gmail.com
---
hw/ide/core.c |7
)
- add error reporting for ncq (stefanha)
- replace hw_error with DPRINTF (stefanha)
- move sg generation to sg users
- fix off-by-one in sglist interpretation
- make background engine work (queued commands)
- use ICH9 instead of ICH7 (aliguori)
- update to new APIs
Alexander Graf (9
The ATA core is currently heavily intertwined with BMDMA code. Let's loosen
that a bit, so we can happily replace the DMA backend with different
implementations.
Signed-off-by: Alexander Graf ag...@suse.de
---
v7 - v8:
- rewrite as DMA ops
v8 - v9:
- fold in: split out irq setting
This patch enables AHCI for all machines supporting PCI.
Signed-off-by: Alexander Graf ag...@suse.de
---
default-configs/pci.mak |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/default-configs/pci.mak b/default-configs/pci.mak
index d700b3c..0471efb 100644
--- a/default
This patch adds the storage sata class id.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/pci_ids.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 82cba7e..ea3418c 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -15,6 +15,7
Now that we have the function split out, we have to reindent it.
In order to increase the readability of the actual functional change,
this is split out.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/core.c | 734
1 files changed
From: Sebastian Herbszt herb...@gmx.de
Set SATA Mode Select to AHCI in the Address Map Register.
Signed-off-by: Sebastian Herbszt herb...@gmx.de
---
hw/ide/ahci.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index f937a92..8ae236a
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