On Sun, Jun 10, 2012 at 11:26 AM, Max Filippov wrote:
> Changes in v2:
> - add Peter's patch to this series
> - rebase to the current master
> - remove HELPER_CFLAGS from target-xtensa/Makefile.objs
Grrr, sent from wrong directory, sorry. v3 to come.
> Max Filippov (2):
&
Changes in v3:
- add Peter's patch to this series
- rebase to the current master
- actually remove HELPER_CFLAGS from target-xtensa/Makefile.objs
Max Filippov (2):
target-xtensa: add attributes to helper functions
target-xtensa: switch to AREG0-free mode
Peter Portante (1):
target-x
From: Peter Portante
Signed-off-by: Peter Portante
Signed-off-by: Max Filippov
---
target-xtensa/xtensa-semi.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
index b7c8c34..1c8a19e 100644
--- a/target-xtensa
Mark exception generating functions 'noreturn' and pure constant
functions as such.
Signed-off-by: Max Filippov
---
target-xtensa/helper.h | 16
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h
ind
Add env parameter to every helper function that needs it, update
'configure' script.
Signed-off-by: Max Filippov
---
configure |2 +-
target-xtensa/Makefile.objs |2 -
target-xtensa/helper.h | 54 ++--
target-xtensa/op_helper.
Mark exception generating functions 'noreturn' and pure constant
functions as such.
Signed-off-by: Max Filippov
---
target-xtensa/helper.h | 16
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h
ind
> In target-i386/translate.c there are this instructions:
> int op, f, val;
> op = (b >> 3) & 7;
> f = (b >> 1) & 3;
> if ((b & 1) == 0)
> ot = OT_BYTE;
> else
> ot = dflag + OT_WORD;
> What does this code do??
It extracts some useful subfields from one-byte opcodes, e.g. op is
the arithmetic
From: Lluís Vilanova
Provides a file naming scheme consistent with other targets.
Signed-off-by: Lluís Vilanova
Signed-off-by: Max Filippov
---
target-xtensa/{helpers.h => helper.h} |0
target-xtensa/op_helper.c |2 +-
target-xtensa/translate.c |
tb_invalidate_phys_page_range,
which is incorrect in system emulation mode.
To fix it use guest TLB/MMU to translate virtual address to physical
address.
However the guest may not have virtual-to-physical mapping at the moment
of IBREAKA/LEND change, thus this fix is not 100% accurate.
Signed-off-by: Max Filippov
- add testcase announcement;
- add global symbols for individual tests;
- add host-debug-* makefile target.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile |3 +++
tests/tcg/xtensa/macros.inc | 17 +
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git
ilanova (1):
target-xtensa: Move helpers.h to helper.h
Max Filippov (3):
target-xtensa: improve unit tests debugging
target-xtensa: add test for LEND invalidation
target-xtensa: fix tb invalidation for IBREAK and LOOP
exec-all.h|1
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_loop.S | 25 +
1 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/tests/tcg/xtensa/test_loop.S b/tests/tcg/xtensa/test_loop.S
index a5ea933..9ebc18d 100644
--- a/tests/tcg/xtensa/test_loop.S
+++ b/tests
apping at the moment
>> of IBREAKA/LEND change, thus this fix is not 100% accurate.
>>
>> Signed-off-by: Max Filippov
>> ---
>> exec-all.h | 1 +
>> exec.c | 9 ++---
>> target-xtensa/op_helper.c | 29 +++
B
and reuse most of breakpoint_invalidate() code to invalidate TB at that
physical address.
This series is extracted from my recent xtensa pull request, build of
usermode targets is fixed.
[1] http://lists.gnu.org/archive/html/qemu-devel/2012-03/msg03572.html
Max Filippov (4):
exec: pr
tb_invalidate_phys_page_range,
which is incorrect in system emulation mode.
To fix it use guest TLB/MMU to translate virtual address to physical
address.
However the guest may not have virtual-to-physical mapping at the moment
of IBREAKA/LEND change, thus this fix is not 100% accurate.
Signed-off-by: Max Filippov
Allow TB invalidation by its physical address, extract implementation
from the breakpoint_invalidate function.
Signed-off-by: Max Filippov
---
exec-all.h |1 +
exec.c |9 ++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/exec-all.h b/exec-all.h
index fa7bdfe
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_break.S | 34 ++
1 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/tests/tcg/xtensa/test_break.S b/tests/tcg/xtensa/test_break.S
index 8a8db80..7574cbe 100644
--- a/tests/tcg/xtensa/test_break.S
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_loop.S | 50 ++
1 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/tests/tcg/xtensa/test_loop.S b/tests/tcg/xtensa/test_loop.S
index a5ea933..5cead47 100644
--- a/tests/tcg/xtensa
> Could someone help me to confirm that I understand how the QEMU cross page
> boundary checking correctly or not? Below is the source code I am looking at,
>
> static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
> {
>
> if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_
>> s->pc is updated each time a byte of code is fetched, when an instruction
>> is fully decoded s->pc points to the first byte of the next instruction. I
>> see
>> that it only makes difference when a branching instruction ends exactly at
>> a page boundary. In this case (s->pc - 1) prevents from
On Thu, Apr 12, 2012 at 1:04 AM, Peter Maydell wrote:
> On 11 April 2012 22:00, Max Filippov wrote:
>> 陳韋任 :
>>> Doesn't a tb spanning guest pages have above problem? I mean what if the
>>> guest page 2 is changed? In this case, the execution flow jump from t
>> This series strips down my Xtensa QOM'ification patch from the
>> qom-cpu-others.v1
>> RFC series, avoiding the XtensaConfig vs. subclass problem and taking care
>> not to introduce "klass", including in the header file.
>>
>> I've tested this with the dc232b semihosting test image.
>
> BTW, is
Hello Max,
This series strips down my Xtensa QOM'ification patch from the qom-cpu-others.v1
RFC series, avoiding the XtensaConfig vs. subclass problem and taking care
not to introduce "klass", including in the header file.
I've tested this with the dc232b semihosting test image.
Please review a
>> Doesn't a tb spanning guest pages have above problem? I mean what if the
>> guest page 2 is changed? In this case, the execution flow jump from tb.a to
>> tb.b. It seems it may have the same problem as above to me.
>
> I agree. I see that only i386 and m68k TBs may cross page boundary.
> Maybe
Färber (3):
target-xtensa: QOM'ify CPU
target-xtensa: QOM'ify CPU reset
target-xtensa: Start QOM'ifying CPU init
Lluís Vilanova (1):
target-xtensa: Move helpers.h to helper.h
Max Filippov (1):
target-xtensa: improve unit tests debugging
Makefile.target
- add testcase announcement;
- add global symbols for individual tests;
- add host-debug-* makefile target.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile |3 +++
tests/tcg/xtensa/macros.inc | 17 +
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git
From: Lluís Vilanova
Provides a file naming scheme consistent with other targets.
Signed-off-by: Lluís Vilanova
Signed-off-by: Max Filippov
---
target-xtensa/helper.h| 39 +++
target-xtensa/helpers.h | 39
From: Andreas Färber
Move XtensaConfig-independent code from cpu_xtensa_init() into a
QOM initfn, as a start.
Signed-off-by: Andreas Färber
Signed-off-by: Max Filippov
---
target-xtensa/cpu.c|9 +
target-xtensa/helper.c |1 -
2 files changed, 9 insertions(+), 1 deletions
From: Andreas Färber
Move code from cpu_state_reset() into QOM xtensa_cpu_reset().
To avoid moving reset_mmu() and dependencies, make it non-static.
Signed-off-by: Andreas Färber
Signed-off-by: Max Filippov
---
target-xtensa/cpu.c| 12 +++-
target-xtensa/cpu.h|1
From: Andreas Färber
Embed CPUXtensaState as first member of XtensaCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber
Signed-off-by: Max Filippov
---
Makefile.target |1 +
target-xtensa/cpu-qom.h | 80
This is Diamond 233L Standard Core Rev.C (LE), implemented through
linux/gdb overlay.
Signed-off-by: Max Filippov
---
Makefile.target|1 +
target-xtensa/core-dc233c.c| 28 ++
target-xtensa/core-dc233c/core-isa.h | 475
On 04/14/2012 03:44 PM, 陳韋任 wrote:
>> I've made a test from the grub multiboot sample, you may find it here:
>> http://jcmvbkbc.spb.ru/git/?p=dumb/qemu-test-kernel.git;a=summary
>>
>> With it I see that an attempt to execute a TB that spans two pages causes
>> an exception when the second page is
Signed-off-by: Max Filippov
---
target-xtensa/core-dc232b.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/core-dc232b.c b/target-xtensa/core-dc232b.c
index 7c03835..804fdef 100644
--- a/target-xtensa/core-dc232b.c
+++ b/target
Signed-off-by: Max Filippov
---
target-xtensa/core-fsf.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/core-fsf.c b/target-xtensa/core-fsf.c
index c11d970..e36b0de 100644
--- a/target-xtensa/core-fsf.c
+++ b/target-xtensa/core
This is Diamond 233L Standard Core Rev.C (LE), implemented through
linux/gdb overlay.
Signed-off-by: Max Filippov
---
Makefile.target|1 +
target-xtensa/core-dc233c.c| 55
target-xtensa/core-dc233c/core-isa.h | 475
Fix accidently broken translation of two looping instructions
by decoupling it from SR write handler. Add unit tests.
Max Filippov (2):
target-xtensa: fix LOOPNEZ/LOOPGTZ translation
target-xtensa: add tests for LOOPNEZ and LOOPGTZ
target-xtensa/translate.c|2 +-
tests/tcg/xtensa
Translation of LOOP instructions used to call LEND SR write handler to
update LEND and invalidate relevant TBs. Now that LEND SR write handler
ends TB, LOOPNEZ and LOOPGTZ generate wrong code (same as for simple
LOOP). Fix it by calling wsr_lend helper directly.
Signed-off-by: Max Filippov
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_loop.S | 36
1 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/tests/tcg/xtensa/test_loop.S b/tests/tcg/xtensa/test_loop.S
index 5cead47..1c240e8 100644
--- a/tests/tcg/xtensa/test_loop.S
> Skip ROM or kernel loading and TCG init for qtest.
>
> For Xtensa there is no default board and the
What is the use case of the default board?
Are there any specific requirements for it?
--
Thanks.
-- Max
On Wed, Apr 18, 2012 at 12:27 AM, Peter Maydell
wrote:
> On 17 April 2012 21:19, Blue Swirl wrote:
>> On Mon, Apr 16, 2012 at 21:58, Max Filippov wrote:
>>> What is the use case of the default board?
>>
>> If an architecture has multiple boards, the default board c
On Thu, Apr 19, 2012 at 5:33 PM, Richard Henderson wrote:
> The xtensa-test image generates a sra_i32 with count 0x40.
Richard, what is that xtensa-test image that you refer?
> Whether this is accident of tcg constant propagation or
> originating directly from the instruction stream is immateria
00644
--- a/xtensa-semi.c
+++ b/xtensa-semi.c
@@ -30,7 +30,6 @@
#include
#include
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helpers.h"
#include "qemu-log.h"
Regarding xtensa part: it does not apply now that helpers.h is renamed to
helper.h
Otherwise Acked-by: Max Filippov
--
Thanks.
-- Max
On 04/26/2012 12:31 AM, Peter Portante wrote:
On 04/25/2012 04:07 PM, Max Filippov wrote:
On 04/25/2012 10:47 PM, Peter Portante wrote:
Signed-off-by: Peter Portante
---
hw/spapr_hcall.c | 1 -
xtensa-semi.c | 1 -
2 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/hw/spapr_hcall.c b
l.
Thanks.
-- Max
The following changes since commit 99c7f87826337fa81f2f0f9baa9ca0a44faf90e9:
input: send kbd+mouse events only to running guests. (2012-02-17 11:02:55
-0600)
are available in the git repository at:
git://jcmvbkbc.spb.ru/dumb/qemu-xtensa.git xtensa
Max Filippov (12):
tar
Fill debug configuration from overlay definitions in the DEBUG_SECTION.
Add DEBUG_SECTION to DC232B and FSF cores.
Signed-off-by: Max Filippov
---
target-xtensa/core-dc232b.c |1 +
target-xtensa/core-fsf.c |1 +
target-xtensa/overlay_tool.h |5 +
3 files changed, 7
DEBUGCAUSE SR holds information about the most recent debug exception.
See ISA, 4.7.7 for more details.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 15 +++
target-xtensa/translate.c |6 ++
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a
for more details.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 12
target-xtensa/helper.c| 41 +
target-xtensa/helpers.h |2 +
target-xtensa/op_helper.c | 62 +
target-xtensa
In case of BP_STOP_BEFORE_ACCESS watchpoint check_watchpoint intends to
signal EXCP_DEBUG exception on exit from cpu loop, but later overwrites
exception code by the cpu_resume_from_signal call.
Use cpu_loop_exit with BP_STOP_BEFORE_ACCESS watchpoints.
Signed-off-by: Max Filippov
---
exec.c
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and
BREAK.N instructions and IBREAK breakpoints.
IBREAK breakpoint address is considered constant for TB lifetime.
On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated.
Signed-off-by: Max Filippov
---
target-xtensa
.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |6 +
target-xtensa/translate.c | 49 -
2 files changed, 54 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index a18072b..92441e3 100644
--- a/target
> Thanks, incidentally:
>
> Am 18.02.2012 18:11, schrieb Max Filippov:
> > Signed-off-by: Max Filippov
>
> Reviewed-by is missing. Care to fix on your branch?
Done.
> I don't see any Rb/Ab on the others as well, please check.
A haven't got any other Rb/Ab.
Thanks.
-- Max
Make cpu_watchpoint_insert accept watchpoints of any power-of-two size
up to the target page size.
Signed-off-by: Max Filippov
---
exec.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/exec.c b/exec.c
index ed091f3..80560fa 100644
--- a/exec.c
+++ b/exec.c
@@ -1443,7
TLB_TEMPLATE macro specifies TLB geometry in the core configuration.
Make TLB_TEMPLATE available for region protection core variants,
defining 1 way ITLB and DTLB with 8 entries each.
Signed-off-by: Max Filippov
---
target-xtensa/overlay_tool.h | 18 --
1 files changed, 16
According to ISA, 3.5.4, third opcode byte should not be fetched for
2-byte instructions.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index c81450d
Signed-off-by: Max Filippov
---
exec.c | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/exec.c b/exec.c
index b81677a..f105b43 100644
--- a/exec.c
+++ b/exec.c
@@ -3289,9 +3289,15 @@ static void watch_mem_write(void *opaque,
target_phys_addr_t addr
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile |1 +
tests/tcg/xtensa/test_break.S | 223 +
2 files changed, 224 insertions(+), 0 deletions(-)
create mode 100644 tests/tcg/xtensa/test_break.S
diff --git a/tests/tcg/xtensa/Makefile b
Command dumps valid ITLB and DTLB entries.
Signed-off-by: Max Filippov
---
hmp-commands.hx|2 +-
monitor.c |4 +-
target-xtensa/cpu.h|1 +
target-xtensa/helper.c | 67
4 files changed, 71 insertions(+), 3
ailable in the git repository at:
> git://jcmvbkbc.spb.ru/dumb/qemu-xtensa.git xtensa
>
> Max Filippov (12):
> target-xtensa: define TLB_TEMPLATE for MMU-less cores
> target-xtensa: implement info tlb monitor command
> target-xtensa: fetch 3rd opcode byte only when nee
> Provides a file naming scheme consistent with other targets.
Thanks, applied to the xtensa tree.
-- Max
Hello guys.
I'm running qemu on x86_64 host.
It's clean build from git sources dated 2011.05.19, commit
1fddfba129f5435c80eda14e8bc23fdb888c7187
I have the following output from "log trace,op,out_asm":
Trace 0x4000a310 [d0026c92]
OP:
0xd0c0
movi_i32 tmp1,$0xfff4
add_i32 tmp0,ar9,
> > Please note how the current instruction in gdb differ from what
> > was said in OUT. This lea corrupts stack pointer and the next
> > callq generates segfault.
> > Could please anyone familiar with TCG take a look at this, or
> > suggest where I should look myself?
>
> You don't say which targ
> > Hello guys.
> >
> > I'm running qemu on x86_64 host.
> > It's clean build from git sources dated 2011.05.19, commit
> > 1fddfba129f5435c80eda14e8bc23fdb888c7187
> > I have the following output from "log trace,op,out_asm":
> >
> > Trace 0x4000a310 [d0026c92]
> > OP:
> > 0xd0c0
> > mo
> Here are my rules of thumb for generating code where the code
> generated might change based on some bit of CPU state:
>
> When you are generating code, if the code you generate will
> change based on the contents of something in the CPUState struct,
> then the bit of CPUState you are looking at
> That should be the last block matching the address in the
> log output if you run *under gdb* with -d out_asm.
This is the case.
> BTW you say this is a clean build, but as far as I could see
> it looks like your emulated target is not part of standard
> QEMU; it seems to have a register named
> Here are my rules of thumb for generating code where the code
> generated might change based on some bit of CPU state:
>
> When you are generating code, if the code you generate will
> change based on the contents of something in the CPUState struct,
> then the bit of CPUState you are looking at
tch;
- implement all memory protection options;
- GDB support.
Max Filippov (31):
target-xtensa: add target stubs
target-xtensa: add target to the configure script
target-xtensa: implement disas_xtensa_insn
target-xtensa: implement narrow instructions
target-xtensa: implement RT0 gr
Signed-off-by: Max Filippov
---
Makefile.target |2 +
arch_init.c |2 +
arch_init.h |1 +
cpu-exec.c|2 +
elf.h |2 +
hw/xtensa_pic.c | 38 ++
target-xtensa/cpu.h
Signed-off-by: Max Filippov
---
configure| 12 +++-
default-configs/xtensa-softmmu.mak |1 +
default-configs/xtensaeb-softmmu.mak |1 +
3 files changed, 13 insertions(+), 1 deletions(-)
create mode 100644 default-configs/xtensa-softmmu.mak
create
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 67 +++
target-xtensa
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 54 +
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xte
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 164
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 110 -
1 files changed, 109 insertions
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 60 -
1 files changed, 59 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 1fe212d..52a76e1 100644
--- a/target-xtensa/translate.c
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
Signed-off-by: Max Filippov
---
v1 -> v2 changes:
- do not encode LITBASE value into TB;
---
target-xtensa/cpu.h |6 ++
target-xtensa/helper.c|1 +
target-xte
Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.
Note that simcalls that accept buffer addresses expect virtual addresses.
Signed-off-by: Max Filippov
looping code verifies actual LEND value.
Invalidation may be avoided for the TB at the new LEND address if
there's a way to associate LEND address with TB at compilation time and
later verify that it doesn't change.
Signed-off-by: Max Filippov
---
v1 -> v2 changes:
- chain TBs ar
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.
Signed-off-by: Max Filippov
---
v1 -> v2 changes:
- don't reset env->halted in xtensa_advance_ccount;
- clean up cases in the do_interrupt switch;
---
hw/x
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push "used register
watermark" beyond its current level. Used register watermark is reset on
instructions that change WINDOW_BASE/WINDOW_START SRs.
Signed-off-by: Max Filippov
---
v1 -> v2 changes:
- dc-&g
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.
Signed-off-by: Max Filippov
---
v1 -> v2 changes:
- use ALIGNED_ONLY to handle unaligned memory access;
---
target-xtensa/helper.c|4 ++-
target-xte
This is Diamond 232L Standard Core Rev.B (LE).
Signed-off-by: Max Filippov
---
Makefile.target |1 +
hw/xtensa_dc232b.c| 112
target-xtensa/gdb-config-dc232b.c | 261 +
target-xtensa/helper.c
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |2 ++
target-xtensa/helper.c| 18 --
target-xtensa/translate.c |1
Add myself as target-xtensa and DC232B maintainer.
Signed-off-by: Max Filippov
---
MAINTAINERS | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6115e4e..c7395df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -115,6 +115,12 @@ M
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.
Signed-off-by: Max Filippov
---
v1 -> v2 changes:
- fix nsa helper implementation;
---
target-xtensa/cpu.h |4 +
target-xtensa/helpers.h |2 +
target-xtensa/op_helper.c |
All operations in this group are no-ops, because there are no delayed
side effects.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 31 ++-
1 files changed, 30 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa
NEG and ABS are the only members of RT0 group.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 2ff5838..dcbc0ae 100644
--- a/target
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 161 +
1 files
- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |1 +
target-xtensa/translate.c | 89 +
2
Group SNM0 (indirect jumps and calls).
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 43 +++
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index c6ebb3d..400c995
es or uregnames are considered valid.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |7 ++
target-xtensa/translate.c | 47 +++-
2 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.
Signed-off-by: Max Filippov
---
cpu-exec.c|6 +++
target-xtensa/cpu.h | 67
target-xtensa/helper.c| 37 +++-
target-xtensa
Signed-off-by: Max Filippov
---
hw/xtensa_sample.c|1 +
target-xtensa/cpu.h |2 ++
target-xtensa/translate.c |7 +++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index 9f7733b..c2ad48a 100644
--- a/hw
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 53 -
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 29
3 files changed, 77 insertions(+), 6 deletions(-)
diff --git a/target-xtensa/cpu.h b
Sample board and sample CPU core are used for debug and may be used for
development of custom SoC emulators.
This board has two fixed size memory regions for DTCM and ITCM and
variable length SRAM region.
Signed-off-by: Max Filippov
---
Makefile.target|1 +
hw/xtensa_sample.c | 105
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 95 +++
inline GDB does not support operations with privileged SRs
(see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support
may be enabled, see NUM_CORE_REGS comment in the gdbstub.c
Signed-off-by: Max Filippov
---
gdbstub.c | 96 +++
targ
separate patch.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |8 ++
target-xtensa/helper.c|1 +
target-xtensa/helpers.h |8 ++
target-xtensa/op_helper.c | 185 +
target-xtensa/translate.c | 144
- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 56 -
target-xtensa/helper.c
Hi.
Current git head build with trace enabled is broken by the commit
c572f23a3e7180dbeab5e86583e43ea2afed6271 hw/9pfs: Introduce tracing for 9p pdu
handlers.
Error messages:
In file included from trace.c:2:0:
trace.h: In function ‘trace_v9fs_attach’:
trace.h:2850:9: error: too many arguments f
Cache options must be enabled for the cores that have cache to avoid
illegal instruction exceptions.
Signed-off-by: Max Filippov
---
target-xtensa/overlay_tool.h |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/overlay_tool.h b/target-xtensa
This includes opcodes from disabled features and those marked reserved in the
ISA.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 1688bb2..792eff1
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